2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2010-2016 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
21 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
22 # TODO: Implement support for detecting various bus errors.
24 import sigrokdecode as srd
33 - 'START' (START condition)
34 - 'START REPEAT' (Repeated START condition)
35 - 'ADDRESS READ' (Slave address, read)
36 - 'ADDRESS WRITE' (Slave address, write)
37 - 'DATA READ' (Data, read)
38 - 'DATA WRITE' (Data, write)
39 - 'STOP' (STOP condition)
42 - 'BITS' (<pdata>: list of data/address bits and their ss/es numbers)
44 <pdata> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
45 command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
46 For example, a slave address field could be 0x51 (instead of 0xa2).
47 For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None.
50 # CMD: [annotation-type-index, long annotation, short annotation]
52 'START': [0, 'Start', 'S'],
53 'START REPEAT': [1, 'Start repeat', 'Sr'],
54 'STOP': [2, 'Stop', 'P'],
55 'ACK': [3, 'ACK', 'A'],
56 'NACK': [4, 'NACK', 'N'],
57 'BIT': [5, 'Bit', 'B'],
58 'ADDRESS READ': [6, 'Address read', 'AR'],
59 'ADDRESS WRITE': [7, 'Address write', 'AW'],
60 'DATA READ': [8, 'Data read', 'DR'],
61 'DATA WRITE': [9, 'Data write', 'DW'],
64 class Decoder(srd.Decoder):
68 longname = 'Inter-Integrated Circuit'
69 desc = 'Two-wire, multi-master, serial bus.'
74 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
75 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
78 {'id': 'address_format', 'desc': 'Displayed slave address format',
79 'default': 'shifted', 'values': ('shifted', 'unshifted')},
82 ('start', 'Start condition'),
83 ('repeat-start', 'Repeat start condition'),
84 ('stop', 'Stop condition'),
87 ('bit', 'Data/address bit'),
88 ('address-read', 'Address read'),
89 ('address-write', 'Address write'),
90 ('data-read', 'Data read'),
91 ('data-write', 'Data write'),
92 ('warnings', 'Human-readable warnings'),
95 ('bits', 'Bits', (5,)),
96 ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
97 ('warnings', 'Warnings', (10,)),
100 ('address-read', 'Address read'),
101 ('address-write', 'Address write'),
102 ('data-read', 'Data read'),
103 ('data-write', 'Data write'),
110 self.samplerate = None
111 self.ss = self.es = self.ss_byte = -1
115 self.is_repeat_start = 0
116 self.state = 'FIND START'
117 self.pdu_start = None
121 def metadata(self, key, value):
122 if key == srd.SRD_CONF_SAMPLERATE:
123 self.samplerate = value
126 self.out_python = self.register(srd.OUTPUT_PYTHON)
127 self.out_ann = self.register(srd.OUTPUT_ANN)
128 self.out_binary = self.register(srd.OUTPUT_BINARY)
129 self.out_bitrate = self.register(srd.OUTPUT_META,
130 meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
132 def putx(self, data):
133 self.put(self.ss, self.es, self.out_ann, data)
135 def putp(self, data):
136 self.put(self.ss, self.es, self.out_python, data)
138 def putb(self, data):
139 self.put(self.ss, self.es, self.out_binary, data)
141 def handle_start(self, pins):
142 self.ss, self.es = self.samplenum, self.samplenum
143 self.pdu_start = self.samplenum
145 cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
146 self.putp([cmd, None])
147 self.putx([proto[cmd][0], proto[cmd][1:]])
148 self.state = 'FIND ADDRESS'
149 self.bitcount = self.databyte = 0
150 self.is_repeat_start = 1
154 # Gather 8 bits of data plus the ACK/NACK bit.
155 def handle_address_or_data(self, pins):
159 # Address and data are transmitted MSB-first.
163 # Remember the start of the first data/address bit.
164 if self.bitcount == 0:
165 self.ss_byte = self.samplenum
167 # Store individual bits and their start/end samplenumbers.
168 # In the list, index 0 represents the LSB (I²C transmits MSB-first).
169 self.bits.insert(0, [sda, self.samplenum, self.samplenum])
170 if self.bitcount > 0:
171 self.bits[1][2] = self.samplenum
172 if self.bitcount == 7:
173 self.bitwidth = self.bits[1][2] - self.bits[2][2]
174 self.bits[0][2] += self.bitwidth
176 # Return if we haven't collected all 8 + 1 bits, yet.
177 if self.bitcount < 7:
182 if self.state == 'FIND ADDRESS':
183 # The READ/WRITE bit is only in address bytes, not data bytes.
184 self.wr = 0 if (self.databyte & 1) else 1
185 if self.options['address_format'] == 'shifted':
189 if self.state == 'FIND ADDRESS' and self.wr == 1:
190 cmd = 'ADDRESS WRITE'
192 elif self.state == 'FIND ADDRESS' and self.wr == 0:
195 elif self.state == 'FIND DATA' and self.wr == 1:
198 elif self.state == 'FIND DATA' and self.wr == 0:
202 self.ss, self.es = self.ss_byte, self.samplenum + self.bitwidth
204 self.putp(['BITS', self.bits])
207 self.putb([bin_class, bytes([d])])
209 for bit in self.bits:
210 self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]])
212 if cmd.startswith('ADDRESS'):
213 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
214 w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R']
215 self.putx([proto[cmd][0], w])
216 self.ss, self.es = self.ss_byte, self.samplenum
218 self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
219 '%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
221 # Done with this packet.
222 self.bitcount = self.databyte = 0
224 self.state = 'FIND ACK'
226 def get_ack(self, pins):
228 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
229 cmd = 'NACK' if (sda == 1) else 'ACK'
230 self.putp([cmd, None])
231 self.putx([proto[cmd][0], proto[cmd][1:]])
232 # There could be multiple data bytes in a row, so either find
233 # another data byte or a STOP condition next.
234 self.state = 'FIND DATA'
236 def handle_stop(self, pins):
239 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
240 bitrate = int(1 / elapsed * self.pdu_bits)
241 self.put(self.ss_byte, self.samplenum, self.out_bitrate, bitrate)
244 self.ss, self.es = self.samplenum, self.samplenum
245 self.putp([cmd, None])
246 self.putx([proto[cmd][0], proto[cmd][1:]])
247 self.state = 'FIND START'
248 self.is_repeat_start = 0
255 if self.state == 'FIND START':
256 # Wait for a START condition (S): SCL = high, SDA = falling.
257 self.handle_start(self.wait({0: 'h', 1: 'f'}))
258 elif self.state == 'FIND ADDRESS':
259 # Wait for a data bit: SCL = rising.
260 self.handle_address_or_data(self.wait({0: 'r'}))
261 elif self.state == 'FIND DATA':
262 # Wait for any of the following conditions (or combinations):
263 # a) Data sampling of receiver: SCL = rising, and/or
264 # b) START condition (S): SCL = high, SDA = falling, and/or
265 # c) STOP condition (P): SCL = high, SDA = rising
266 pins = self.wait([{0: 'r'}, {0: 'h', 1: 'f'}, {0: 'h', 1: 'r'}])
268 # Check which of the condition(s) matched and handle them.
270 self.handle_address_or_data(pins)
271 elif self.matched[1]:
272 self.handle_start(pins)
273 elif self.matched[2]:
274 self.handle_stop(pins)
275 elif self.state == 'FIND ACK':
276 # Wait for a data/ack bit: SCL = rising.
277 self.get_ack(self.wait({0: 'r'}))