2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include "libsigrok-internal.h"
38 HARD_DATA_CHECK_SUM = 0x00,
46 FREQUENCY_REG0 = 0x30,
54 TRIGGER_STATUS0 = 0x40,
64 TRIGGER_COUNT0 = 0x50,
67 TRIGGER_LEVEL0 = 0x55,
72 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
73 RAMSIZE_TRIGGERBAR_ADDRESS1,
74 RAMSIZE_TRIGGERBAR_ADDRESS2,
83 ENABLE_DELAY_TIME0 = 0x7a,
86 ENABLE_INSERT_DATA0 = 0x80,
93 TRIGGER_ADDRESS0 = 0x90,
101 STOP_ADDRESS0 = 0x9b,
105 READ_RAM_STATUS = 0xa0,
108 static int g_trigger_status[9] = { 0 };
109 static int g_trigger_count = 1;
110 static int g_filter_status[8] = { 0 };
111 static int g_filter_enable = 0;
113 static int g_freq_value = 1;
114 static int g_freq_scale = FREQ_SCALE_MHZ;
115 static int g_memory_size = MEMORY_SIZE_8K;
116 static int g_ramsize_triggerbar_addr = 2 * 1024;
117 static int g_triggerbar_addr = 0;
118 static int g_compression = COMPRESSION_NONE;
120 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
121 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
125 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
129 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
131 int reg0 = 0, divisor = 0, reg2 = 0;
134 case FREQ_SCALE_MHZ: /* MHz */
135 if (freq >= 100 && freq <= 200) {
141 if (freq >= 50 && freq < 100) {
147 if (freq >= 10 && freq < 50) {
160 if (freq >= 2 && freq < 10) {
176 case FREQ_SCALE_HZ: /* Hz */
177 if (freq >= 500 && freq < 1000) {
183 if (freq >= 300 && freq < 500) {
184 reg0 = freq * 0.005 * 8;
189 if (freq >= 100 && freq < 300) {
190 reg0 = freq * 0.005 * 16;
199 case FREQ_SCALE_KHZ: /* kHz */
200 if (freq >= 500 && freq < 1000) {
206 if (freq >= 100 && freq < 500) {
212 if (freq >= 50 && freq < 100) {
218 if (freq >= 10 && freq < 50) {
230 if (freq >= 2 && freq < 10) {
247 sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
248 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
249 freq, scale, divisor, reg0, 0x02, reg2);
251 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
252 return -1; /* Divisor maybe? */
254 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
255 return -1; /* 10 / 0.2 */
257 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
258 return -1; /* Always 2 */
260 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
269 * FREQUENCT_REG0 - division factor (?)
270 * FREQUENCT_REG1 - multiplication factor (?)
271 * FREQUENCT_REG4 - clock selection (?)
274 * 0 10MHz 16 1MHz 32 100kHz 48 10kHz 64 1kHz
275 * 1 5MHz 17 500kHz 33 50kHz 49 5kHz 65 500Hz
276 * 2 2.5MHz . . 50 2.5kHz 66 250Hz
280 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
290 static const struct freq_factor f[] = {
291 { 200, FREQ_SCALE_MHZ, 0, 1, 20 },
292 { 150, FREQ_SCALE_MHZ, 0, 1, 15 },
293 { 100, FREQ_SCALE_MHZ, 0, 1, 10 },
294 { 80, FREQ_SCALE_MHZ, 0, 2, 16 },
295 { 50, FREQ_SCALE_MHZ, 0, 2, 10 },
296 { 25, FREQ_SCALE_MHZ, 1, 5, 25 },
297 { 10, FREQ_SCALE_MHZ, 1, 5, 10 },
298 { 1, FREQ_SCALE_MHZ, 16, 5, 5 },
299 { 800, FREQ_SCALE_KHZ, 17, 5, 8 },
300 { 400, FREQ_SCALE_KHZ, 32, 5, 20 },
301 { 200, FREQ_SCALE_KHZ, 32, 5, 10 },
302 { 100, FREQ_SCALE_KHZ, 32, 5, 5 },
303 { 50, FREQ_SCALE_KHZ, 33, 5, 5 },
304 { 25, FREQ_SCALE_KHZ, 49, 5, 25 },
305 { 5, FREQ_SCALE_KHZ, 50, 5, 10 },
306 { 1, FREQ_SCALE_KHZ, 64, 5, 5 },
307 { 500, FREQ_SCALE_HZ, 64, 10, 5 },
308 { 100, FREQ_SCALE_HZ, 68, 5, 8 },
314 for (i = 0; f[i].freq; i++) {
315 if (scale == f[i].scale && freq == f[i].freq)
321 sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
322 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
323 freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
325 if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
328 if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
331 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
334 if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
340 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
341 unsigned int address)
343 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
344 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
345 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
348 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
349 unsigned int address)
351 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
352 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
353 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
356 static void __analyzer_set_compression(libusb_device_handle *devh,
359 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
360 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
363 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
366 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
367 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
370 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
372 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
373 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
374 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
375 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
378 static void analyzer_set_filter(libusb_device_handle *devh)
381 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
382 for (i = 0; i < 8; i++)
383 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
386 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
388 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
389 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
392 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
394 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
395 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
396 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
399 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
403 status = gl_reg_read(devh, DEV_STATUS);
404 if ((status & set) && ((status & unset) == 0))
409 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
413 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
415 for (i = 0; i < 8; i++)
416 (void)gl_reg_read(devh, READ_RAM_STATUS);
419 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
422 return gl_read_bulk(devh, buffer, size);
425 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
427 analyzer_write_status(devh, 3, STATUS_FLAG_20);
428 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
431 SR_PRIV void analyzer_start(libusb_device_handle *devh)
433 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
434 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
435 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
436 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
439 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
443 /* Write_Start_Status */
444 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
445 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
447 /* Start_Config_Outside_Device ? */
448 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
449 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
451 /* SetData_To_Frequence_Reg */
452 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
454 /* SetMemory_Length */
455 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
457 /* Sele_Inside_Outside_Clock */
458 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
460 /* Set_Trigger_Status */
461 for (i = 0; i < 9; i++)
462 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
464 __analyzer_set_trigger_count(devh, g_trigger_count);
466 /* Set_Trigger_Level */
467 gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
468 gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
469 gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
470 gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
472 /* Size of actual memory >> 2 */
473 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
474 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
476 /* Set_Dont_Care_TriggerBar */
477 if (g_triggerbar_addr)
478 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x00);
480 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
483 analyzer_set_filter(devh);
485 /* Set_Enable_Delay_Time */
486 gl_reg_write(devh, 0x7a, 0x00);
487 gl_reg_write(devh, 0x7b, 0x00);
488 analyzer_write_enable_insert_data(devh);
489 __analyzer_set_compression(devh, g_compression);
492 SR_PRIV void analyzer_add_trigger(int channel, int type)
496 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
499 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
502 case TRIGGER_POSEDGE:
503 g_trigger_status[8] = 0x40 | channel;
505 case TRIGGER_NEGEDGE:
506 g_trigger_status[8] = 0x80 | channel;
508 case TRIGGER_ANYEDGE:
509 g_trigger_status[8] = 0xc0 | channel;
517 SR_PRIV void analyzer_add_filter(int channel, int type)
521 if (type != FILTER_HIGH && type != FILTER_LOW)
523 if ((channel & 0xf) >= 8)
526 if (channel & CHANNEL_A)
528 else if (channel & CHANNEL_B)
530 else if (channel & CHANNEL_C)
532 else if (channel & CHANNEL_D)
537 if ((channel & 0xf) >= 4) {
542 g_filter_status[i] |=
543 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
548 SR_PRIV void analyzer_set_trigger_count(int count)
550 g_trigger_count = count;
553 SR_PRIV void analyzer_set_freq(int freq, int scale)
556 g_freq_scale = scale;
559 SR_PRIV void analyzer_set_memory_size(unsigned int size)
561 g_memory_size = size;
564 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
566 g_ramsize_triggerbar_addr = address;
569 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
571 g_triggerbar_addr = address;
574 SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
576 return gl_reg_read(devh, DEV_STATUS);
579 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
581 return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
584 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
586 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
587 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
590 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
592 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
593 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
596 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
598 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
599 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
602 SR_PRIV void analyzer_set_compression(unsigned int type)
604 g_compression = type;
607 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
609 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
612 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
614 analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
617 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
618 void *output, unsigned int output_len)
620 unsigned char *in = input;
621 unsigned char *out = output;
622 unsigned int A, B, C, count;
623 unsigned int written = 0;
625 while (input_len > 0) {
631 if (count > output_len)
640 *out++ = 0; /* Channel D */