2 * This file is part of the sigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
6 * Copyright (C) 2013 Lior Elazary <lelazary@yahoo.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
23 #define LIBSIGROK_HARDWARE_LINK_MSO19_PROTOCOL_H
29 #include "libsigrok.h"
30 #include "libsigrok-internal.h"
32 /* Message logging helpers with driver-specific prefix string. */
33 #define DRIVER_LOG_DOMAIN "mso19: "
34 #define sr_log(l, s, args...) sr_log(l, DRIVER_LOG_DOMAIN s, ## args)
35 #define sr_spew(s, args...) sr_spew(DRIVER_LOG_DOMAIN s, ## args)
36 #define sr_dbg(s, args...) sr_dbg(DRIVER_LOG_DOMAIN s, ## args)
37 #define sr_info(s, args...) sr_info(DRIVER_LOG_DOMAIN s, ## args)
38 #define sr_warn(s, args...) sr_warn(DRIVER_LOG_DOMAIN s, ## args)
39 #define sr_err(s, args...) sr_err(DRIVER_LOG_DOMAIN s, ## args)
41 #define USB_VENDOR "3195"
42 #define USB_PRODUCT "f190"
44 #define NUM_PROBES (1 + 8)
45 #define NUM_TRIGGER_STAGES 4
46 #define TRIGGER_TYPE "01" //the first r/f is used for the whole group
47 #define SERIALCOMM "460800/8n1/flow=2"
48 #define SERIALCONN "/dev/ttyUSB0"
49 #define CLOCK_RATE SR_MHZ(100)
50 #define MIN_NUM_SAMPLES 4
52 #define MSO_TRIGGER_UNKNOWN '!'
53 #define MSO_TRIGGER_UNKNOWN1 '1'
54 #define MSO_TRIGGER_UNKNOWN2 '2'
55 #define MSO_TRIGGER_UNKNOWN3 '3'
56 #define MSO_TRIGGER_WAIT '4'
57 #define MSO_TRIGGER_FIRED '5'
58 #define MSO_TRIGGER_DATAREADY '6'
65 /* Structure for the pattern generator state */
67 /* Pattern generator clock config */
69 /* Buffer start address */
71 /* Buffer end address */
73 /* Pattern generator config */
77 /* Input/output configuration for the samples buffer (?) */
79 /* Number of loops for the pattern generator */
81 /* Bit enable mask for the I/O lines */
85 /* Data structure for the protocol trigger state */
86 struct mso_prototrig {
87 /* Word match buffer */
89 /* Masks for the wordmatch buffer */
91 /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
95 /* Private, per-device-instance driver context. */
100 struct sr_serial_dev_inst *serial;
101 // uint8_t num_sample_rates;
105 uint16_t offset_range;
106 uint64_t limit_samples;
107 uint64_t num_samples;
112 uint8_t la_threshold;
114 uint8_t dso_probe_attn;
116 uint8_t trigger_chan;
117 uint8_t trigger_slope;
118 uint8_t trigger_outsrc;
119 uint8_t trigger_state;
120 uint8_t trigger_holdoff[2];
122 uint8_t la_trigger_mask;
123 double dso_trigger_voltage;
124 uint16_t dso_trigger_width;
125 struct mso_prototrig protocol_trigger;
131 SR_PRIV int mso_parse_serial(const char *iSerial, const char *iProduct,
132 struct dev_context *ctx);
133 SR_PRIV int mso_check_trigger(struct sr_serial_dev_inst *serial,
135 SR_PRIV int mso_reset_adc(struct sr_dev_inst *sdi);
136 SR_PRIV int mso_clkrate_out(struct sr_serial_dev_inst *serial, uint16_t val);
137 SR_PRIV int mso_configure_rate(const struct sr_dev_inst *sdi, uint32_t rate);
138 SR_PRIV int mso_receive_data(int fd, int revents, void *cb_data);
139 SR_PRIV int mso_configure_trigger(const struct sr_dev_inst *sdi);
140 SR_PRIV int mso_configure_threshold_level(const struct sr_dev_inst *sdi);
141 SR_PRIV int mso_read_buffer(struct sr_dev_inst *sdi);
142 SR_PRIV int mso_arm(const struct sr_dev_inst *sdi);
143 SR_PRIV int mso_force_capture(struct sr_dev_inst *sdi);
144 SR_PRIV int mso_dac_out(const struct sr_dev_inst *sdi, uint16_t val);
145 SR_PRIV inline uint16_t mso_calc_raw_from_mv(struct dev_context *devc);
146 SR_PRIV int mso_reset_fsm(struct sr_dev_inst *sdi);
147 SR_PRIV int mso_toggle_led(struct sr_dev_inst *sdi, int state);
149 SR_PRIV int mso_configure_probes(const struct sr_dev_inst *sdi);
150 SR_PRIV void stop_acquisition(const struct sr_dev_inst *sdi);
152 /* bank agnostic registers */
155 /* bank 0 registers */
157 #define REG_TRIGGER 2
158 #define REG_CLKRATE1 9
159 #define REG_CLKRATE2 10
162 /* possibly bank agnostic: */
165 /* bank 2 registers (SPI/I2C protocol trigger) */
166 #define REG_PT_WORD(x) (x)
167 #define REG_PT_MASK(x) (x + 4)
168 #define REG_PT_SPIMODE 8
170 /* bits - REG_CTL1 */
171 #define BIT_CTL1_RESETFSM (1 << 0)
172 #define BIT_CTL1_ARM (1 << 1)
173 #define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
174 #define BIT_CTL1_RESETADC (1 << 6)
175 #define BIT_CTL1_LED (1 << 7)
177 /* bits - REG_CTL2 */
178 #define BITS_CTL2_BANK(x) (x & 0x3)
179 #define BIT_CTL2_SLOWMODE (1 << 5)
187 static const struct rate_map rate_map[] = {
188 { SR_MHZ(200), 0x0205, 0 },
189 { SR_MHZ(100), 0x0105, 0 },
190 { SR_MHZ(50), 0x0005, 0 },
191 { SR_MHZ(20), 0x0303, 0 },
192 { SR_MHZ(10), 0x0308, 0 },
193 { SR_MHZ(5), 0x030c, 0 },
194 { SR_MHZ(2), 0x0330, 0 },
195 { SR_MHZ(1), 0x0362, 0 },
196 { SR_KHZ(500), 0x03c6, 0 },
197 { SR_KHZ(200), 0x07f2, 0 },
198 { SR_KHZ(100), 0x0fe6, 0 },
199 { SR_KHZ(50), 0x1fce, 0 },
200 { SR_KHZ(20), 0x4f86, 0 },
201 { SR_KHZ(10), 0x9f0e, 0 },
202 { SR_KHZ(5), 0x03c7, 0x20 },
203 { SR_KHZ(2), 0x07f3, 0x20 },
204 { SR_KHZ(1), 0x0fe7, 0x20 },
205 { SR_HZ(500), 0x1fcf, 0x20 },
206 { SR_HZ(200), 0x4f87, 0x20 },
207 { SR_HZ(100), 0x9f0f, 0x20 },
210 /* FIXME: Determine corresponding voltages */
211 static const uint16_t la_threshold_map[] = {