2 * This file is part of the sigrok project.
4 * Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
5 * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef LIBSIGROK_HARDWARE_LINK_MSO19_LINK_MSO19_H
22 #define LIBSIGROK_HARDWARE_LINK_MSO19_LINK_MSO19_H
24 /* Message logging helpers with driver-specific prefix string. */
25 #define DRIVER_LOG_DOMAIN "mso-19: "
26 #define sr_log(l, s, args...) sr_log(l, DRIVER_LOG_DOMAIN s, ## args)
27 #define sr_spew(s, args...) sr_spew(DRIVER_LOG_DOMAIN s, ## args)
28 #define sr_dbg(s, args...) sr_dbg(DRIVER_LOG_DOMAIN s, ## args)
29 #define sr_info(s, args...) sr_info(DRIVER_LOG_DOMAIN s, ## args)
30 #define sr_warn(s, args...) sr_warn(DRIVER_LOG_DOMAIN s, ## args)
31 #define sr_err(s, args...) sr_err(DRIVER_LOG_DOMAIN s, ## args)
33 /* Structure for the pattern generator state */
35 /* Pattern generator clock config */
37 /* Buffer start address */
39 /* Buffer end address */
41 /* Pattern generator config */
45 /* Input/output configuration for the samples buffer (?)*/
47 /* Number of loops for the pattern generator */
49 /* Bit enable mask for the I/O lines */
53 /* Data structure for the protocol trigger state */
54 struct mso_prototrig {
55 /* Word match buffer */
57 /* Masks for the wordmatch buffer */
59 /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
63 /* Private, per-device-instance driver context. */
69 // uint8_t num_sample_rates;
73 uint16_t offset_range;
80 uint8_t dso_probe_attn;
82 uint8_t trigger_slope;
83 uint8_t trigger_outsrc;
84 uint8_t trigger_state;
86 uint8_t la_trigger_mask;
87 double dso_trigger_voltage;
88 uint16_t dso_trigger_width;
89 struct mso_prototrig protocol_trigger;
96 #define mso_trans(a, v) \
97 (((v) & 0x3f) | (((v) & 0xc0) << 6) | (((a) & 0xf) << 8) | \
98 ((~(v) & 0x20) << 1) | ((~(v) & 0x80) << 7))
100 const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
101 const char mso_foot[] = { 0x7e };
103 /* bank agnostic registers */
106 /* bank 0 registers */
108 #define REG_TRIGGER 2
109 #define REG_CLKRATE1 9
110 #define REG_CLKRATE2 10
113 /* possibly bank agnostic: */
116 /* bank 2 registers (SPI/I2C protocol trigger) */
117 #define REG_PT_WORD(x) (x)
118 #define REG_PT_MASK(x) (x+4)
119 #define REG_PT_SPIMODE 8
121 /* bits - REG_CTL1 */
122 #define BIT_CTL1_RESETFSM (1 << 0)
123 #define BIT_CTL1_ARM (1 << 1)
124 #define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
125 #define BIT_CTL1_RESETADC (1 << 6)
126 #define BIT_CTL1_LED (1 << 7)
128 /* bits - REG_CTL2 */
129 #define BITS_CTL2_BANK(x) (x & 0x3)
130 #define BIT_CTL2_SLOWMODE (1 << 5)
138 static struct rate_map rate_map[] = {
139 { SR_MHZ(200), 0x0205, 0 },
140 { SR_MHZ(100), 0x0105, 0 },
141 { SR_MHZ(50), 0x0005, 0 },
142 { SR_MHZ(20), 0x0303, 0 },
143 { SR_MHZ(10), 0x0308, 0 },
144 { SR_MHZ(5), 0x030c, 0 },
145 { SR_MHZ(2), 0x0330, 0 },
146 { SR_MHZ(1), 0x0362, 0 },
147 { SR_KHZ(500), 0x03c6, 0 },
148 { SR_KHZ(200), 0x07f2, 0 },
149 { SR_KHZ(100), 0x0fe6, 0 },
150 { SR_KHZ(50), 0x1fce, 0 },
151 { SR_KHZ(20), 0x4f86, 0 },
152 { SR_KHZ(10), 0x9f0e, 0 },
153 { SR_KHZ(5), 0x03c7, 0x20 },
154 { SR_KHZ(2), 0x07f3, 0x20 },
155 { SR_KHZ(1), 0x0fe7, 0x20 },
156 { 500, 0x1fcf, 0x20 },
157 { 200, 0x4f87, 0x20 },
158 { 100, 0x9f0f, 0x20 },
161 /* FIXME: Determine corresponding voltages */
162 static uint16_t la_threshold_map[] = {