2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
38 #define TRIGGER_TYPES "rf"
40 static GSList *device_instances = NULL;
42 // XXX These should be per device
43 static struct ftdi_context ftdic;
44 static uint64_t cur_samplerate = 0;
45 static uint32_t limit_msec = 0;
46 static struct timeval start_tv;
47 static int cur_firmware = -1;
48 static int num_probes = 0;
49 static int samples_per_event = 0;
50 static int capture_ratio = 50;
52 /* Single-pin trigger support. */
53 static uint8_t triggerpin = 1;
54 static uint8_t triggerfall = 0;
56 static uint64_t supported_samplerates[] = {
70 static struct samplerates samplerates = {
74 supported_samplerates,
77 static int capabilities[] = {
87 /* Force the FPGA to reboot. */
88 static uint8_t suicide[] = {
89 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
92 /* Prepare to upload firmware (FPGA specific). */
93 static uint8_t init[] = {
94 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
97 /* Initialize the logic analyzer mode. */
98 static uint8_t logic_mode_start[] = {
99 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
100 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
103 static const char *firmware_files[] = {
104 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
105 "asix-sigma-100.fw", /* 100 MHz */
106 "asix-sigma-200.fw", /* 200 MHz */
107 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
108 "asix-sigma-phasor.fw", /* Frequency counter */
111 static int sigma_read(void *buf, size_t size)
115 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
117 g_warning("ftdi_read_data failed: %s",
118 ftdi_get_error_string(&ftdic));
124 static int sigma_write(void *buf, size_t size)
128 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
130 g_warning("ftdi_write_data failed: %s",
131 ftdi_get_error_string(&ftdic));
132 } else if ((size_t) ret != size) {
133 g_warning("ftdi_write_data did not complete write\n");
139 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
142 uint8_t buf[len + 2];
145 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
146 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
148 for (i = 0; i < len; ++i) {
149 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
150 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
153 return sigma_write(buf, idx);
156 static int sigma_set_register(uint8_t reg, uint8_t value)
158 return sigma_write_register(reg, &value, 1);
161 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
165 buf[0] = REG_ADDR_LOW | (reg & 0xf);
166 buf[1] = REG_ADDR_HIGH | (reg >> 4);
167 buf[2] = REG_READ_ADDR;
169 sigma_write(buf, sizeof(buf));
171 return sigma_read(data, len);
174 static uint8_t sigma_get_register(uint8_t reg)
178 if (1 != sigma_read_register(reg, &value, 1)) {
179 g_warning("Sigma_get_register: 1 byte expected");
186 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
189 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 REG_READ_ADDR | NEXT_REG,
195 REG_READ_ADDR | NEXT_REG,
196 REG_READ_ADDR | NEXT_REG,
200 sigma_write(buf, sizeof(buf));
202 sigma_read(result, sizeof(result));
204 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
205 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
207 /* Not really sure why this must be done, but according to spec. */
208 if ((--*stoppos & 0x1ff) == 0x1ff)
211 if ((*--triggerpos & 0x1ff) == 0x1ff)
217 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
223 /* Send the startchunk. Index start with 1. */
224 buf[0] = startchunk >> 8;
225 buf[1] = startchunk & 0xff;
226 sigma_write_register(WRITE_MEMROW, buf, 2);
229 buf[idx++] = REG_DRAM_BLOCK;
230 buf[idx++] = REG_DRAM_WAIT_ACK;
232 for (i = 0; i < numchunks; ++i) {
233 /* Alternate bit to copy from DRAM to cache. */
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
237 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
239 if (i != (numchunks - 1))
240 buf[idx++] = REG_DRAM_WAIT_ACK;
243 sigma_write(buf, idx);
245 return sigma_read(data, numchunks * CHUNK_SIZE);
248 /* Generate the bitbang stream for programming the FPGA. */
249 static int bin2bitbang(const char *filename,
250 unsigned char **buf, size_t *buf_size)
254 unsigned long offset = 0;
256 uint8_t *compressed_buf, *firmware;
257 uLongf csize, fwsize;
258 const int buffer_size = 65536;
261 uint32_t imm = 0x3f6df2ab;
263 f = fopen(filename, "r");
265 g_warning("fopen(\"%s\", \"r\")", filename);
269 if (-1 == fseek(f, 0, SEEK_END)) {
270 g_warning("fseek on %s failed", filename);
275 file_size = ftell(f);
277 fseek(f, 0, SEEK_SET);
279 compressed_buf = g_malloc(file_size);
280 firmware = g_malloc(buffer_size);
282 if (!compressed_buf || !firmware) {
283 g_warning("Error allocating buffers");
288 while ((c = getc(f)) != EOF) {
289 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
290 compressed_buf[csize++] = c ^ imm;
294 fwsize = buffer_size;
295 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
297 g_free(compressed_buf);
299 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
303 g_free(compressed_buf);
305 *buf_size = fwsize * 2 * 8;
307 *buf = p = (unsigned char *)g_malloc(*buf_size);
310 g_warning("Error allocating buffers");
314 for (i = 0; i < fwsize; ++i) {
315 for (bit = 7; bit >= 0; --bit) {
316 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
317 p[offset++] = v | 0x01;
324 if (offset != *buf_size) {
326 g_warning("Error reading firmware %s "
327 "offset=%ld, file_size=%ld, buf_size=%zd\n",
328 filename, offset, file_size, *buf_size);
336 static int hw_init(char *deviceinfo)
338 struct sigrok_device_instance *sdi;
340 deviceinfo = deviceinfo;
344 /* Look for SIGMAs. */
345 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
346 USB_DESCRIPTION, NULL) < 0)
349 /* Register SIGMA device. */
350 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
351 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
355 device_instances = g_slist_append(device_instances, sdi);
357 /* We will open the device again when we need it. */
358 ftdi_usb_close(&ftdic);
363 static int upload_firmware(int firmware_idx)
369 unsigned char result[32];
370 char firmware_path[128];
372 /* Make sure it's an ASIX SIGMA. */
373 if ((ret = ftdi_usb_open_desc(&ftdic,
374 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
375 g_warning("ftdi_usb_open failed: %s",
376 ftdi_get_error_string(&ftdic));
380 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
381 g_warning("ftdi_set_bitmode failed: %s",
382 ftdi_get_error_string(&ftdic));
386 /* Four times the speed of sigmalogan - Works well. */
387 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
388 g_warning("ftdi_set_baudrate failed: %s",
389 ftdi_get_error_string(&ftdic));
393 /* Force the FPGA to reboot. */
394 sigma_write(suicide, sizeof(suicide));
395 sigma_write(suicide, sizeof(suicide));
396 sigma_write(suicide, sizeof(suicide));
397 sigma_write(suicide, sizeof(suicide));
399 /* Prepare to upload firmware (FPGA specific). */
400 sigma_write(init, sizeof(init));
402 ftdi_usb_purge_buffers(&ftdic);
404 /* Wait until the FPGA asserts INIT_B. */
406 ret = sigma_read(result, 1);
407 if (result[0] & 0x20)
411 /* Prepare firmware. */
412 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
413 firmware_files[firmware_idx]);
415 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
416 g_warning("An error occured while reading the firmware: %s",
421 /* Upload firmare. */
422 sigma_write(buf, buf_size);
426 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
427 g_warning("ftdi_set_bitmode failed: %s",
428 ftdi_get_error_string(&ftdic));
432 ftdi_usb_purge_buffers(&ftdic);
434 /* Discard garbage. */
435 while (1 == sigma_read(&pins, 1))
438 /* Initialize the logic analyzer mode. */
439 sigma_write(logic_mode_start, sizeof(logic_mode_start));
441 /* Expect a 3 byte reply. */
442 ret = sigma_read(result, 3);
444 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
445 g_warning("Configuration failed. Invalid reply received.");
449 cur_firmware = firmware_idx;
454 static int hw_opendev(int device_index)
456 struct sigrok_device_instance *sdi;
459 /* Make sure it's an ASIX SIGMA. */
460 if ((ret = ftdi_usb_open_desc(&ftdic,
461 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
463 g_warning("ftdi_usb_open failed: %s",
464 ftdi_get_error_string(&ftdic));
469 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
472 sdi->status = ST_ACTIVE;
477 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
483 for (i = 0; supported_samplerates[i]; i++) {
484 if (supported_samplerates[i] == samplerate)
487 if (supported_samplerates[i] == 0)
488 return SIGROK_ERR_SAMPLERATE;
490 if (samplerate <= MHZ(50)) {
491 ret = upload_firmware(0);
494 if (samplerate == MHZ(100)) {
495 ret = upload_firmware(1);
498 else if (samplerate == MHZ(200)) {
499 ret = upload_firmware(2);
503 cur_samplerate = samplerate;
504 samples_per_event = 16 / num_probes;
506 g_message("Firmware uploaded");
511 /* Only trigger on single pin supported (in 100-200 MHz modes). */
512 static int configure_probes(GSList *probes)
518 if (cur_samplerate <= MHZ(50)) {
519 g_warning("Trigger support only implemented "
520 "in 100 and 200 MHz mode.");
524 for (l = probes; l; l = l->next) {
525 probe = (struct probe *)l->data;
527 if (!probe->enabled || !probe->trigger)
531 g_warning("Asix Sigma only supports a single pin trigger "
532 "in 100 and 200 MHz mode.");
537 if (probe->trigger[0] == 'f')
542 triggerpin = probe->index - 1;
549 static void hw_closedev(int device_index)
551 device_index = device_index;
553 ftdi_usb_close(&ftdic);
556 static void hw_cleanup(void)
560 static void *hw_get_device_info(int device_index, int device_info_id)
562 struct sigrok_device_instance *sdi;
565 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
566 fprintf(stderr, "It's NULL.\n");
570 switch (device_info_id) {
575 info = GINT_TO_POINTER(16);
580 case DI_TRIGGER_TYPES:
581 info = (char *)TRIGGER_TYPES;
583 case DI_CUR_SAMPLERATE:
584 info = &cur_samplerate;
591 static int hw_get_status(int device_index)
593 struct sigrok_device_instance *sdi;
595 sdi = get_sigrok_device_instance(device_instances, device_index);
602 static int *hw_get_capabilities(void)
607 static int hw_set_configuration(int device_index, int capability, void *value)
609 struct sigrok_device_instance *sdi;
612 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
615 if (capability == HWCAP_SAMPLERATE) {
616 ret = set_samplerate(sdi, *(uint64_t*) value);
617 } else if (capability == HWCAP_PROBECONFIG) {
618 ret = configure_probes(value);
619 } else if (capability == HWCAP_LIMIT_MSEC) {
620 limit_msec = strtoull(value, NULL, 10);
622 } else if (capability == HWCAP_CAPTURE_RATIO) {
623 capture_ratio = strtoull(value, NULL, 10);
625 } else if (capability == HWCAP_PROBECONFIG) {
626 ret = configure_probes((GSList *) value);
635 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
636 * Each event is 20ns apart, and can contain multiple samples.
638 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
639 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
640 * For 50 MHz and below, events contain one sample for each channel,
641 * spread 20 ns apart.
643 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
644 uint16_t *lastsample, int triggerpos, void *user_data)
647 uint16_t samples[65536 * samples_per_event];
648 struct datafeed_packet packet;
649 int i, j, k, l, numpad, tosend;
650 size_t n = 0, sent = 0;
651 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
656 /* Find in which cluster the trigger occured. */
657 if (triggerpos != -1)
658 triggerts = (triggerpos / 7);
661 for (i = 0; i < 64; ++i) {
662 ts = *(uint16_t *) &buf[i * 16];
663 tsdiff = ts - *lastts;
666 /* Pad last sample up to current point. */
667 numpad = tsdiff * samples_per_event - clustersize;
669 for (j = 0; j < numpad; ++j)
670 samples[j] = *lastsample;
675 /* Send samples between previous and this timestamp to sigrok. */
678 tosend = MIN(2048, n - sent);
680 packet.type = DF_LOGIC16;
681 packet.length = tosend * sizeof(uint16_t);
682 packet.payload = samples + sent;
683 session_bus(user_data, &packet);
689 event = (uint16_t *) &buf[i * 16 + 2];
692 /* For each event in cluster. */
693 for (j = 0; j < 7; ++j) {
695 /* For each sample in event. */
696 for (k = 0; k < samples_per_event; ++k) {
699 /* For each probe. */
700 for (l = 0; l < num_probes; ++l)
701 cur_sample |= (!!(event[j] & (1 << (l *
702 samples_per_event + k))))
705 samples[n++] = cur_sample;
709 *lastsample = samples[n - 1];
711 /* Send data up to trigger point (if triggered). */
713 if (i == triggerts) {
715 * Trigger is presumptively only accurate to event, i.e.
716 * for 100 and 200 MHz, where multiple samples are coded
717 * in a single event, the trigger does not match the
720 tosend = (triggerpos % 7) - 3;
723 packet.type = DF_LOGIC16;
724 packet.length = tosend * sizeof(uint16_t);
725 packet.payload = samples;
726 session_bus(user_data, &packet);
731 packet.type = DF_TRIGGER;
734 session_bus(user_data, &packet);
737 /* Send rest of the chunk to sigrok. */
740 packet.type = DF_LOGIC16;
741 packet.length = tosend * sizeof(uint16_t);
742 packet.payload = samples + sent;
743 session_bus(user_data, &packet);
749 static int receive_data(int fd, int revents, void *user_data)
751 struct datafeed_packet packet;
752 const int chunks_per_read = 32;
753 unsigned char buf[chunks_per_read * CHUNK_SIZE];
754 int bufsz, numchunks, curchunk, i, newchunks;
755 uint32_t triggerpos, stoppos, running_msec;
758 uint16_t lastsample = 0;
760 int triggerchunk = -1;
765 /* Get the current position. */
766 sigma_read_pos(&stoppos, &triggerpos);
767 numchunks = stoppos / 512;
769 /* Check if the has expired, or memory is full. */
770 gettimeofday(&tv, 0);
771 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
772 (tv.tv_usec - start_tv.tv_usec) / 1000;
774 if (running_msec < limit_msec && numchunks < 32767)
777 /* Stop acqusition. */
778 sigma_set_register(WRITE_MODE, 0x11);
780 /* Set SDRAM Read Enable. */
781 sigma_set_register(WRITE_MODE, 0x02);
783 /* Get the current position. */
784 sigma_read_pos(&stoppos, &triggerpos);
786 /* Check if trigger has fired. */
787 modestatus = sigma_get_register(READ_MODE);
788 if (modestatus & 0x20) {
789 triggerchunk = triggerpos / 512;
792 /* Download sample data. */
793 for (curchunk = 0; curchunk < numchunks;) {
794 newchunks = MIN(chunks_per_read, numchunks - curchunk);
796 g_message("Downloading sample data: %.0f %%",
797 100.0 * curchunk / numchunks);
799 bufsz = sigma_read_dram(curchunk, newchunks, buf);
803 lastts = *(uint16_t *) buf - 1;
805 /* Decode chunks and send them to sigrok. */
806 for (i = 0; i < newchunks; ++i) {
807 if (curchunk + i == triggerchunk)
808 decode_chunk_ts(buf + (i * CHUNK_SIZE),
809 &lastts, &lastsample,
810 triggerpos & 0x1ff, user_data);
812 decode_chunk_ts(buf + (i * CHUNK_SIZE),
813 &lastts, &lastsample,
817 curchunk += newchunks;
821 packet.type = DF_END;
823 session_bus(user_data, &packet);
828 static int hw_start_acquisition(int device_index, gpointer session_device_id)
830 struct sigrok_device_instance *sdi;
831 struct datafeed_packet packet;
832 struct datafeed_header header;
833 struct clockselect_50 clockselect;
835 uint8_t triggerselect;
836 struct triggerinout triggerinout_conf;
838 session_device_id = session_device_id;
840 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
843 device_index = device_index;
845 /* If the samplerate has not been set, default to 50 MHz. */
846 if (cur_firmware == -1)
847 set_samplerate(sdi, MHZ(50));
849 /* Enter trigger programming mode. */
850 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
852 /* 100 and 200 MHz mode. */
853 if (cur_samplerate >= MHZ(100)) {
854 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
856 triggerselect = (1 << LEDSEL1) | (triggerfall << 3) |
859 /* All other modes. */
860 } else if (cur_samplerate <= MHZ(50)) {
861 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
863 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
866 /* Setup trigger in and out pins to default values. */
867 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
868 triggerinout_conf.trgout_bytrigger = 1;
869 triggerinout_conf.trgout_enable = 1;
871 sigma_write_register(WRITE_TRIGGER_OPTION,
872 (uint8_t *) &triggerinout_conf,
873 sizeof(struct triggerinout));
875 /* Go back to normal mode. */
876 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
878 /* Set clock select register. */
879 if (cur_samplerate == MHZ(200))
880 /* Enable 4 probes. */
881 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
882 else if (cur_samplerate == MHZ(100))
883 /* Enable 8 probes. */
884 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
887 * 50 MHz mode (or fraction thereof). Any fraction down to
888 * 50 MHz / 256 can be used, but is not supported by sigrok API.
890 frac = MHZ(50) / cur_samplerate - 1;
892 clockselect.async = 0;
893 clockselect.fraction = frac;
894 clockselect.disabled_probes = 0;
896 sigma_write_register(WRITE_CLOCK_SELECT,
897 (uint8_t *) &clockselect,
898 sizeof(clockselect));
901 /* Setup maximum post trigger time. */
902 sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 256) / 100);
904 /* Start acqusition. */
905 gettimeofday(&start_tv, 0);
906 sigma_set_register(WRITE_MODE, 0x0d);
908 /* Send header packet to the session bus. */
909 packet.type = DF_HEADER;
910 packet.length = sizeof(struct datafeed_header);
911 packet.payload = &header;
912 header.feed_version = 1;
913 gettimeofday(&header.starttime, NULL);
914 header.samplerate = cur_samplerate;
915 header.protocol_id = PROTO_RAW;
916 header.num_probes = num_probes;
917 session_bus(session_device_id, &packet);
919 /* Add capture source. */
920 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
925 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
927 device_index = device_index;
928 session_device_id = session_device_id;
930 /* Stop acquisition. */
931 sigma_set_register(WRITE_MODE, 0x11);
933 // XXX Set some state to indicate that data should be sent to sigrok
934 // Now, we just wait for timeout
937 struct device_plugin asix_sigma_plugin_info = {
947 hw_set_configuration,
948 hw_start_acquisition,