2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 /* Initialize the logic analyzer mode. */
84 static uint8_t logic_mode_start[] = {
85 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
86 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
89 static const char *firmware_files[] = {
90 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
91 "asix-sigma-100.fw", /* 100 MHz */
92 "asix-sigma-200.fw", /* 200 MHz */
93 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
94 "asix-sigma-phasor.fw", /* Frequency counter */
97 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
101 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
103 sr_err("ftdi_read_data failed: %s",
104 ftdi_get_error_string(&devc->ftdic));
110 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
114 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
116 sr_err("ftdi_write_data failed: %s",
117 ftdi_get_error_string(&devc->ftdic));
118 } else if ((size_t) ret != size) {
119 sr_err("ftdi_write_data did not complete write.");
125 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
126 struct dev_context *devc)
129 uint8_t buf[len + 2];
132 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
133 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
135 for (i = 0; i < len; ++i) {
136 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
137 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
140 return sigma_write(buf, idx, devc);
143 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
145 return sigma_write_register(reg, &value, 1, devc);
148 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
149 struct dev_context *devc)
153 buf[0] = REG_ADDR_LOW | (reg & 0xf);
154 buf[1] = REG_ADDR_HIGH | (reg >> 4);
155 buf[2] = REG_READ_ADDR;
157 sigma_write(buf, sizeof(buf), devc);
159 return sigma_read(data, len, devc);
162 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
166 if (1 != sigma_read_register(reg, &value, 1, devc)) {
167 sr_err("sigma_get_register: 1 byte expected");
174 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
175 struct dev_context *devc)
178 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
180 REG_READ_ADDR | NEXT_REG,
181 REG_READ_ADDR | NEXT_REG,
182 REG_READ_ADDR | NEXT_REG,
183 REG_READ_ADDR | NEXT_REG,
184 REG_READ_ADDR | NEXT_REG,
185 REG_READ_ADDR | NEXT_REG,
189 sigma_write(buf, sizeof(buf), devc);
191 sigma_read(result, sizeof(result), devc);
193 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
194 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
196 /* Not really sure why this must be done, but according to spec. */
197 if ((--*stoppos & 0x1ff) == 0x1ff)
200 if ((*--triggerpos & 0x1ff) == 0x1ff)
206 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
207 uint8_t *data, struct dev_context *devc)
213 /* Send the startchunk. Index start with 1. */
214 buf[0] = startchunk >> 8;
215 buf[1] = startchunk & 0xff;
216 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
219 buf[idx++] = REG_DRAM_BLOCK;
220 buf[idx++] = REG_DRAM_WAIT_ACK;
222 for (i = 0; i < numchunks; ++i) {
223 /* Alternate bit to copy from DRAM to cache. */
224 if (i != (numchunks - 1))
225 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
227 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_WAIT_ACK;
233 sigma_write(buf, idx, devc);
235 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
238 /* Upload trigger look-up tables to Sigma. */
239 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
245 /* Transpose the table and send to Sigma. */
246 for (i = 0; i < 16; ++i) {
251 if (lut->m2d[0] & bit)
253 if (lut->m2d[1] & bit)
255 if (lut->m2d[2] & bit)
257 if (lut->m2d[3] & bit)
267 if (lut->m0d[0] & bit)
269 if (lut->m0d[1] & bit)
271 if (lut->m0d[2] & bit)
273 if (lut->m0d[3] & bit)
276 if (lut->m1d[0] & bit)
278 if (lut->m1d[1] & bit)
280 if (lut->m1d[2] & bit)
282 if (lut->m1d[3] & bit)
285 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
287 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
290 /* Send the parameters */
291 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
292 sizeof(lut->params), devc);
297 /* Generate the bitbang stream for programming the FPGA. */
298 static int bin2bitbang(const char *filename,
299 unsigned char **buf, size_t *buf_size)
302 unsigned long file_size;
303 unsigned long offset = 0;
306 unsigned long fwsize = 0;
307 const int buffer_size = 65536;
310 uint32_t imm = 0x3f6df2ab;
312 f = g_fopen(filename, "rb");
314 sr_err("g_fopen(\"%s\", \"rb\")", filename);
318 if (-1 == fseek(f, 0, SEEK_END)) {
319 sr_err("fseek on %s failed", filename);
324 file_size = ftell(f);
326 fseek(f, 0, SEEK_SET);
328 if (!(firmware = g_try_malloc(buffer_size))) {
329 sr_err("%s: firmware malloc failed", __func__);
331 return SR_ERR_MALLOC;
334 while ((c = getc(f)) != EOF) {
335 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
336 firmware[fwsize++] = c ^ imm;
340 if(fwsize != file_size) {
341 sr_err("%s: Error reading firmware", filename);
347 *buf_size = fwsize * 2 * 8;
349 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
351 sr_err("%s: buf/p malloc failed", __func__);
353 return SR_ERR_MALLOC;
356 for (i = 0; i < fwsize; ++i) {
357 for (bit = 7; bit >= 0; --bit) {
358 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
359 p[offset++] = v | 0x01;
366 if (offset != *buf_size) {
368 sr_err("Error reading firmware %s "
369 "offset=%ld, file_size=%ld, buf_size=%zd.",
370 filename, offset, file_size, *buf_size);
378 static void clear_helper(void *priv)
380 struct dev_context *devc;
384 ftdi_deinit(&devc->ftdic);
387 static int dev_clear(void)
389 return std_dev_clear(di, clear_helper);
392 static int init(struct sr_context *sr_ctx)
394 return std_init(sr_ctx, di, LOG_PREFIX);
397 static GSList *scan(GSList *options)
399 struct sr_dev_inst *sdi;
400 struct sr_channel *ch;
401 struct drv_context *drvc;
402 struct dev_context *devc;
404 struct ftdi_device_list *devlist;
416 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
417 sr_err("%s: devc malloc failed", __func__);
421 ftdi_init(&devc->ftdic);
423 /* Look for SIGMAs. */
425 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
426 USB_VENDOR, USB_PRODUCT)) <= 0) {
428 sr_err("ftdi_usb_find_all(): %d", ret);
432 /* Make sure it's a version 1 or 2 SIGMA. */
433 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
434 serial_txt, sizeof(serial_txt));
435 sscanf(serial_txt, "%x", &serial);
437 if (serial < 0xa6010000 || serial > 0xa602ffff) {
438 sr_err("Only SIGMA and SIGMA2 are supported "
439 "in this version of libsigrok.");
443 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
445 devc->cur_samplerate = 0;
447 devc->limit_msec = 0;
448 devc->cur_firmware = -1;
449 devc->num_channels = 0;
450 devc->samples_per_event = 0;
451 devc->capture_ratio = 50;
452 devc->use_triggers = 0;
454 /* Register SIGMA device. */
455 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
456 USB_MODEL_NAME, NULL))) {
457 sr_err("%s: sdi was NULL", __func__);
462 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
463 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
467 sdi->channels = g_slist_append(sdi->channels, ch);
470 devices = g_slist_append(devices, sdi);
471 drvc->instances = g_slist_append(drvc->instances, sdi);
474 /* We will open the device again when we need it. */
475 ftdi_list_free(&devlist);
480 ftdi_deinit(&devc->ftdic);
485 static GSList *dev_list(void)
487 return ((struct drv_context *)(di->priv))->instances;
491 * Configure the FPGA for bitbang mode.
492 * This sequence is documented in section 2. of the ASIX Sigma programming
493 * manual. This sequence is necessary to configure the FPGA in the Sigma
494 * into Bitbang mode, in which it can be programmed with the firmware.
496 static int sigma_fpga_init_bitbang(struct dev_context *devc)
498 uint8_t suicide[] = {
499 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
501 uint8_t init_array[] = {
502 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
505 int i, ret, timeout = 10000;
508 /* Section 2. part 1), do the FPGA suicide. */
509 sigma_write(suicide, sizeof(suicide), devc);
510 sigma_write(suicide, sizeof(suicide), devc);
511 sigma_write(suicide, sizeof(suicide), devc);
512 sigma_write(suicide, sizeof(suicide), devc);
514 /* Section 2. part 2), do pulse on D1. */
515 sigma_write(init_array, sizeof(init_array), devc);
516 ftdi_usb_purge_buffers(&devc->ftdic);
518 /* Wait until the FPGA asserts D6/INIT_B. */
519 for (i = 0; i < timeout; i++) {
520 ret = sigma_read(&data, 1, devc);
523 /* Test if pin D6 got asserted. */
526 /* The D6 was not asserted yet, wait a bit. */
530 return SR_ERR_TIMEOUT;
533 static int upload_firmware(int firmware_idx, struct dev_context *devc)
539 unsigned char result[32];
540 char firmware_path[128];
542 /* Make sure it's an ASIX SIGMA. */
543 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
544 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
545 sr_err("ftdi_usb_open failed: %s",
546 ftdi_get_error_string(&devc->ftdic));
550 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
551 sr_err("ftdi_set_bitmode failed: %s",
552 ftdi_get_error_string(&devc->ftdic));
556 /* Four times the speed of sigmalogan - Works well. */
557 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
558 sr_err("ftdi_set_baudrate failed: %s",
559 ftdi_get_error_string(&devc->ftdic));
563 /* Initialize the FPGA for firmware upload. */
564 ret = sigma_fpga_init_bitbang(devc);
568 /* Prepare firmware. */
569 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
570 firmware_files[firmware_idx]);
572 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
573 sr_err("An error occured while reading the firmware: %s",
578 /* Upload firmare. */
579 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
580 sigma_write(buf, buf_size, devc);
584 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
585 sr_err("ftdi_set_bitmode failed: %s",
586 ftdi_get_error_string(&devc->ftdic));
590 ftdi_usb_purge_buffers(&devc->ftdic);
592 /* Discard garbage. */
593 while (1 == sigma_read(&pins, 1, devc))
596 /* Initialize the logic analyzer mode. */
597 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
599 /* Expect a 3 byte reply. */
600 ret = sigma_read(result, 3, devc);
602 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
603 sr_err("Configuration failed. Invalid reply received.");
607 devc->cur_firmware = firmware_idx;
609 sr_info("Firmware uploaded.");
614 static int dev_open(struct sr_dev_inst *sdi)
616 struct dev_context *devc;
621 /* Make sure it's an ASIX SIGMA. */
622 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
623 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
625 sr_err("ftdi_usb_open failed: %s",
626 ftdi_get_error_string(&devc->ftdic));
631 sdi->status = SR_ST_ACTIVE;
636 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
638 struct dev_context *devc;
645 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
646 if (samplerates[i] == samplerate)
649 if (samplerates[i] == 0)
650 return SR_ERR_SAMPLERATE;
652 if (samplerate <= SR_MHZ(50)) {
653 ret = upload_firmware(0, devc);
654 devc->num_channels = 16;
656 if (samplerate == SR_MHZ(100)) {
657 ret = upload_firmware(1, devc);
658 devc->num_channels = 8;
660 else if (samplerate == SR_MHZ(200)) {
661 ret = upload_firmware(2, devc);
662 devc->num_channels = 4;
665 devc->cur_samplerate = samplerate;
666 devc->period_ps = 1000000000000ULL / samplerate;
667 devc->samples_per_event = 16 / devc->num_channels;
668 devc->state.state = SIGMA_IDLE;
674 * In 100 and 200 MHz mode, only a single pin rising/falling can be
675 * set as trigger. In other modes, two rising/falling triggers can be set,
676 * in addition to value/mask trigger for any number of channels.
678 * The Sigma supports complex triggers using boolean expressions, but this
679 * has not been implemented yet.
681 static int configure_channels(const struct sr_dev_inst *sdi)
683 struct dev_context *devc = sdi->priv;
684 const struct sr_channel *ch;
689 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
691 for (l = sdi->channels; l; l = l->next) {
692 ch = (struct sr_channel *)l->data;
693 channelbit = 1 << (ch->index);
695 if (!ch->enabled || !ch->trigger)
698 if (devc->cur_samplerate >= SR_MHZ(100)) {
699 /* Fast trigger support. */
701 sr_err("Only a single pin trigger in 100 and "
702 "200MHz mode is supported.");
705 if (ch->trigger[0] == 'f')
706 devc->trigger.fallingmask |= channelbit;
707 else if (ch->trigger[0] == 'r')
708 devc->trigger.risingmask |= channelbit;
710 sr_err("Only rising/falling trigger in 100 "
711 "and 200MHz mode is supported.");
717 /* Simple trigger support (event). */
718 if (ch->trigger[0] == '1') {
719 devc->trigger.simplevalue |= channelbit;
720 devc->trigger.simplemask |= channelbit;
722 else if (ch->trigger[0] == '0') {
723 devc->trigger.simplevalue &= ~channelbit;
724 devc->trigger.simplemask |= channelbit;
726 else if (ch->trigger[0] == 'f') {
727 devc->trigger.fallingmask |= channelbit;
730 else if (ch->trigger[0] == 'r') {
731 devc->trigger.risingmask |= channelbit;
736 * Actually, Sigma supports 2 rising/falling triggers,
737 * but they are ORed and the current trigger syntax
738 * does not permit ORed triggers.
740 if (trigger_set > 1) {
741 sr_err("Only 1 rising/falling trigger "
748 devc->use_triggers = 1;
754 static int dev_close(struct sr_dev_inst *sdi)
756 struct dev_context *devc;
761 if (sdi->status == SR_ST_ACTIVE)
762 ftdi_usb_close(&devc->ftdic);
764 sdi->status = SR_ST_INACTIVE;
769 static int cleanup(void)
774 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
775 const struct sr_channel_group *cg)
777 struct dev_context *devc;
782 case SR_CONF_SAMPLERATE:
785 *data = g_variant_new_uint64(devc->cur_samplerate);
796 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
797 const struct sr_channel_group *cg)
799 struct dev_context *devc;
800 uint64_t num_samples;
805 if (sdi->status != SR_ST_ACTIVE)
806 return SR_ERR_DEV_CLOSED;
811 case SR_CONF_SAMPLERATE:
812 ret = set_samplerate(sdi, g_variant_get_uint64(data));
814 case SR_CONF_LIMIT_MSEC:
815 devc->limit_msec = g_variant_get_uint64(data);
816 if (devc->limit_msec > 0)
821 case SR_CONF_LIMIT_SAMPLES:
822 num_samples = g_variant_get_uint64(data);
823 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
825 case SR_CONF_CAPTURE_RATIO:
826 devc->capture_ratio = g_variant_get_uint64(data);
827 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
839 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
840 const struct sr_channel_group *cg)
849 case SR_CONF_DEVICE_OPTIONS:
850 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
851 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
853 case SR_CONF_SAMPLERATE:
854 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
855 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
856 ARRAY_SIZE(samplerates), sizeof(uint64_t));
857 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
858 *data = g_variant_builder_end(&gvb);
860 case SR_CONF_TRIGGER_TYPE:
861 *data = g_variant_new_string(TRIGGER_TYPE);
870 /* Software trigger to determine exact trigger position. */
871 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
872 struct sigma_trigger *t)
876 for (i = 0; i < 8; ++i) {
878 last_sample = samples[i-1];
880 /* Simple triggers. */
881 if ((samples[i] & t->simplemask) != t->simplevalue)
885 if ((last_sample & t->risingmask) != 0 || (samples[i] &
886 t->risingmask) != t->risingmask)
890 if ((last_sample & t->fallingmask) != t->fallingmask ||
891 (samples[i] & t->fallingmask) != 0)
897 /* If we did not match, return original trigger pos. */
902 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
903 * Each event is 20ns apart, and can contain multiple samples.
905 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
906 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
907 * For 50 MHz and below, events contain one sample for each channel,
908 * spread 20 ns apart.
910 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
911 uint16_t *lastsample, int triggerpos,
912 uint16_t limit_chunk, void *cb_data)
914 struct sr_dev_inst *sdi = cb_data;
915 struct dev_context *devc = sdi->priv;
917 uint16_t samples[65536 * devc->samples_per_event];
918 struct sr_datafeed_packet packet;
919 struct sr_datafeed_logic logic;
920 int i, j, k, l, numpad, tosend;
921 size_t n = 0, sent = 0;
922 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
927 /* Check if trigger is in this chunk. */
928 if (triggerpos != -1) {
929 if (devc->cur_samplerate <= SR_MHZ(50))
930 triggerpos -= EVENTS_PER_CLUSTER - 1;
935 /* Find in which cluster the trigger occured. */
936 triggerts = triggerpos / 7;
940 for (i = 0; i < 64; ++i) {
941 ts = *(uint16_t *) &buf[i * 16];
942 tsdiff = ts - *lastts;
945 /* Decode partial chunk. */
946 if (limit_chunk && ts > limit_chunk)
949 /* Pad last sample up to current point. */
950 numpad = tsdiff * devc->samples_per_event - clustersize;
952 for (j = 0; j < numpad; ++j)
953 samples[j] = *lastsample;
958 /* Send samples between previous and this timestamp to sigrok. */
961 tosend = MIN(2048, n - sent);
963 packet.type = SR_DF_LOGIC;
964 packet.payload = &logic;
965 logic.length = tosend * sizeof(uint16_t);
967 logic.data = samples + sent;
968 sr_session_send(devc->cb_data, &packet);
974 event = (uint16_t *) &buf[i * 16 + 2];
977 /* For each event in cluster. */
978 for (j = 0; j < 7; ++j) {
980 /* For each sample in event. */
981 for (k = 0; k < devc->samples_per_event; ++k) {
984 /* For each channel. */
985 for (l = 0; l < devc->num_channels; ++l)
986 cur_sample |= (!!(event[j] & (1 << (l *
987 devc->samples_per_event + k)))) << l;
989 samples[n++] = cur_sample;
993 /* Send data up to trigger point (if triggered). */
995 if (i == triggerts) {
997 * Trigger is not always accurate to sample because of
998 * pipeline delay. However, it always triggers before
999 * the actual event. We therefore look at the next
1000 * samples to pinpoint the exact position of the trigger.
1002 tosend = get_trigger_offset(samples, *lastsample,
1006 packet.type = SR_DF_LOGIC;
1007 packet.payload = &logic;
1008 logic.length = tosend * sizeof(uint16_t);
1010 logic.data = samples;
1011 sr_session_send(devc->cb_data, &packet);
1016 /* Only send trigger if explicitly enabled. */
1017 if (devc->use_triggers) {
1018 packet.type = SR_DF_TRIGGER;
1019 sr_session_send(devc->cb_data, &packet);
1023 /* Send rest of the chunk to sigrok. */
1027 packet.type = SR_DF_LOGIC;
1028 packet.payload = &logic;
1029 logic.length = tosend * sizeof(uint16_t);
1031 logic.data = samples + sent;
1032 sr_session_send(devc->cb_data, &packet);
1035 *lastsample = samples[n - 1];
1041 static void download_capture(struct sr_dev_inst *sdi)
1043 struct dev_context *devc;
1044 const int chunks_per_read = 32;
1045 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1046 int bufsz, i, numchunks, newchunks;
1048 sr_info("Downloading sample data.");
1051 devc->state.chunks_downloaded = 0;
1052 numchunks = (devc->state.stoppos + 511) / 512;
1053 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1055 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1056 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1059 /* Find first ts. */
1060 if (devc->state.chunks_downloaded == 0) {
1061 devc->state.lastts = RL16(buf) - 1;
1062 devc->state.lastsample = 0;
1065 /* Decode chunks and send them to sigrok. */
1066 for (i = 0; i < newchunks; ++i) {
1067 int limit_chunk = 0;
1069 /* The last chunk may potentially be only in part. */
1070 if (devc->state.chunks_downloaded == numchunks - 1) {
1071 /* Find the last valid timestamp */
1072 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1075 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1076 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1077 &devc->state.lastts,
1078 &devc->state.lastsample,
1079 devc->state.triggerpos & 0x1ff,
1082 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1083 &devc->state.lastts,
1084 &devc->state.lastsample,
1085 -1, limit_chunk, sdi);
1087 ++devc->state.chunks_downloaded;
1092 static int receive_data(int fd, int revents, void *cb_data)
1094 struct sr_dev_inst *sdi;
1095 struct dev_context *devc;
1096 struct sr_datafeed_packet packet;
1097 uint64_t running_msec;
1108 /* Get the current position. */
1109 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1111 if (devc->state.state == SIGMA_IDLE)
1114 if (devc->state.state == SIGMA_CAPTURE) {
1115 numchunks = (devc->state.stoppos + 511) / 512;
1117 /* Check if the timer has expired, or memory is full. */
1118 gettimeofday(&tv, 0);
1119 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1120 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1122 if (running_msec < devc->limit_msec && numchunks < 32767)
1123 /* Still capturing. */
1126 /* Stop acquisition. */
1127 sigma_set_register(WRITE_MODE, 0x11, devc);
1129 /* Set SDRAM Read Enable. */
1130 sigma_set_register(WRITE_MODE, 0x02, devc);
1132 /* Get the current position. */
1133 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1135 /* Check if trigger has fired. */
1136 modestatus = sigma_get_register(READ_MODE, devc);
1137 if (modestatus & 0x20)
1138 devc->state.triggerchunk = devc->state.triggerpos / 512;
1140 devc->state.triggerchunk = -1;
1142 /* Transfer captured data from device. */
1143 download_capture(sdi);
1146 packet.type = SR_DF_END;
1147 sr_session_send(sdi, &packet);
1149 dev_acquisition_stop(sdi, sdi);
1155 /* Build a LUT entry used by the trigger functions. */
1156 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1160 /* For each quad channel. */
1161 for (i = 0; i < 4; ++i) {
1164 /* For each bit in LUT. */
1165 for (j = 0; j < 16; ++j)
1167 /* For each channel in quad. */
1168 for (k = 0; k < 4; ++k) {
1169 bit = 1 << (i * 4 + k);
1171 /* Set bit in entry */
1173 ((!(value & bit)) !=
1175 entry[i] &= ~(1 << j);
1180 /* Add a logical function to LUT mask. */
1181 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1182 int index, int neg, uint16_t *mask)
1185 int x[2][2], tmp, a, b, aset, bset, rset;
1187 memset(x, 0, 4 * sizeof(int));
1189 /* Trigger detect condition. */
1219 case OP_NOTRISEFALL:
1225 /* Transpose if neg is set. */
1227 for (i = 0; i < 2; ++i) {
1228 for (j = 0; j < 2; ++j) {
1230 x[i][j] = x[1-i][1-j];
1236 /* Update mask with function. */
1237 for (i = 0; i < 16; ++i) {
1238 a = (i >> (2 * index + 0)) & 1;
1239 b = (i >> (2 * index + 1)) & 1;
1241 aset = (*mask >> i) & 1;
1244 if (func == FUNC_AND || func == FUNC_NAND)
1246 else if (func == FUNC_OR || func == FUNC_NOR)
1248 else if (func == FUNC_XOR || func == FUNC_NXOR)
1251 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1262 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1263 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1264 * set at any time, but a full mask and value can be set (0/1).
1266 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1269 uint16_t masks[2] = { 0, 0 };
1271 memset(lut, 0, sizeof(struct triggerlut));
1273 /* Contant for simple triggers. */
1276 /* Value/mask trigger support. */
1277 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1280 /* Rise/fall trigger support. */
1281 for (i = 0, j = 0; i < 16; ++i) {
1282 if (devc->trigger.risingmask & (1 << i) ||
1283 devc->trigger.fallingmask & (1 << i))
1284 masks[j++] = 1 << i;
1287 build_lut_entry(masks[0], masks[0], lut->m0d);
1288 build_lut_entry(masks[1], masks[1], lut->m1d);
1290 /* Add glue logic */
1291 if (masks[0] || masks[1]) {
1292 /* Transition trigger. */
1293 if (masks[0] & devc->trigger.risingmask)
1294 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1295 if (masks[0] & devc->trigger.fallingmask)
1296 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1297 if (masks[1] & devc->trigger.risingmask)
1298 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1299 if (masks[1] & devc->trigger.fallingmask)
1300 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1302 /* Only value/mask trigger. */
1306 /* Triggertype: event. */
1307 lut->params.selres = 3;
1312 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1314 struct dev_context *devc;
1315 struct clockselect_50 clockselect;
1316 int frac, triggerpin, ret;
1317 uint8_t triggerselect = 0;
1318 struct triggerinout triggerinout_conf;
1319 struct triggerlut lut;
1321 if (sdi->status != SR_ST_ACTIVE)
1322 return SR_ERR_DEV_CLOSED;
1326 if (configure_channels(sdi) != SR_OK) {
1327 sr_err("Failed to configure channels.");
1331 /* If the samplerate has not been set, default to 200 kHz. */
1332 if (devc->cur_firmware == -1) {
1333 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1337 /* Enter trigger programming mode. */
1338 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1340 /* 100 and 200 MHz mode. */
1341 if (devc->cur_samplerate >= SR_MHZ(100)) {
1342 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1344 /* Find which pin to trigger on from mask. */
1345 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1346 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1350 /* Set trigger pin and light LED on trigger. */
1351 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1353 /* Default rising edge. */
1354 if (devc->trigger.fallingmask)
1355 triggerselect |= 1 << 3;
1357 /* All other modes. */
1358 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1359 build_basic_trigger(&lut, devc);
1361 sigma_write_trigger_lut(&lut, devc);
1363 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1366 /* Setup trigger in and out pins to default values. */
1367 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1368 triggerinout_conf.trgout_bytrigger = 1;
1369 triggerinout_conf.trgout_enable = 1;
1371 sigma_write_register(WRITE_TRIGGER_OPTION,
1372 (uint8_t *) &triggerinout_conf,
1373 sizeof(struct triggerinout), devc);
1375 /* Go back to normal mode. */
1376 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1378 /* Set clock select register. */
1379 if (devc->cur_samplerate == SR_MHZ(200))
1380 /* Enable 4 channels. */
1381 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1382 else if (devc->cur_samplerate == SR_MHZ(100))
1383 /* Enable 8 channels. */
1384 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1387 * 50 MHz mode (or fraction thereof). Any fraction down to
1388 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1390 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1392 clockselect.async = 0;
1393 clockselect.fraction = frac;
1394 clockselect.disabled_channels = 0;
1396 sigma_write_register(WRITE_CLOCK_SELECT,
1397 (uint8_t *) &clockselect,
1398 sizeof(clockselect), devc);
1401 /* Setup maximum post trigger time. */
1402 sigma_set_register(WRITE_POST_TRIGGER,
1403 (devc->capture_ratio * 255) / 100, devc);
1405 /* Start acqusition. */
1406 gettimeofday(&devc->start_tv, 0);
1407 sigma_set_register(WRITE_MODE, 0x0d, devc);
1409 devc->cb_data = cb_data;
1411 /* Send header packet to the session bus. */
1412 std_session_send_df_header(cb_data, LOG_PREFIX);
1414 /* Add capture source. */
1415 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1417 devc->state.state = SIGMA_CAPTURE;
1422 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1424 struct dev_context *devc;
1429 devc->state.state = SIGMA_IDLE;
1431 sr_source_remove(0);
1436 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1437 .name = "asix-sigma",
1438 .longname = "ASIX SIGMA/SIGMA2",
1443 .dev_list = dev_list,
1444 .dev_clear = dev_clear,
1445 .config_get = config_get,
1446 .config_set = config_set,
1447 .config_list = config_list,
1448 .dev_open = dev_open,
1449 .dev_close = dev_close,
1450 .dev_acquisition_start = dev_acquisition_start,
1451 .dev_acquisition_stop = dev_acquisition_stop,