2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
40 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
41 static struct sr_dev_driver *di = &asix_sigma_driver_info;
42 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
45 * The ASIX Sigma supports arbitrary integer frequency divider in
46 * the 50MHz mode. The divider is in range 1...256 , allowing for
47 * very precise sampling rate selection. This driver supports only
48 * a subset of the sampling rates.
50 static const uint64_t samplerates[] = {
51 SR_KHZ(200), /* div=250 */
52 SR_KHZ(250), /* div=200 */
53 SR_KHZ(500), /* div=100 */
54 SR_MHZ(1), /* div=50 */
55 SR_MHZ(5), /* div=10 */
56 SR_MHZ(10), /* div=5 */
57 SR_MHZ(25), /* div=2 */
58 SR_MHZ(50), /* div=1 */
59 SR_MHZ(100), /* Special FW needed */
60 SR_MHZ(200), /* Special FW needed */
64 * Channel numbers seem to go from 1-16, according to this image:
65 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
66 * (the cable has two additional GND pins, and a TI and TO pin)
68 static const char *channel_names[] = {
69 "1", "2", "3", "4", "5", "6", "7", "8",
70 "9", "10", "11", "12", "13", "14", "15", "16",
73 static const int32_t hwcaps[] = {
74 SR_CONF_LOGIC_ANALYZER,
76 SR_CONF_TRIGGER_MATCH,
77 SR_CONF_CAPTURE_RATIO,
81 static const int32_t trigger_matches[] = {
88 static const char *sigma_firmware_files[] = {
89 /* 50 MHz, supports 8 bit fractions */
90 FIRMWARE_DIR "/asix-sigma-50.fw",
92 FIRMWARE_DIR "/asix-sigma-100.fw",
94 FIRMWARE_DIR "/asix-sigma-200.fw",
95 /* Synchronous clock from pin */
96 FIRMWARE_DIR "/asix-sigma-50sync.fw",
97 /* Frequency counter */
98 FIRMWARE_DIR "/asix-sigma-phasor.fw",
101 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
105 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
107 sr_err("ftdi_read_data failed: %s",
108 ftdi_get_error_string(&devc->ftdic));
114 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
118 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
120 sr_err("ftdi_write_data failed: %s",
121 ftdi_get_error_string(&devc->ftdic));
122 } else if ((size_t) ret != size) {
123 sr_err("ftdi_write_data did not complete write.");
129 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
130 struct dev_context *devc)
133 uint8_t buf[len + 2];
136 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
137 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
139 for (i = 0; i < len; ++i) {
140 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
141 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
144 return sigma_write(buf, idx, devc);
147 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
149 return sigma_write_register(reg, &value, 1, devc);
152 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
153 struct dev_context *devc)
157 buf[0] = REG_ADDR_LOW | (reg & 0xf);
158 buf[1] = REG_ADDR_HIGH | (reg >> 4);
159 buf[2] = REG_READ_ADDR;
161 sigma_write(buf, sizeof(buf), devc);
163 return sigma_read(data, len, devc);
166 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
170 if (1 != sigma_read_register(reg, &value, 1, devc)) {
171 sr_err("sigma_get_register: 1 byte expected");
178 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
179 struct dev_context *devc)
182 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
184 REG_READ_ADDR | NEXT_REG,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
193 sigma_write(buf, sizeof(buf), devc);
195 sigma_read(result, sizeof(result), devc);
197 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
198 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
200 /* Not really sure why this must be done, but according to spec. */
201 if ((--*stoppos & 0x1ff) == 0x1ff)
204 if ((*--triggerpos & 0x1ff) == 0x1ff)
210 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
211 uint8_t *data, struct dev_context *devc)
217 /* Send the startchunk. Index start with 1. */
218 buf[0] = startchunk >> 8;
219 buf[1] = startchunk & 0xff;
220 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
223 buf[idx++] = REG_DRAM_BLOCK;
224 buf[idx++] = REG_DRAM_WAIT_ACK;
226 for (i = 0; i < numchunks; ++i) {
227 /* Alternate bit to copy from DRAM to cache. */
228 if (i != (numchunks - 1))
229 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
231 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
233 if (i != (numchunks - 1))
234 buf[idx++] = REG_DRAM_WAIT_ACK;
237 sigma_write(buf, idx, devc);
239 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
242 /* Upload trigger look-up tables to Sigma. */
243 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
249 /* Transpose the table and send to Sigma. */
250 for (i = 0; i < 16; ++i) {
255 if (lut->m2d[0] & bit)
257 if (lut->m2d[1] & bit)
259 if (lut->m2d[2] & bit)
261 if (lut->m2d[3] & bit)
271 if (lut->m0d[0] & bit)
273 if (lut->m0d[1] & bit)
275 if (lut->m0d[2] & bit)
277 if (lut->m0d[3] & bit)
280 if (lut->m1d[0] & bit)
282 if (lut->m1d[1] & bit)
284 if (lut->m1d[2] & bit)
286 if (lut->m1d[3] & bit)
289 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
291 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
294 /* Send the parameters */
295 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
296 sizeof(lut->params), devc);
301 static void clear_helper(void *priv)
303 struct dev_context *devc;
307 ftdi_deinit(&devc->ftdic);
310 static int dev_clear(void)
312 return std_dev_clear(di, clear_helper);
315 static int init(struct sr_context *sr_ctx)
317 return std_init(sr_ctx, di, LOG_PREFIX);
320 static GSList *scan(GSList *options)
322 struct sr_dev_inst *sdi;
323 struct sr_channel *ch;
324 struct drv_context *drvc;
325 struct dev_context *devc;
327 struct ftdi_device_list *devlist;
339 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
340 sr_err("%s: devc malloc failed", __func__);
344 ftdi_init(&devc->ftdic);
346 /* Look for SIGMAs. */
348 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
349 USB_VENDOR, USB_PRODUCT)) <= 0) {
351 sr_err("ftdi_usb_find_all(): %d", ret);
355 /* Make sure it's a version 1 or 2 SIGMA. */
356 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
357 serial_txt, sizeof(serial_txt));
358 sscanf(serial_txt, "%x", &serial);
360 if (serial < 0xa6010000 || serial > 0xa602ffff) {
361 sr_err("Only SIGMA and SIGMA2 are supported "
362 "in this version of libsigrok.");
366 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
368 devc->cur_samplerate = samplerates[0];
370 devc->limit_msec = 0;
371 devc->cur_firmware = -1;
372 devc->num_channels = 0;
373 devc->samples_per_event = 0;
374 devc->capture_ratio = 50;
375 devc->use_triggers = 0;
377 /* Register SIGMA device. */
378 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
379 USB_MODEL_NAME, NULL))) {
380 sr_err("%s: sdi was NULL", __func__);
385 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
386 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
390 sdi->channels = g_slist_append(sdi->channels, ch);
393 devices = g_slist_append(devices, sdi);
394 drvc->instances = g_slist_append(drvc->instances, sdi);
397 /* We will open the device again when we need it. */
398 ftdi_list_free(&devlist);
403 ftdi_deinit(&devc->ftdic);
408 static GSList *dev_list(void)
410 return ((struct drv_context *)(di->priv))->instances;
414 * Configure the FPGA for bitbang mode.
415 * This sequence is documented in section 2. of the ASIX Sigma programming
416 * manual. This sequence is necessary to configure the FPGA in the Sigma
417 * into Bitbang mode, in which it can be programmed with the firmware.
419 static int sigma_fpga_init_bitbang(struct dev_context *devc)
421 uint8_t suicide[] = {
422 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
424 uint8_t init_array[] = {
425 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
428 int i, ret, timeout = 10000;
431 /* Section 2. part 1), do the FPGA suicide. */
432 sigma_write(suicide, sizeof(suicide), devc);
433 sigma_write(suicide, sizeof(suicide), devc);
434 sigma_write(suicide, sizeof(suicide), devc);
435 sigma_write(suicide, sizeof(suicide), devc);
437 /* Section 2. part 2), do pulse on D1. */
438 sigma_write(init_array, sizeof(init_array), devc);
439 ftdi_usb_purge_buffers(&devc->ftdic);
441 /* Wait until the FPGA asserts D6/INIT_B. */
442 for (i = 0; i < timeout; i++) {
443 ret = sigma_read(&data, 1, devc);
446 /* Test if pin D6 got asserted. */
449 /* The D6 was not asserted yet, wait a bit. */
453 return SR_ERR_TIMEOUT;
457 * Configure the FPGA for logic-analyzer mode.
459 static int sigma_fpga_init_la(struct dev_context *devc)
461 /* Initialize the logic analyzer mode. */
462 uint8_t logic_mode_start[] = {
463 REG_ADDR_LOW | (READ_ID & 0xf),
464 REG_ADDR_HIGH | (READ_ID >> 8),
465 REG_READ_ADDR, /* Read ID register. */
467 REG_ADDR_LOW | (WRITE_TEST & 0xf),
469 REG_DATA_HIGH_WRITE | 0x5,
470 REG_READ_ADDR, /* Read scratch register. */
473 REG_DATA_HIGH_WRITE | 0xa,
474 REG_READ_ADDR, /* Read scratch register. */
476 REG_ADDR_LOW | (WRITE_MODE & 0xf),
478 REG_DATA_HIGH_WRITE | 0x8,
484 /* Initialize the logic analyzer mode. */
485 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
487 /* Expect a 3 byte reply since we issued three READ requests. */
488 ret = sigma_read(result, 3, devc);
492 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
497 sr_err("Configuration failed. Invalid reply received.");
502 * Read the firmware from a file and transform it into a series of bitbang
503 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
504 * by the caller of this function.
506 static int sigma_fw_2_bitbang(const char *filename,
507 uint8_t **bb_cmd, gsize *bb_cmd_size)
511 gsize i, file_size, bb_size;
513 uint8_t *bb_stream, *bbs;
519 * Map the file and make the mapped buffer writable.
520 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
521 * will be modified. It will not be modified until someone uses
522 * g_file_set_contents() on it.
525 file = g_mapped_file_new(filename, TRUE, &error);
526 g_assert_no_error(error);
528 file_size = g_mapped_file_get_length(file);
529 firmware = g_mapped_file_get_contents(file);
532 /* Weird magic transformation below, I have no idea what it does. */
534 for (i = 0; i < file_size; i++) {
535 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
536 firmware[i] ^= imm & 0xff;
540 * Now that the firmware is "transformed", we will transcribe the
541 * firmware blob into a sequence of toggles of the Dx wires. This
542 * sequence will be fed directly into the Sigma, which must be in
543 * the FPGA bitbang programming mode.
546 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
547 bb_size = file_size * 8 * 2;
548 bb_stream = (uint8_t *)g_try_malloc(bb_size);
550 sr_err("%s: Failed to allocate bitbang stream", __func__);
556 for (i = 0; i < file_size; i++) {
557 for (bit = 7; bit >= 0; bit--) {
558 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
564 /* The transformation completed successfully, return the result. */
566 *bb_cmd_size = bb_size;
569 g_mapped_file_unref(file);
573 static int upload_firmware(int firmware_idx, struct dev_context *devc)
579 const char *firmware = sigma_firmware_files[firmware_idx];
580 struct ftdi_context *ftdic = &devc->ftdic;
582 /* Make sure it's an ASIX SIGMA. */
583 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
584 USB_DESCRIPTION, NULL);
586 sr_err("ftdi_usb_open failed: %s",
587 ftdi_get_error_string(ftdic));
591 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
593 sr_err("ftdi_set_bitmode failed: %s",
594 ftdi_get_error_string(ftdic));
598 /* Four times the speed of sigmalogan - Works well. */
599 ret = ftdi_set_baudrate(ftdic, 750000);
601 sr_err("ftdi_set_baudrate failed: %s",
602 ftdi_get_error_string(ftdic));
606 /* Initialize the FPGA for firmware upload. */
607 ret = sigma_fpga_init_bitbang(devc);
611 /* Prepare firmware. */
612 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
614 sr_err("An error occured while reading the firmware: %s",
619 /* Upload firmare. */
620 sr_info("Uploading firmware file '%s'.", firmware);
621 sigma_write(buf, buf_size, devc);
625 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
627 sr_err("ftdi_set_bitmode failed: %s",
628 ftdi_get_error_string(ftdic));
632 ftdi_usb_purge_buffers(ftdic);
634 /* Discard garbage. */
635 while (sigma_read(&pins, 1, devc) == 1)
638 /* Initialize the FPGA for logic-analyzer mode. */
639 ret = sigma_fpga_init_la(devc);
643 devc->cur_firmware = firmware_idx;
645 sr_info("Firmware uploaded.");
650 static int dev_open(struct sr_dev_inst *sdi)
652 struct dev_context *devc;
657 /* Make sure it's an ASIX SIGMA. */
658 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
659 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
661 sr_err("ftdi_usb_open failed: %s",
662 ftdi_get_error_string(&devc->ftdic));
667 sdi->status = SR_ST_ACTIVE;
672 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
674 struct dev_context *devc;
681 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
682 if (samplerates[i] == samplerate)
685 if (samplerates[i] == 0)
686 return SR_ERR_SAMPLERATE;
688 if (samplerate <= SR_MHZ(50)) {
689 ret = upload_firmware(0, devc);
690 devc->num_channels = 16;
691 } else if (samplerate == SR_MHZ(100)) {
692 ret = upload_firmware(1, devc);
693 devc->num_channels = 8;
694 } else if (samplerate == SR_MHZ(200)) {
695 ret = upload_firmware(2, devc);
696 devc->num_channels = 4;
700 devc->cur_samplerate = samplerate;
701 devc->period_ps = 1000000000000ULL / samplerate;
702 devc->samples_per_event = 16 / devc->num_channels;
703 devc->state.state = SIGMA_IDLE;
710 * In 100 and 200 MHz mode, only a single pin rising/falling can be
711 * set as trigger. In other modes, two rising/falling triggers can be set,
712 * in addition to value/mask trigger for any number of channels.
714 * The Sigma supports complex triggers using boolean expressions, but this
715 * has not been implemented yet.
717 static int convert_trigger(const struct sr_dev_inst *sdi)
719 struct dev_context *devc;
720 struct sr_trigger *trigger;
721 struct sr_trigger_stage *stage;
722 struct sr_trigger_match *match;
724 int channelbit, trigger_set;
727 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
728 if (!(trigger = sr_session_trigger_get()))
732 for (l = trigger->stages; l; l = l->next) {
734 for (m = stage->matches; m; m = m->next) {
736 if (!match->channel->enabled)
737 /* Ignore disabled channels with a trigger. */
739 channelbit = 1 << (match->channel->index);
740 if (devc->cur_samplerate >= SR_MHZ(100)) {
741 /* Fast trigger support. */
743 sr_err("Only a single pin trigger is "
744 "supported in 100 and 200MHz mode.");
747 if (match->match == SR_TRIGGER_FALLING)
748 devc->trigger.fallingmask |= channelbit;
749 else if (match->match == SR_TRIGGER_RISING)
750 devc->trigger.risingmask |= channelbit;
752 sr_err("Only rising/falling trigger is "
753 "supported in 100 and 200MHz mode.");
759 /* Simple trigger support (event). */
760 if (match->match == SR_TRIGGER_ONE) {
761 devc->trigger.simplevalue |= channelbit;
762 devc->trigger.simplemask |= channelbit;
764 else if (match->match == SR_TRIGGER_ZERO) {
765 devc->trigger.simplevalue &= ~channelbit;
766 devc->trigger.simplemask |= channelbit;
768 else if (match->match == SR_TRIGGER_FALLING) {
769 devc->trigger.fallingmask |= channelbit;
772 else if (match->match == SR_TRIGGER_RISING) {
773 devc->trigger.risingmask |= channelbit;
778 * Actually, Sigma supports 2 rising/falling triggers,
779 * but they are ORed and the current trigger syntax
780 * does not permit ORed triggers.
782 if (trigger_set > 1) {
783 sr_err("Only 1 rising/falling trigger "
795 static int dev_close(struct sr_dev_inst *sdi)
797 struct dev_context *devc;
802 if (sdi->status == SR_ST_ACTIVE)
803 ftdi_usb_close(&devc->ftdic);
805 sdi->status = SR_ST_INACTIVE;
810 static int cleanup(void)
815 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
816 const struct sr_channel_group *cg)
818 struct dev_context *devc;
827 case SR_CONF_SAMPLERATE:
828 *data = g_variant_new_uint64(devc->cur_samplerate);
830 case SR_CONF_LIMIT_MSEC:
831 *data = g_variant_new_uint64(devc->limit_msec);
833 case SR_CONF_CAPTURE_RATIO:
834 *data = g_variant_new_uint64(devc->capture_ratio);
843 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
844 const struct sr_channel_group *cg)
846 struct dev_context *devc;
852 if (sdi->status != SR_ST_ACTIVE)
853 return SR_ERR_DEV_CLOSED;
859 case SR_CONF_SAMPLERATE:
860 ret = set_samplerate(sdi, g_variant_get_uint64(data));
862 case SR_CONF_LIMIT_MSEC:
863 tmp = g_variant_get_uint64(data);
865 devc->limit_msec = g_variant_get_uint64(data);
869 case SR_CONF_LIMIT_SAMPLES:
870 tmp = g_variant_get_uint64(data);
871 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
873 case SR_CONF_CAPTURE_RATIO:
874 tmp = g_variant_get_uint64(data);
876 devc->capture_ratio = tmp;
887 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
888 const struct sr_channel_group *cg)
897 case SR_CONF_DEVICE_OPTIONS:
898 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
899 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
901 case SR_CONF_SAMPLERATE:
902 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
903 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
904 ARRAY_SIZE(samplerates), sizeof(uint64_t));
905 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
906 *data = g_variant_builder_end(&gvb);
908 case SR_CONF_TRIGGER_MATCH:
909 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
910 trigger_matches, ARRAY_SIZE(trigger_matches),
920 /* Software trigger to determine exact trigger position. */
921 static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
922 struct sigma_trigger *t)
927 for (i = 0; i < 8; ++i) {
929 last_sample = sample;
930 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
932 /* Simple triggers. */
933 if ((sample & t->simplemask) != t->simplevalue)
937 if (((last_sample & t->risingmask) != 0) ||
938 ((sample & t->risingmask) != t->risingmask))
942 if ((last_sample & t->fallingmask) != t->fallingmask ||
943 (sample & t->fallingmask) != 0)
949 /* If we did not match, return original trigger pos. */
955 * Return the timestamp of "DRAM cluster".
957 static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
959 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
962 static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
963 unsigned int events_in_cluster,
964 unsigned int triggered,
965 struct sr_dev_inst *sdi)
967 struct dev_context *devc = sdi->priv;
968 struct sigma_state *ss = &devc->state;
969 struct sr_datafeed_packet packet;
970 struct sr_datafeed_logic logic;
972 uint8_t samples[2048];
975 ts = sigma_dram_cluster_ts(dram_cluster);
976 tsdiff = ts - ss->lastts;
979 packet.type = SR_DF_LOGIC;
980 packet.payload = &logic;
982 logic.data = samples;
985 * First of all, send Sigrok a copy of the last sample from
986 * previous cluster as many times as needed to make up for
987 * the differential characteristics of data we get from the
988 * Sigma. Sigrok needs one sample of data per period.
990 * One DRAM cluster contains a timestamp and seven samples,
991 * the units of timestamp are "devc->period_ps" , the first
992 * sample in the cluster happens at the time of the timestamp
993 * and the remaining samples happen at timestamp +1...+6 .
995 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
997 samples[2 * i + 0] = ss->lastsample & 0xff;
998 samples[2 * i + 1] = ss->lastsample >> 8;
1001 * If we have 1024 samples ready or we're at the
1002 * end of submitting the padding samples, submit
1003 * the packet to Sigrok.
1005 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1006 logic.length = (i + 1) * logic.unitsize;
1007 sr_session_send(devc->cb_data, &packet);
1012 * Parse the samples in current cluster and prepare them
1013 * to be submitted to Sigrok.
1015 for (i = 0; i < events_in_cluster; i++) {
1016 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1017 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1020 /* Send data up to trigger point (if triggered). */
1021 int trigger_offset = 0;
1024 * Trigger is not always accurate to sample because of
1025 * pipeline delay. However, it always triggers before
1026 * the actual event. We therefore look at the next
1027 * samples to pinpoint the exact position of the trigger.
1029 trigger_offset = get_trigger_offset(samples,
1030 ss->lastsample, &devc->trigger);
1032 if (trigger_offset > 0) {
1033 packet.type = SR_DF_LOGIC;
1034 logic.length = trigger_offset * logic.unitsize;
1035 sr_session_send(devc->cb_data, &packet);
1036 events_in_cluster -= trigger_offset;
1039 /* Only send trigger if explicitly enabled. */
1040 if (devc->use_triggers) {
1041 packet.type = SR_DF_TRIGGER;
1042 sr_session_send(devc->cb_data, &packet);
1046 if (events_in_cluster > 0) {
1047 packet.type = SR_DF_LOGIC;
1048 logic.length = events_in_cluster * logic.unitsize;
1049 logic.data = samples + (trigger_offset * logic.unitsize);
1050 sr_session_send(devc->cb_data, &packet);
1054 samples[2 * (events_in_cluster - 1) + 0] |
1055 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1060 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1061 * Each event is 20ns apart, and can contain multiple samples.
1063 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1064 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1065 * For 50 MHz and below, events contain one sample for each channel,
1066 * spread 20 ns apart.
1068 static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1069 uint16_t events_in_line,
1070 uint32_t trigger_event,
1073 struct sigma_dram_cluster *dram_cluster;
1074 struct sr_dev_inst *sdi = cb_data;
1075 struct dev_context *devc = sdi->priv;
1076 unsigned int clusters_in_line =
1077 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1078 unsigned int events_in_cluster;
1080 uint32_t trigger_cluster = ~0, triggered = 0;
1082 /* Check if trigger is in this chunk. */
1083 if (trigger_event < (64 * 7)) {
1084 if (devc->cur_samplerate <= SR_MHZ(50)) {
1085 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1089 /* Find in which cluster the trigger occured. */
1090 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1093 /* For each full DRAM cluster. */
1094 for (i = 0; i < clusters_in_line; i++) {
1095 dram_cluster = &dram_line->cluster[i];
1097 /* The last cluster might not be full. */
1098 if ((i == clusters_in_line - 1) &&
1099 (events_in_line % EVENTS_PER_CLUSTER)) {
1100 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1102 events_in_cluster = EVENTS_PER_CLUSTER;
1105 triggered = (i == trigger_cluster);
1106 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1113 static int download_capture(struct sr_dev_inst *sdi)
1115 struct dev_context *devc = sdi->priv;
1116 const int chunks_per_read = 32;
1117 struct sigma_dram_line *dram_line;
1119 uint32_t stoppos, triggerpos;
1120 struct sr_datafeed_packet packet;
1124 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1125 uint32_t dl_events_in_line = 64 * 7;
1126 uint32_t trg_line = ~0, trg_event = ~0;
1128 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1132 sr_info("Downloading sample data.");
1134 /* Stop acquisition. */
1135 sigma_set_register(WRITE_MODE, 0x11, devc);
1137 /* Set SDRAM Read Enable. */
1138 sigma_set_register(WRITE_MODE, 0x02, devc);
1140 /* Get the current position. */
1141 sigma_read_pos(&stoppos, &triggerpos, devc);
1143 /* Check if trigger has fired. */
1144 modestatus = sigma_get_register(READ_MODE, devc);
1145 if (modestatus & 0x20) {
1146 trg_line = triggerpos >> 9;
1147 trg_event = triggerpos & 0x1ff;
1151 * Determine how many 1024b "DRAM lines" do we need to read from the
1152 * Sigma so we have a complete set of samples. Note that the last
1153 * line can be only partial, containing less than 64 clusters.
1155 dl_lines_total = (stoppos >> 9) + 1;
1159 while (dl_lines_total > dl_lines_done) {
1160 /* We can download only up-to 32 DRAM lines in one go! */
1161 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1163 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1164 (uint8_t *)dram_line, devc);
1165 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1168 /* This is the first DRAM line, so find the initial timestamp. */
1169 if (dl_lines_done == 0) {
1170 devc->state.lastts =
1171 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1172 devc->state.lastsample = 0;
1175 for (i = 0; i < dl_lines_curr; i++) {
1176 uint32_t trigger_event = ~0;
1177 /* The last "DRAM line" can be only partially full. */
1178 if (dl_lines_done + i == dl_lines_total - 1)
1179 dl_events_in_line = stoppos & 0x1ff;
1181 /* Test if the trigger happened on this line. */
1182 if (dl_lines_done + i == trg_line)
1183 trigger_event = trg_event;
1185 decode_chunk_ts(dram_line + i, dl_events_in_line,
1186 trigger_event, sdi);
1189 dl_lines_done += dl_lines_curr;
1193 packet.type = SR_DF_END;
1194 sr_session_send(sdi, &packet);
1196 dev_acquisition_stop(sdi, sdi);
1204 * Handle the Sigma when in CAPTURE mode. This function checks:
1205 * - Sampling time ended
1206 * - DRAM capacity overflow
1207 * This function triggers download of the samples from Sigma
1208 * in case either of the above conditions is true.
1210 static int sigma_capture_mode(struct sr_dev_inst *sdi)
1212 struct dev_context *devc = sdi->priv;
1214 uint64_t running_msec;
1217 uint32_t stoppos, triggerpos;
1219 /* Check if the selected sampling duration passed. */
1220 gettimeofday(&tv, 0);
1221 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1222 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1223 if (running_msec >= devc->limit_msec)
1224 return download_capture(sdi);
1226 /* Get the position in DRAM to which the FPGA is writing now. */
1227 sigma_read_pos(&stoppos, &triggerpos, devc);
1228 /* Test if DRAM is full and if so, download the data. */
1229 if ((stoppos >> 9) == 32767)
1230 return download_capture(sdi);
1235 static int receive_data(int fd, int revents, void *cb_data)
1237 struct sr_dev_inst *sdi;
1238 struct dev_context *devc;
1246 if (devc->state.state == SIGMA_IDLE)
1249 if (devc->state.state == SIGMA_CAPTURE)
1250 return sigma_capture_mode(sdi);
1255 /* Build a LUT entry used by the trigger functions. */
1256 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1260 /* For each quad channel. */
1261 for (i = 0; i < 4; ++i) {
1264 /* For each bit in LUT. */
1265 for (j = 0; j < 16; ++j)
1267 /* For each channel in quad. */
1268 for (k = 0; k < 4; ++k) {
1269 bit = 1 << (i * 4 + k);
1271 /* Set bit in entry */
1273 ((!(value & bit)) !=
1275 entry[i] &= ~(1 << j);
1280 /* Add a logical function to LUT mask. */
1281 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1282 int index, int neg, uint16_t *mask)
1285 int x[2][2], tmp, a, b, aset, bset, rset;
1287 memset(x, 0, 4 * sizeof(int));
1289 /* Trigger detect condition. */
1319 case OP_NOTRISEFALL:
1325 /* Transpose if neg is set. */
1327 for (i = 0; i < 2; ++i) {
1328 for (j = 0; j < 2; ++j) {
1330 x[i][j] = x[1-i][1-j];
1336 /* Update mask with function. */
1337 for (i = 0; i < 16; ++i) {
1338 a = (i >> (2 * index + 0)) & 1;
1339 b = (i >> (2 * index + 1)) & 1;
1341 aset = (*mask >> i) & 1;
1344 if (func == FUNC_AND || func == FUNC_NAND)
1346 else if (func == FUNC_OR || func == FUNC_NOR)
1348 else if (func == FUNC_XOR || func == FUNC_NXOR)
1351 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1362 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1363 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1364 * set at any time, but a full mask and value can be set (0/1).
1366 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1369 uint16_t masks[2] = { 0, 0 };
1371 memset(lut, 0, sizeof(struct triggerlut));
1373 /* Contant for simple triggers. */
1376 /* Value/mask trigger support. */
1377 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1380 /* Rise/fall trigger support. */
1381 for (i = 0, j = 0; i < 16; ++i) {
1382 if (devc->trigger.risingmask & (1 << i) ||
1383 devc->trigger.fallingmask & (1 << i))
1384 masks[j++] = 1 << i;
1387 build_lut_entry(masks[0], masks[0], lut->m0d);
1388 build_lut_entry(masks[1], masks[1], lut->m1d);
1390 /* Add glue logic */
1391 if (masks[0] || masks[1]) {
1392 /* Transition trigger. */
1393 if (masks[0] & devc->trigger.risingmask)
1394 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1395 if (masks[0] & devc->trigger.fallingmask)
1396 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1397 if (masks[1] & devc->trigger.risingmask)
1398 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1399 if (masks[1] & devc->trigger.fallingmask)
1400 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1402 /* Only value/mask trigger. */
1406 /* Triggertype: event. */
1407 lut->params.selres = 3;
1412 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1414 struct dev_context *devc;
1415 struct clockselect_50 clockselect;
1416 int frac, triggerpin, ret;
1417 uint8_t triggerselect = 0;
1418 struct triggerinout triggerinout_conf;
1419 struct triggerlut lut;
1421 if (sdi->status != SR_ST_ACTIVE)
1422 return SR_ERR_DEV_CLOSED;
1426 if (convert_trigger(sdi) != SR_OK) {
1427 sr_err("Failed to configure triggers.");
1431 /* If the samplerate has not been set, default to 200 kHz. */
1432 if (devc->cur_firmware == -1) {
1433 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1437 /* Enter trigger programming mode. */
1438 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1440 /* 100 and 200 MHz mode. */
1441 if (devc->cur_samplerate >= SR_MHZ(100)) {
1442 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1444 /* Find which pin to trigger on from mask. */
1445 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1446 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1450 /* Set trigger pin and light LED on trigger. */
1451 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1453 /* Default rising edge. */
1454 if (devc->trigger.fallingmask)
1455 triggerselect |= 1 << 3;
1457 /* All other modes. */
1458 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1459 build_basic_trigger(&lut, devc);
1461 sigma_write_trigger_lut(&lut, devc);
1463 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1466 /* Setup trigger in and out pins to default values. */
1467 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1468 triggerinout_conf.trgout_bytrigger = 1;
1469 triggerinout_conf.trgout_enable = 1;
1471 sigma_write_register(WRITE_TRIGGER_OPTION,
1472 (uint8_t *) &triggerinout_conf,
1473 sizeof(struct triggerinout), devc);
1475 /* Go back to normal mode. */
1476 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1478 /* Set clock select register. */
1479 if (devc->cur_samplerate == SR_MHZ(200))
1480 /* Enable 4 channels. */
1481 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1482 else if (devc->cur_samplerate == SR_MHZ(100))
1483 /* Enable 8 channels. */
1484 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1487 * 50 MHz mode (or fraction thereof). Any fraction down to
1488 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1490 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1492 clockselect.async = 0;
1493 clockselect.fraction = frac;
1494 clockselect.disabled_channels = 0;
1496 sigma_write_register(WRITE_CLOCK_SELECT,
1497 (uint8_t *) &clockselect,
1498 sizeof(clockselect), devc);
1501 /* Setup maximum post trigger time. */
1502 sigma_set_register(WRITE_POST_TRIGGER,
1503 (devc->capture_ratio * 255) / 100, devc);
1505 /* Start acqusition. */
1506 gettimeofday(&devc->start_tv, 0);
1507 sigma_set_register(WRITE_MODE, 0x0d, devc);
1509 devc->cb_data = cb_data;
1511 /* Send header packet to the session bus. */
1512 std_session_send_df_header(cb_data, LOG_PREFIX);
1514 /* Add capture source. */
1515 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1517 devc->state.state = SIGMA_CAPTURE;
1522 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1524 struct dev_context *devc;
1529 devc->state.state = SIGMA_IDLE;
1531 sr_source_remove(0);
1536 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1537 .name = "asix-sigma",
1538 .longname = "ASIX SIGMA/SIGMA2",
1543 .dev_list = dev_list,
1544 .dev_clear = dev_clear,
1545 .config_get = config_get,
1546 .config_set = config_set,
1547 .config_list = config_list,
1548 .dev_open = dev_open,
1549 .dev_close = dev_close,
1550 .dev_acquisition_start = dev_acquisition_start,
1551 .dev_acquisition_stop = dev_acquisition_stop,