2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 /* Force the FPGA to reboot. */
84 static uint8_t suicide[] = {
85 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
88 /* Prepare to upload firmware (FPGA specific). */
89 static uint8_t init_array[] = {
90 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
93 /* Initialize the logic analyzer mode. */
94 static uint8_t logic_mode_start[] = {
95 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
96 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
99 static const char *firmware_files[] = {
100 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
101 "asix-sigma-100.fw", /* 100 MHz */
102 "asix-sigma-200.fw", /* 200 MHz */
103 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
104 "asix-sigma-phasor.fw", /* Frequency counter */
107 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
111 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
113 sr_err("ftdi_read_data failed: %s",
114 ftdi_get_error_string(&devc->ftdic));
120 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
124 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
126 sr_err("ftdi_write_data failed: %s",
127 ftdi_get_error_string(&devc->ftdic));
128 } else if ((size_t) ret != size) {
129 sr_err("ftdi_write_data did not complete write.");
135 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
136 struct dev_context *devc)
139 uint8_t buf[len + 2];
142 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
143 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
145 for (i = 0; i < len; ++i) {
146 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
147 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
150 return sigma_write(buf, idx, devc);
153 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
155 return sigma_write_register(reg, &value, 1, devc);
158 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
159 struct dev_context *devc)
163 buf[0] = REG_ADDR_LOW | (reg & 0xf);
164 buf[1] = REG_ADDR_HIGH | (reg >> 4);
165 buf[2] = REG_READ_ADDR;
167 sigma_write(buf, sizeof(buf), devc);
169 return sigma_read(data, len, devc);
172 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
176 if (1 != sigma_read_register(reg, &value, 1, devc)) {
177 sr_err("sigma_get_register: 1 byte expected");
184 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
185 struct dev_context *devc)
188 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 REG_READ_ADDR | NEXT_REG,
195 REG_READ_ADDR | NEXT_REG,
199 sigma_write(buf, sizeof(buf), devc);
201 sigma_read(result, sizeof(result), devc);
203 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
204 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
206 /* Not really sure why this must be done, but according to spec. */
207 if ((--*stoppos & 0x1ff) == 0x1ff)
210 if ((*--triggerpos & 0x1ff) == 0x1ff)
216 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
217 uint8_t *data, struct dev_context *devc)
223 /* Send the startchunk. Index start with 1. */
224 buf[0] = startchunk >> 8;
225 buf[1] = startchunk & 0xff;
226 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
229 buf[idx++] = REG_DRAM_BLOCK;
230 buf[idx++] = REG_DRAM_WAIT_ACK;
232 for (i = 0; i < numchunks; ++i) {
233 /* Alternate bit to copy from DRAM to cache. */
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
237 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
239 if (i != (numchunks - 1))
240 buf[idx++] = REG_DRAM_WAIT_ACK;
243 sigma_write(buf, idx, devc);
245 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
248 /* Upload trigger look-up tables to Sigma. */
249 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
255 /* Transpose the table and send to Sigma. */
256 for (i = 0; i < 16; ++i) {
261 if (lut->m2d[0] & bit)
263 if (lut->m2d[1] & bit)
265 if (lut->m2d[2] & bit)
267 if (lut->m2d[3] & bit)
277 if (lut->m0d[0] & bit)
279 if (lut->m0d[1] & bit)
281 if (lut->m0d[2] & bit)
283 if (lut->m0d[3] & bit)
286 if (lut->m1d[0] & bit)
288 if (lut->m1d[1] & bit)
290 if (lut->m1d[2] & bit)
292 if (lut->m1d[3] & bit)
295 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
297 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
300 /* Send the parameters */
301 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
302 sizeof(lut->params), devc);
307 /* Generate the bitbang stream for programming the FPGA. */
308 static int bin2bitbang(const char *filename,
309 unsigned char **buf, size_t *buf_size)
312 unsigned long file_size;
313 unsigned long offset = 0;
316 unsigned long fwsize = 0;
317 const int buffer_size = 65536;
320 uint32_t imm = 0x3f6df2ab;
322 f = g_fopen(filename, "rb");
324 sr_err("g_fopen(\"%s\", \"rb\")", filename);
328 if (-1 == fseek(f, 0, SEEK_END)) {
329 sr_err("fseek on %s failed", filename);
334 file_size = ftell(f);
336 fseek(f, 0, SEEK_SET);
338 if (!(firmware = g_try_malloc(buffer_size))) {
339 sr_err("%s: firmware malloc failed", __func__);
341 return SR_ERR_MALLOC;
344 while ((c = getc(f)) != EOF) {
345 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
346 firmware[fwsize++] = c ^ imm;
350 if(fwsize != file_size) {
351 sr_err("%s: Error reading firmware", filename);
357 *buf_size = fwsize * 2 * 8;
359 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
361 sr_err("%s: buf/p malloc failed", __func__);
363 return SR_ERR_MALLOC;
366 for (i = 0; i < fwsize; ++i) {
367 for (bit = 7; bit >= 0; --bit) {
368 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
369 p[offset++] = v | 0x01;
376 if (offset != *buf_size) {
378 sr_err("Error reading firmware %s "
379 "offset=%ld, file_size=%ld, buf_size=%zd.",
380 filename, offset, file_size, *buf_size);
388 static void clear_helper(void *priv)
390 struct dev_context *devc;
394 ftdi_deinit(&devc->ftdic);
397 static int dev_clear(void)
399 return std_dev_clear(di, clear_helper);
402 static int init(struct sr_context *sr_ctx)
404 return std_init(sr_ctx, di, LOG_PREFIX);
407 static GSList *scan(GSList *options)
409 struct sr_dev_inst *sdi;
410 struct sr_channel *ch;
411 struct drv_context *drvc;
412 struct dev_context *devc;
414 struct ftdi_device_list *devlist;
426 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
427 sr_err("%s: devc malloc failed", __func__);
431 ftdi_init(&devc->ftdic);
433 /* Look for SIGMAs. */
435 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
436 USB_VENDOR, USB_PRODUCT)) <= 0) {
438 sr_err("ftdi_usb_find_all(): %d", ret);
442 /* Make sure it's a version 1 or 2 SIGMA. */
443 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
444 serial_txt, sizeof(serial_txt));
445 sscanf(serial_txt, "%x", &serial);
447 if (serial < 0xa6010000 || serial > 0xa602ffff) {
448 sr_err("Only SIGMA and SIGMA2 are supported "
449 "in this version of libsigrok.");
453 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
455 devc->cur_samplerate = 0;
457 devc->limit_msec = 0;
458 devc->cur_firmware = -1;
459 devc->num_channels = 0;
460 devc->samples_per_event = 0;
461 devc->capture_ratio = 50;
462 devc->use_triggers = 0;
464 /* Register SIGMA device. */
465 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
466 USB_MODEL_NAME, NULL))) {
467 sr_err("%s: sdi was NULL", __func__);
472 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
473 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
477 sdi->channels = g_slist_append(sdi->channels, ch);
480 devices = g_slist_append(devices, sdi);
481 drvc->instances = g_slist_append(drvc->instances, sdi);
484 /* We will open the device again when we need it. */
485 ftdi_list_free(&devlist);
490 ftdi_deinit(&devc->ftdic);
495 static GSList *dev_list(void)
497 return ((struct drv_context *)(di->priv))->instances;
500 static int upload_firmware(int firmware_idx, struct dev_context *devc)
506 unsigned char result[32];
507 char firmware_path[128];
509 /* Make sure it's an ASIX SIGMA. */
510 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
511 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
512 sr_err("ftdi_usb_open failed: %s",
513 ftdi_get_error_string(&devc->ftdic));
517 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
518 sr_err("ftdi_set_bitmode failed: %s",
519 ftdi_get_error_string(&devc->ftdic));
523 /* Four times the speed of sigmalogan - Works well. */
524 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
525 sr_err("ftdi_set_baudrate failed: %s",
526 ftdi_get_error_string(&devc->ftdic));
530 /* Force the FPGA to reboot. */
531 sigma_write(suicide, sizeof(suicide), devc);
532 sigma_write(suicide, sizeof(suicide), devc);
533 sigma_write(suicide, sizeof(suicide), devc);
534 sigma_write(suicide, sizeof(suicide), devc);
536 /* Prepare to upload firmware (FPGA specific). */
537 sigma_write(init_array, sizeof(init_array), devc);
539 ftdi_usb_purge_buffers(&devc->ftdic);
541 /* Wait until the FPGA asserts INIT_B. */
543 ret = sigma_read(result, 1, devc);
544 if (result[0] & 0x20)
548 /* Prepare firmware. */
549 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
550 firmware_files[firmware_idx]);
552 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
553 sr_err("An error occured while reading the firmware: %s",
558 /* Upload firmare. */
559 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
560 sigma_write(buf, buf_size, devc);
564 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
565 sr_err("ftdi_set_bitmode failed: %s",
566 ftdi_get_error_string(&devc->ftdic));
570 ftdi_usb_purge_buffers(&devc->ftdic);
572 /* Discard garbage. */
573 while (1 == sigma_read(&pins, 1, devc))
576 /* Initialize the logic analyzer mode. */
577 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
579 /* Expect a 3 byte reply. */
580 ret = sigma_read(result, 3, devc);
582 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
583 sr_err("Configuration failed. Invalid reply received.");
587 devc->cur_firmware = firmware_idx;
589 sr_info("Firmware uploaded.");
594 static int dev_open(struct sr_dev_inst *sdi)
596 struct dev_context *devc;
601 /* Make sure it's an ASIX SIGMA. */
602 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
603 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
605 sr_err("ftdi_usb_open failed: %s",
606 ftdi_get_error_string(&devc->ftdic));
611 sdi->status = SR_ST_ACTIVE;
616 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
618 struct dev_context *devc;
625 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
626 if (samplerates[i] == samplerate)
629 if (samplerates[i] == 0)
630 return SR_ERR_SAMPLERATE;
632 if (samplerate <= SR_MHZ(50)) {
633 ret = upload_firmware(0, devc);
634 devc->num_channels = 16;
636 if (samplerate == SR_MHZ(100)) {
637 ret = upload_firmware(1, devc);
638 devc->num_channels = 8;
640 else if (samplerate == SR_MHZ(200)) {
641 ret = upload_firmware(2, devc);
642 devc->num_channels = 4;
645 devc->cur_samplerate = samplerate;
646 devc->period_ps = 1000000000000ULL / samplerate;
647 devc->samples_per_event = 16 / devc->num_channels;
648 devc->state.state = SIGMA_IDLE;
654 * In 100 and 200 MHz mode, only a single pin rising/falling can be
655 * set as trigger. In other modes, two rising/falling triggers can be set,
656 * in addition to value/mask trigger for any number of channels.
658 * The Sigma supports complex triggers using boolean expressions, but this
659 * has not been implemented yet.
661 static int configure_channels(const struct sr_dev_inst *sdi)
663 struct dev_context *devc = sdi->priv;
664 const struct sr_channel *ch;
669 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
671 for (l = sdi->channels; l; l = l->next) {
672 ch = (struct sr_channel *)l->data;
673 channelbit = 1 << (ch->index);
675 if (!ch->enabled || !ch->trigger)
678 if (devc->cur_samplerate >= SR_MHZ(100)) {
679 /* Fast trigger support. */
681 sr_err("Only a single pin trigger in 100 and "
682 "200MHz mode is supported.");
685 if (ch->trigger[0] == 'f')
686 devc->trigger.fallingmask |= channelbit;
687 else if (ch->trigger[0] == 'r')
688 devc->trigger.risingmask |= channelbit;
690 sr_err("Only rising/falling trigger in 100 "
691 "and 200MHz mode is supported.");
697 /* Simple trigger support (event). */
698 if (ch->trigger[0] == '1') {
699 devc->trigger.simplevalue |= channelbit;
700 devc->trigger.simplemask |= channelbit;
702 else if (ch->trigger[0] == '0') {
703 devc->trigger.simplevalue &= ~channelbit;
704 devc->trigger.simplemask |= channelbit;
706 else if (ch->trigger[0] == 'f') {
707 devc->trigger.fallingmask |= channelbit;
710 else if (ch->trigger[0] == 'r') {
711 devc->trigger.risingmask |= channelbit;
716 * Actually, Sigma supports 2 rising/falling triggers,
717 * but they are ORed and the current trigger syntax
718 * does not permit ORed triggers.
720 if (trigger_set > 1) {
721 sr_err("Only 1 rising/falling trigger "
728 devc->use_triggers = 1;
734 static int dev_close(struct sr_dev_inst *sdi)
736 struct dev_context *devc;
741 if (sdi->status == SR_ST_ACTIVE)
742 ftdi_usb_close(&devc->ftdic);
744 sdi->status = SR_ST_INACTIVE;
749 static int cleanup(void)
754 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
755 const struct sr_channel_group *cg)
757 struct dev_context *devc;
762 case SR_CONF_SAMPLERATE:
765 *data = g_variant_new_uint64(devc->cur_samplerate);
776 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
777 const struct sr_channel_group *cg)
779 struct dev_context *devc;
780 uint64_t num_samples;
785 if (sdi->status != SR_ST_ACTIVE)
786 return SR_ERR_DEV_CLOSED;
791 case SR_CONF_SAMPLERATE:
792 ret = set_samplerate(sdi, g_variant_get_uint64(data));
794 case SR_CONF_LIMIT_MSEC:
795 devc->limit_msec = g_variant_get_uint64(data);
796 if (devc->limit_msec > 0)
801 case SR_CONF_LIMIT_SAMPLES:
802 num_samples = g_variant_get_uint64(data);
803 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
805 case SR_CONF_CAPTURE_RATIO:
806 devc->capture_ratio = g_variant_get_uint64(data);
807 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
819 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
820 const struct sr_channel_group *cg)
829 case SR_CONF_DEVICE_OPTIONS:
830 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
831 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
833 case SR_CONF_SAMPLERATE:
834 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
835 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
836 ARRAY_SIZE(samplerates), sizeof(uint64_t));
837 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
838 *data = g_variant_builder_end(&gvb);
840 case SR_CONF_TRIGGER_TYPE:
841 *data = g_variant_new_string(TRIGGER_TYPE);
850 /* Software trigger to determine exact trigger position. */
851 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
852 struct sigma_trigger *t)
856 for (i = 0; i < 8; ++i) {
858 last_sample = samples[i-1];
860 /* Simple triggers. */
861 if ((samples[i] & t->simplemask) != t->simplevalue)
865 if ((last_sample & t->risingmask) != 0 || (samples[i] &
866 t->risingmask) != t->risingmask)
870 if ((last_sample & t->fallingmask) != t->fallingmask ||
871 (samples[i] & t->fallingmask) != 0)
877 /* If we did not match, return original trigger pos. */
882 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
883 * Each event is 20ns apart, and can contain multiple samples.
885 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
886 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
887 * For 50 MHz and below, events contain one sample for each channel,
888 * spread 20 ns apart.
890 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
891 uint16_t *lastsample, int triggerpos,
892 uint16_t limit_chunk, void *cb_data)
894 struct sr_dev_inst *sdi = cb_data;
895 struct dev_context *devc = sdi->priv;
897 uint16_t samples[65536 * devc->samples_per_event];
898 struct sr_datafeed_packet packet;
899 struct sr_datafeed_logic logic;
900 int i, j, k, l, numpad, tosend;
901 size_t n = 0, sent = 0;
902 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
907 /* Check if trigger is in this chunk. */
908 if (triggerpos != -1) {
909 if (devc->cur_samplerate <= SR_MHZ(50))
910 triggerpos -= EVENTS_PER_CLUSTER - 1;
915 /* Find in which cluster the trigger occured. */
916 triggerts = triggerpos / 7;
920 for (i = 0; i < 64; ++i) {
921 ts = *(uint16_t *) &buf[i * 16];
922 tsdiff = ts - *lastts;
925 /* Decode partial chunk. */
926 if (limit_chunk && ts > limit_chunk)
929 /* Pad last sample up to current point. */
930 numpad = tsdiff * devc->samples_per_event - clustersize;
932 for (j = 0; j < numpad; ++j)
933 samples[j] = *lastsample;
938 /* Send samples between previous and this timestamp to sigrok. */
941 tosend = MIN(2048, n - sent);
943 packet.type = SR_DF_LOGIC;
944 packet.payload = &logic;
945 logic.length = tosend * sizeof(uint16_t);
947 logic.data = samples + sent;
948 sr_session_send(devc->cb_data, &packet);
954 event = (uint16_t *) &buf[i * 16 + 2];
957 /* For each event in cluster. */
958 for (j = 0; j < 7; ++j) {
960 /* For each sample in event. */
961 for (k = 0; k < devc->samples_per_event; ++k) {
964 /* For each channel. */
965 for (l = 0; l < devc->num_channels; ++l)
966 cur_sample |= (!!(event[j] & (1 << (l *
967 devc->samples_per_event + k)))) << l;
969 samples[n++] = cur_sample;
973 /* Send data up to trigger point (if triggered). */
975 if (i == triggerts) {
977 * Trigger is not always accurate to sample because of
978 * pipeline delay. However, it always triggers before
979 * the actual event. We therefore look at the next
980 * samples to pinpoint the exact position of the trigger.
982 tosend = get_trigger_offset(samples, *lastsample,
986 packet.type = SR_DF_LOGIC;
987 packet.payload = &logic;
988 logic.length = tosend * sizeof(uint16_t);
990 logic.data = samples;
991 sr_session_send(devc->cb_data, &packet);
996 /* Only send trigger if explicitly enabled. */
997 if (devc->use_triggers) {
998 packet.type = SR_DF_TRIGGER;
999 sr_session_send(devc->cb_data, &packet);
1003 /* Send rest of the chunk to sigrok. */
1007 packet.type = SR_DF_LOGIC;
1008 packet.payload = &logic;
1009 logic.length = tosend * sizeof(uint16_t);
1011 logic.data = samples + sent;
1012 sr_session_send(devc->cb_data, &packet);
1015 *lastsample = samples[n - 1];
1021 static void download_capture(struct sr_dev_inst *sdi)
1023 struct dev_context *devc;
1024 const int chunks_per_read = 32;
1025 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1026 int bufsz, i, numchunks, newchunks;
1028 sr_info("Downloading sample data.");
1031 devc->state.chunks_downloaded = 0;
1032 numchunks = (devc->state.stoppos + 511) / 512;
1033 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1035 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1036 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1039 /* Find first ts. */
1040 if (devc->state.chunks_downloaded == 0) {
1041 devc->state.lastts = RL16(buf) - 1;
1042 devc->state.lastsample = 0;
1045 /* Decode chunks and send them to sigrok. */
1046 for (i = 0; i < newchunks; ++i) {
1047 int limit_chunk = 0;
1049 /* The last chunk may potentially be only in part. */
1050 if (devc->state.chunks_downloaded == numchunks - 1) {
1051 /* Find the last valid timestamp */
1052 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1055 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1056 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1057 &devc->state.lastts,
1058 &devc->state.lastsample,
1059 devc->state.triggerpos & 0x1ff,
1062 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1063 &devc->state.lastts,
1064 &devc->state.lastsample,
1065 -1, limit_chunk, sdi);
1067 ++devc->state.chunks_downloaded;
1072 static int receive_data(int fd, int revents, void *cb_data)
1074 struct sr_dev_inst *sdi;
1075 struct dev_context *devc;
1076 struct sr_datafeed_packet packet;
1077 uint64_t running_msec;
1088 /* Get the current position. */
1089 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1091 if (devc->state.state == SIGMA_IDLE)
1094 if (devc->state.state == SIGMA_CAPTURE) {
1095 numchunks = (devc->state.stoppos + 511) / 512;
1097 /* Check if the timer has expired, or memory is full. */
1098 gettimeofday(&tv, 0);
1099 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1100 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1102 if (running_msec < devc->limit_msec && numchunks < 32767)
1103 /* Still capturing. */
1106 /* Stop acquisition. */
1107 sigma_set_register(WRITE_MODE, 0x11, devc);
1109 /* Set SDRAM Read Enable. */
1110 sigma_set_register(WRITE_MODE, 0x02, devc);
1112 /* Get the current position. */
1113 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1115 /* Check if trigger has fired. */
1116 modestatus = sigma_get_register(READ_MODE, devc);
1117 if (modestatus & 0x20)
1118 devc->state.triggerchunk = devc->state.triggerpos / 512;
1120 devc->state.triggerchunk = -1;
1122 /* Transfer captured data from device. */
1123 download_capture(sdi);
1126 packet.type = SR_DF_END;
1127 sr_session_send(sdi, &packet);
1129 dev_acquisition_stop(sdi, sdi);
1135 /* Build a LUT entry used by the trigger functions. */
1136 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1140 /* For each quad channel. */
1141 for (i = 0; i < 4; ++i) {
1144 /* For each bit in LUT. */
1145 for (j = 0; j < 16; ++j)
1147 /* For each channel in quad. */
1148 for (k = 0; k < 4; ++k) {
1149 bit = 1 << (i * 4 + k);
1151 /* Set bit in entry */
1153 ((!(value & bit)) !=
1155 entry[i] &= ~(1 << j);
1160 /* Add a logical function to LUT mask. */
1161 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1162 int index, int neg, uint16_t *mask)
1165 int x[2][2], tmp, a, b, aset, bset, rset;
1167 memset(x, 0, 4 * sizeof(int));
1169 /* Trigger detect condition. */
1199 case OP_NOTRISEFALL:
1205 /* Transpose if neg is set. */
1207 for (i = 0; i < 2; ++i) {
1208 for (j = 0; j < 2; ++j) {
1210 x[i][j] = x[1-i][1-j];
1216 /* Update mask with function. */
1217 for (i = 0; i < 16; ++i) {
1218 a = (i >> (2 * index + 0)) & 1;
1219 b = (i >> (2 * index + 1)) & 1;
1221 aset = (*mask >> i) & 1;
1224 if (func == FUNC_AND || func == FUNC_NAND)
1226 else if (func == FUNC_OR || func == FUNC_NOR)
1228 else if (func == FUNC_XOR || func == FUNC_NXOR)
1231 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1242 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1243 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1244 * set at any time, but a full mask and value can be set (0/1).
1246 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1249 uint16_t masks[2] = { 0, 0 };
1251 memset(lut, 0, sizeof(struct triggerlut));
1253 /* Contant for simple triggers. */
1256 /* Value/mask trigger support. */
1257 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1260 /* Rise/fall trigger support. */
1261 for (i = 0, j = 0; i < 16; ++i) {
1262 if (devc->trigger.risingmask & (1 << i) ||
1263 devc->trigger.fallingmask & (1 << i))
1264 masks[j++] = 1 << i;
1267 build_lut_entry(masks[0], masks[0], lut->m0d);
1268 build_lut_entry(masks[1], masks[1], lut->m1d);
1270 /* Add glue logic */
1271 if (masks[0] || masks[1]) {
1272 /* Transition trigger. */
1273 if (masks[0] & devc->trigger.risingmask)
1274 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1275 if (masks[0] & devc->trigger.fallingmask)
1276 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1277 if (masks[1] & devc->trigger.risingmask)
1278 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1279 if (masks[1] & devc->trigger.fallingmask)
1280 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1282 /* Only value/mask trigger. */
1286 /* Triggertype: event. */
1287 lut->params.selres = 3;
1292 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1294 struct dev_context *devc;
1295 struct clockselect_50 clockselect;
1296 int frac, triggerpin, ret;
1297 uint8_t triggerselect = 0;
1298 struct triggerinout triggerinout_conf;
1299 struct triggerlut lut;
1301 if (sdi->status != SR_ST_ACTIVE)
1302 return SR_ERR_DEV_CLOSED;
1306 if (configure_channels(sdi) != SR_OK) {
1307 sr_err("Failed to configure channels.");
1311 /* If the samplerate has not been set, default to 200 kHz. */
1312 if (devc->cur_firmware == -1) {
1313 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1317 /* Enter trigger programming mode. */
1318 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1320 /* 100 and 200 MHz mode. */
1321 if (devc->cur_samplerate >= SR_MHZ(100)) {
1322 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1324 /* Find which pin to trigger on from mask. */
1325 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1326 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1330 /* Set trigger pin and light LED on trigger. */
1331 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1333 /* Default rising edge. */
1334 if (devc->trigger.fallingmask)
1335 triggerselect |= 1 << 3;
1337 /* All other modes. */
1338 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1339 build_basic_trigger(&lut, devc);
1341 sigma_write_trigger_lut(&lut, devc);
1343 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1346 /* Setup trigger in and out pins to default values. */
1347 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1348 triggerinout_conf.trgout_bytrigger = 1;
1349 triggerinout_conf.trgout_enable = 1;
1351 sigma_write_register(WRITE_TRIGGER_OPTION,
1352 (uint8_t *) &triggerinout_conf,
1353 sizeof(struct triggerinout), devc);
1355 /* Go back to normal mode. */
1356 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1358 /* Set clock select register. */
1359 if (devc->cur_samplerate == SR_MHZ(200))
1360 /* Enable 4 channels. */
1361 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1362 else if (devc->cur_samplerate == SR_MHZ(100))
1363 /* Enable 8 channels. */
1364 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1367 * 50 MHz mode (or fraction thereof). Any fraction down to
1368 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1370 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1372 clockselect.async = 0;
1373 clockselect.fraction = frac;
1374 clockselect.disabled_channels = 0;
1376 sigma_write_register(WRITE_CLOCK_SELECT,
1377 (uint8_t *) &clockselect,
1378 sizeof(clockselect), devc);
1381 /* Setup maximum post trigger time. */
1382 sigma_set_register(WRITE_POST_TRIGGER,
1383 (devc->capture_ratio * 255) / 100, devc);
1385 /* Start acqusition. */
1386 gettimeofday(&devc->start_tv, 0);
1387 sigma_set_register(WRITE_MODE, 0x0d, devc);
1389 devc->cb_data = cb_data;
1391 /* Send header packet to the session bus. */
1392 std_session_send_df_header(cb_data, LOG_PREFIX);
1394 /* Add capture source. */
1395 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1397 devc->state.state = SIGMA_CAPTURE;
1402 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1404 struct dev_context *devc;
1409 devc->state.state = SIGMA_IDLE;
1411 sr_source_remove(0);
1416 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1417 .name = "asix-sigma",
1418 .longname = "ASIX SIGMA/SIGMA2",
1423 .dev_list = dev_list,
1424 .dev_clear = dev_clear,
1425 .config_get = config_get,
1426 .config_set = config_set,
1427 .config_list = config_list,
1428 .dev_open = dev_open,
1429 .dev_close = dev_close,
1430 .dev_acquisition_start = dev_acquisition_start,
1431 .dev_acquisition_stop = dev_acquisition_stop,