2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define TRIGGER_TYPE "rf10"
41 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42 static struct sr_dev_driver *di = &asix_sigma_driver_info;
43 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
51 static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
69 static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
74 static const int32_t hwcaps[] = {
75 SR_CONF_LOGIC_ANALYZER,
78 SR_CONF_CAPTURE_RATIO,
80 SR_CONF_LIMIT_SAMPLES,
83 static const char *sigma_firmware_files[] = {
84 /* 50 MHz, supports 8 bit fractions */
85 FIRMWARE_DIR "/asix-sigma-50.fw",
87 FIRMWARE_DIR "/asix-sigma-100.fw",
89 FIRMWARE_DIR "/asix-sigma-200.fw",
90 /* Synchronous clock from pin */
91 FIRMWARE_DIR "/asix-sigma-50sync.fw",
92 /* Frequency counter */
93 FIRMWARE_DIR "/asix-sigma-phasor.fw",
96 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
100 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
102 sr_err("ftdi_read_data failed: %s",
103 ftdi_get_error_string(&devc->ftdic));
109 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
113 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
115 sr_err("ftdi_write_data failed: %s",
116 ftdi_get_error_string(&devc->ftdic));
117 } else if ((size_t) ret != size) {
118 sr_err("ftdi_write_data did not complete write.");
124 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
125 struct dev_context *devc)
128 uint8_t buf[len + 2];
131 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
132 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
134 for (i = 0; i < len; ++i) {
135 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
136 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
139 return sigma_write(buf, idx, devc);
142 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
144 return sigma_write_register(reg, &value, 1, devc);
147 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
148 struct dev_context *devc)
152 buf[0] = REG_ADDR_LOW | (reg & 0xf);
153 buf[1] = REG_ADDR_HIGH | (reg >> 4);
154 buf[2] = REG_READ_ADDR;
156 sigma_write(buf, sizeof(buf), devc);
158 return sigma_read(data, len, devc);
161 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
165 if (1 != sigma_read_register(reg, &value, 1, devc)) {
166 sr_err("sigma_get_register: 1 byte expected");
173 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
174 struct dev_context *devc)
177 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
179 REG_READ_ADDR | NEXT_REG,
180 REG_READ_ADDR | NEXT_REG,
181 REG_READ_ADDR | NEXT_REG,
182 REG_READ_ADDR | NEXT_REG,
183 REG_READ_ADDR | NEXT_REG,
184 REG_READ_ADDR | NEXT_REG,
188 sigma_write(buf, sizeof(buf), devc);
190 sigma_read(result, sizeof(result), devc);
192 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
193 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
195 /* Not really sure why this must be done, but according to spec. */
196 if ((--*stoppos & 0x1ff) == 0x1ff)
199 if ((*--triggerpos & 0x1ff) == 0x1ff)
205 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
206 uint8_t *data, struct dev_context *devc)
212 /* Send the startchunk. Index start with 1. */
213 buf[0] = startchunk >> 8;
214 buf[1] = startchunk & 0xff;
215 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
218 buf[idx++] = REG_DRAM_BLOCK;
219 buf[idx++] = REG_DRAM_WAIT_ACK;
221 for (i = 0; i < numchunks; ++i) {
222 /* Alternate bit to copy from DRAM to cache. */
223 if (i != (numchunks - 1))
224 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
226 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
228 if (i != (numchunks - 1))
229 buf[idx++] = REG_DRAM_WAIT_ACK;
232 sigma_write(buf, idx, devc);
234 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
237 /* Upload trigger look-up tables to Sigma. */
238 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
244 /* Transpose the table and send to Sigma. */
245 for (i = 0; i < 16; ++i) {
250 if (lut->m2d[0] & bit)
252 if (lut->m2d[1] & bit)
254 if (lut->m2d[2] & bit)
256 if (lut->m2d[3] & bit)
266 if (lut->m0d[0] & bit)
268 if (lut->m0d[1] & bit)
270 if (lut->m0d[2] & bit)
272 if (lut->m0d[3] & bit)
275 if (lut->m1d[0] & bit)
277 if (lut->m1d[1] & bit)
279 if (lut->m1d[2] & bit)
281 if (lut->m1d[3] & bit)
284 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
286 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
289 /* Send the parameters */
290 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
291 sizeof(lut->params), devc);
296 static void clear_helper(void *priv)
298 struct dev_context *devc;
302 ftdi_deinit(&devc->ftdic);
305 static int dev_clear(void)
307 return std_dev_clear(di, clear_helper);
310 static int init(struct sr_context *sr_ctx)
312 return std_init(sr_ctx, di, LOG_PREFIX);
315 static GSList *scan(GSList *options)
317 struct sr_dev_inst *sdi;
318 struct sr_channel *ch;
319 struct drv_context *drvc;
320 struct dev_context *devc;
322 struct ftdi_device_list *devlist;
334 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
335 sr_err("%s: devc malloc failed", __func__);
339 ftdi_init(&devc->ftdic);
341 /* Look for SIGMAs. */
343 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
344 USB_VENDOR, USB_PRODUCT)) <= 0) {
346 sr_err("ftdi_usb_find_all(): %d", ret);
350 /* Make sure it's a version 1 or 2 SIGMA. */
351 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
352 serial_txt, sizeof(serial_txt));
353 sscanf(serial_txt, "%x", &serial);
355 if (serial < 0xa6010000 || serial > 0xa602ffff) {
356 sr_err("Only SIGMA and SIGMA2 are supported "
357 "in this version of libsigrok.");
361 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
363 devc->cur_samplerate = 0;
365 devc->limit_msec = 0;
366 devc->cur_firmware = -1;
367 devc->num_channels = 0;
368 devc->samples_per_event = 0;
369 devc->capture_ratio = 50;
370 devc->use_triggers = 0;
372 /* Register SIGMA device. */
373 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
374 USB_MODEL_NAME, NULL))) {
375 sr_err("%s: sdi was NULL", __func__);
380 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
381 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
385 sdi->channels = g_slist_append(sdi->channels, ch);
388 devices = g_slist_append(devices, sdi);
389 drvc->instances = g_slist_append(drvc->instances, sdi);
392 /* We will open the device again when we need it. */
393 ftdi_list_free(&devlist);
398 ftdi_deinit(&devc->ftdic);
403 static GSList *dev_list(void)
405 return ((struct drv_context *)(di->priv))->instances;
409 * Configure the FPGA for bitbang mode.
410 * This sequence is documented in section 2. of the ASIX Sigma programming
411 * manual. This sequence is necessary to configure the FPGA in the Sigma
412 * into Bitbang mode, in which it can be programmed with the firmware.
414 static int sigma_fpga_init_bitbang(struct dev_context *devc)
416 uint8_t suicide[] = {
417 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
419 uint8_t init_array[] = {
420 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
423 int i, ret, timeout = 10000;
426 /* Section 2. part 1), do the FPGA suicide. */
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430 sigma_write(suicide, sizeof(suicide), devc);
432 /* Section 2. part 2), do pulse on D1. */
433 sigma_write(init_array, sizeof(init_array), devc);
434 ftdi_usb_purge_buffers(&devc->ftdic);
436 /* Wait until the FPGA asserts D6/INIT_B. */
437 for (i = 0; i < timeout; i++) {
438 ret = sigma_read(&data, 1, devc);
441 /* Test if pin D6 got asserted. */
444 /* The D6 was not asserted yet, wait a bit. */
448 return SR_ERR_TIMEOUT;
452 * Configure the FPGA for logic-analyzer mode.
454 static int sigma_fpga_init_la(struct dev_context *devc)
456 /* Initialize the logic analyzer mode. */
457 uint8_t logic_mode_start[] = {
458 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
459 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
465 /* Initialize the logic analyzer mode. */
466 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
468 /* Expect a 3 byte reply. */
469 ret = sigma_read(result, 3, devc);
473 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
478 sr_err("Configuration failed. Invalid reply received.");
483 * Read the firmware from a file and transform it into a series of bitbang
484 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
485 * by the caller of this function.
487 static int sigma_fw_2_bitbang(const char *filename,
488 uint8_t **bb_cmd, gsize *bb_cmd_size)
492 gsize i, file_size, bb_size;
494 uint8_t *bb_stream, *bbs;
500 * Map the file and make the mapped buffer writable.
501 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
502 * will be modified. It will not be modified until someone uses
503 * g_file_set_contents() on it.
506 file = g_mapped_file_new(filename, TRUE, &error);
507 g_assert_no_error(error);
509 file_size = g_mapped_file_get_length(file);
510 firmware = g_mapped_file_get_contents(file);
513 /* Weird magic transformation below, I have no idea what it does. */
515 for (i = 0; i < file_size; i++) {
516 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
517 firmware[i] ^= imm & 0xff;
521 * Now that the firmware is "transformed", we will transcribe the
522 * firmware blob into a sequence of toggles of the Dx wires. This
523 * sequence will be fed directly into the Sigma, which must be in
524 * the FPGA bitbang programming mode.
527 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
528 bb_size = file_size * 8 * 2;
529 bb_stream = (uint8_t *)g_try_malloc(bb_size);
531 sr_err("%s: Failed to allocate bitbang stream", __func__);
537 for (i = 0; i < file_size; i++) {
538 for (bit = 7; bit >= 0; bit--) {
539 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
545 /* The transformation completed successfully, return the result. */
547 *bb_cmd_size = bb_size;
550 g_mapped_file_unref(file);
554 static int upload_firmware(int firmware_idx, struct dev_context *devc)
560 const char *firmware = sigma_firmware_files[firmware_idx];
561 struct ftdi_context *ftdic = &devc->ftdic;
563 /* Make sure it's an ASIX SIGMA. */
564 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
565 USB_DESCRIPTION, NULL);
567 sr_err("ftdi_usb_open failed: %s",
568 ftdi_get_error_string(ftdic));
572 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
574 sr_err("ftdi_set_bitmode failed: %s",
575 ftdi_get_error_string(ftdic));
579 /* Four times the speed of sigmalogan - Works well. */
580 ret = ftdi_set_baudrate(ftdic, 750000);
582 sr_err("ftdi_set_baudrate failed: %s",
583 ftdi_get_error_string(ftdic));
587 /* Initialize the FPGA for firmware upload. */
588 ret = sigma_fpga_init_bitbang(devc);
592 /* Prepare firmware. */
593 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
595 sr_err("An error occured while reading the firmware: %s",
600 /* Upload firmare. */
601 sr_info("Uploading firmware file '%s'.", firmware);
602 sigma_write(buf, buf_size, devc);
606 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
608 sr_err("ftdi_set_bitmode failed: %s",
609 ftdi_get_error_string(ftdic));
613 ftdi_usb_purge_buffers(ftdic);
615 /* Discard garbage. */
616 while (sigma_read(&pins, 1, devc) == 1)
619 /* Initialize the FPGA for logic-analyzer mode. */
620 ret = sigma_fpga_init_la(devc);
624 devc->cur_firmware = firmware_idx;
626 sr_info("Firmware uploaded.");
631 static int dev_open(struct sr_dev_inst *sdi)
633 struct dev_context *devc;
638 /* Make sure it's an ASIX SIGMA. */
639 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
640 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
642 sr_err("ftdi_usb_open failed: %s",
643 ftdi_get_error_string(&devc->ftdic));
648 sdi->status = SR_ST_ACTIVE;
653 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
655 struct dev_context *devc;
662 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
663 if (samplerates[i] == samplerate)
666 if (samplerates[i] == 0)
667 return SR_ERR_SAMPLERATE;
669 if (samplerate <= SR_MHZ(50)) {
670 ret = upload_firmware(0, devc);
671 devc->num_channels = 16;
673 if (samplerate == SR_MHZ(100)) {
674 ret = upload_firmware(1, devc);
675 devc->num_channels = 8;
677 else if (samplerate == SR_MHZ(200)) {
678 ret = upload_firmware(2, devc);
679 devc->num_channels = 4;
682 devc->cur_samplerate = samplerate;
683 devc->period_ps = 1000000000000ULL / samplerate;
684 devc->samples_per_event = 16 / devc->num_channels;
685 devc->state.state = SIGMA_IDLE;
691 * In 100 and 200 MHz mode, only a single pin rising/falling can be
692 * set as trigger. In other modes, two rising/falling triggers can be set,
693 * in addition to value/mask trigger for any number of channels.
695 * The Sigma supports complex triggers using boolean expressions, but this
696 * has not been implemented yet.
698 static int configure_channels(const struct sr_dev_inst *sdi)
700 struct dev_context *devc = sdi->priv;
701 const struct sr_channel *ch;
706 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
708 for (l = sdi->channels; l; l = l->next) {
709 ch = (struct sr_channel *)l->data;
710 channelbit = 1 << (ch->index);
712 if (!ch->enabled || !ch->trigger)
715 if (devc->cur_samplerate >= SR_MHZ(100)) {
716 /* Fast trigger support. */
718 sr_err("Only a single pin trigger in 100 and "
719 "200MHz mode is supported.");
722 if (ch->trigger[0] == 'f')
723 devc->trigger.fallingmask |= channelbit;
724 else if (ch->trigger[0] == 'r')
725 devc->trigger.risingmask |= channelbit;
727 sr_err("Only rising/falling trigger in 100 "
728 "and 200MHz mode is supported.");
734 /* Simple trigger support (event). */
735 if (ch->trigger[0] == '1') {
736 devc->trigger.simplevalue |= channelbit;
737 devc->trigger.simplemask |= channelbit;
739 else if (ch->trigger[0] == '0') {
740 devc->trigger.simplevalue &= ~channelbit;
741 devc->trigger.simplemask |= channelbit;
743 else if (ch->trigger[0] == 'f') {
744 devc->trigger.fallingmask |= channelbit;
747 else if (ch->trigger[0] == 'r') {
748 devc->trigger.risingmask |= channelbit;
753 * Actually, Sigma supports 2 rising/falling triggers,
754 * but they are ORed and the current trigger syntax
755 * does not permit ORed triggers.
757 if (trigger_set > 1) {
758 sr_err("Only 1 rising/falling trigger "
765 devc->use_triggers = 1;
771 static int dev_close(struct sr_dev_inst *sdi)
773 struct dev_context *devc;
778 if (sdi->status == SR_ST_ACTIVE)
779 ftdi_usb_close(&devc->ftdic);
781 sdi->status = SR_ST_INACTIVE;
786 static int cleanup(void)
791 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
792 const struct sr_channel_group *cg)
794 struct dev_context *devc;
799 case SR_CONF_SAMPLERATE:
802 *data = g_variant_new_uint64(devc->cur_samplerate);
813 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi,
814 const struct sr_channel_group *cg)
816 struct dev_context *devc;
817 uint64_t num_samples;
822 if (sdi->status != SR_ST_ACTIVE)
823 return SR_ERR_DEV_CLOSED;
828 case SR_CONF_SAMPLERATE:
829 ret = set_samplerate(sdi, g_variant_get_uint64(data));
831 case SR_CONF_LIMIT_MSEC:
832 devc->limit_msec = g_variant_get_uint64(data);
833 if (devc->limit_msec > 0)
838 case SR_CONF_LIMIT_SAMPLES:
839 num_samples = g_variant_get_uint64(data);
840 devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
842 case SR_CONF_CAPTURE_RATIO:
843 devc->capture_ratio = g_variant_get_uint64(data);
844 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
856 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi,
857 const struct sr_channel_group *cg)
866 case SR_CONF_DEVICE_OPTIONS:
867 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
868 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
870 case SR_CONF_SAMPLERATE:
871 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
872 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
873 ARRAY_SIZE(samplerates), sizeof(uint64_t));
874 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
875 *data = g_variant_builder_end(&gvb);
877 case SR_CONF_TRIGGER_TYPE:
878 *data = g_variant_new_string(TRIGGER_TYPE);
887 /* Software trigger to determine exact trigger position. */
888 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
889 struct sigma_trigger *t)
893 for (i = 0; i < 8; ++i) {
895 last_sample = samples[i-1];
897 /* Simple triggers. */
898 if ((samples[i] & t->simplemask) != t->simplevalue)
902 if ((last_sample & t->risingmask) != 0 || (samples[i] &
903 t->risingmask) != t->risingmask)
907 if ((last_sample & t->fallingmask) != t->fallingmask ||
908 (samples[i] & t->fallingmask) != 0)
914 /* If we did not match, return original trigger pos. */
919 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
920 * Each event is 20ns apart, and can contain multiple samples.
922 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
923 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
924 * For 50 MHz and below, events contain one sample for each channel,
925 * spread 20 ns apart.
927 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
928 uint16_t *lastsample, int triggerpos,
929 uint16_t limit_chunk, void *cb_data)
931 struct sr_dev_inst *sdi = cb_data;
932 struct dev_context *devc = sdi->priv;
934 uint16_t samples[65536 * devc->samples_per_event];
935 struct sr_datafeed_packet packet;
936 struct sr_datafeed_logic logic;
937 int i, j, k, l, numpad, tosend;
938 size_t n = 0, sent = 0;
939 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
944 /* Check if trigger is in this chunk. */
945 if (triggerpos != -1) {
946 if (devc->cur_samplerate <= SR_MHZ(50))
947 triggerpos -= EVENTS_PER_CLUSTER - 1;
952 /* Find in which cluster the trigger occured. */
953 triggerts = triggerpos / 7;
957 for (i = 0; i < 64; ++i) {
958 ts = *(uint16_t *) &buf[i * 16];
959 tsdiff = ts - *lastts;
962 /* Decode partial chunk. */
963 if (limit_chunk && ts > limit_chunk)
966 /* Pad last sample up to current point. */
967 numpad = tsdiff * devc->samples_per_event - clustersize;
969 for (j = 0; j < numpad; ++j)
970 samples[j] = *lastsample;
975 /* Send samples between previous and this timestamp to sigrok. */
978 tosend = MIN(2048, n - sent);
980 packet.type = SR_DF_LOGIC;
981 packet.payload = &logic;
982 logic.length = tosend * sizeof(uint16_t);
984 logic.data = samples + sent;
985 sr_session_send(devc->cb_data, &packet);
991 event = (uint16_t *) &buf[i * 16 + 2];
994 /* For each event in cluster. */
995 for (j = 0; j < 7; ++j) {
997 /* For each sample in event. */
998 for (k = 0; k < devc->samples_per_event; ++k) {
1001 /* For each channel. */
1002 for (l = 0; l < devc->num_channels; ++l)
1003 cur_sample |= (!!(event[j] & (1 << (l *
1004 devc->samples_per_event + k)))) << l;
1006 samples[n++] = cur_sample;
1010 /* Send data up to trigger point (if triggered). */
1012 if (i == triggerts) {
1014 * Trigger is not always accurate to sample because of
1015 * pipeline delay. However, it always triggers before
1016 * the actual event. We therefore look at the next
1017 * samples to pinpoint the exact position of the trigger.
1019 tosend = get_trigger_offset(samples, *lastsample,
1023 packet.type = SR_DF_LOGIC;
1024 packet.payload = &logic;
1025 logic.length = tosend * sizeof(uint16_t);
1027 logic.data = samples;
1028 sr_session_send(devc->cb_data, &packet);
1033 /* Only send trigger if explicitly enabled. */
1034 if (devc->use_triggers) {
1035 packet.type = SR_DF_TRIGGER;
1036 sr_session_send(devc->cb_data, &packet);
1040 /* Send rest of the chunk to sigrok. */
1044 packet.type = SR_DF_LOGIC;
1045 packet.payload = &logic;
1046 logic.length = tosend * sizeof(uint16_t);
1048 logic.data = samples + sent;
1049 sr_session_send(devc->cb_data, &packet);
1052 *lastsample = samples[n - 1];
1058 static void download_capture(struct sr_dev_inst *sdi)
1060 struct dev_context *devc;
1061 const int chunks_per_read = 32;
1062 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1063 int bufsz, i, numchunks, newchunks;
1065 sr_info("Downloading sample data.");
1068 devc->state.chunks_downloaded = 0;
1069 numchunks = (devc->state.stoppos + 511) / 512;
1070 newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
1072 bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
1073 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1076 /* Find first ts. */
1077 if (devc->state.chunks_downloaded == 0) {
1078 devc->state.lastts = RL16(buf) - 1;
1079 devc->state.lastsample = 0;
1082 /* Decode chunks and send them to sigrok. */
1083 for (i = 0; i < newchunks; ++i) {
1084 int limit_chunk = 0;
1086 /* The last chunk may potentially be only in part. */
1087 if (devc->state.chunks_downloaded == numchunks - 1) {
1088 /* Find the last valid timestamp */
1089 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1092 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1093 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1094 &devc->state.lastts,
1095 &devc->state.lastsample,
1096 devc->state.triggerpos & 0x1ff,
1099 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1100 &devc->state.lastts,
1101 &devc->state.lastsample,
1102 -1, limit_chunk, sdi);
1104 ++devc->state.chunks_downloaded;
1109 static int receive_data(int fd, int revents, void *cb_data)
1111 struct sr_dev_inst *sdi;
1112 struct dev_context *devc;
1113 struct sr_datafeed_packet packet;
1114 uint64_t running_msec;
1125 /* Get the current position. */
1126 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1128 if (devc->state.state == SIGMA_IDLE)
1131 if (devc->state.state == SIGMA_CAPTURE) {
1132 numchunks = (devc->state.stoppos + 511) / 512;
1134 /* Check if the timer has expired, or memory is full. */
1135 gettimeofday(&tv, 0);
1136 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1137 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1139 if (running_msec < devc->limit_msec && numchunks < 32767)
1140 /* Still capturing. */
1143 /* Stop acquisition. */
1144 sigma_set_register(WRITE_MODE, 0x11, devc);
1146 /* Set SDRAM Read Enable. */
1147 sigma_set_register(WRITE_MODE, 0x02, devc);
1149 /* Get the current position. */
1150 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1152 /* Check if trigger has fired. */
1153 modestatus = sigma_get_register(READ_MODE, devc);
1154 if (modestatus & 0x20)
1155 devc->state.triggerchunk = devc->state.triggerpos / 512;
1157 devc->state.triggerchunk = -1;
1159 /* Transfer captured data from device. */
1160 download_capture(sdi);
1163 packet.type = SR_DF_END;
1164 sr_session_send(sdi, &packet);
1166 dev_acquisition_stop(sdi, sdi);
1172 /* Build a LUT entry used by the trigger functions. */
1173 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1177 /* For each quad channel. */
1178 for (i = 0; i < 4; ++i) {
1181 /* For each bit in LUT. */
1182 for (j = 0; j < 16; ++j)
1184 /* For each channel in quad. */
1185 for (k = 0; k < 4; ++k) {
1186 bit = 1 << (i * 4 + k);
1188 /* Set bit in entry */
1190 ((!(value & bit)) !=
1192 entry[i] &= ~(1 << j);
1197 /* Add a logical function to LUT mask. */
1198 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1199 int index, int neg, uint16_t *mask)
1202 int x[2][2], tmp, a, b, aset, bset, rset;
1204 memset(x, 0, 4 * sizeof(int));
1206 /* Trigger detect condition. */
1236 case OP_NOTRISEFALL:
1242 /* Transpose if neg is set. */
1244 for (i = 0; i < 2; ++i) {
1245 for (j = 0; j < 2; ++j) {
1247 x[i][j] = x[1-i][1-j];
1253 /* Update mask with function. */
1254 for (i = 0; i < 16; ++i) {
1255 a = (i >> (2 * index + 0)) & 1;
1256 b = (i >> (2 * index + 1)) & 1;
1258 aset = (*mask >> i) & 1;
1261 if (func == FUNC_AND || func == FUNC_NAND)
1263 else if (func == FUNC_OR || func == FUNC_NOR)
1265 else if (func == FUNC_XOR || func == FUNC_NXOR)
1268 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1279 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1280 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1281 * set at any time, but a full mask and value can be set (0/1).
1283 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1286 uint16_t masks[2] = { 0, 0 };
1288 memset(lut, 0, sizeof(struct triggerlut));
1290 /* Contant for simple triggers. */
1293 /* Value/mask trigger support. */
1294 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1297 /* Rise/fall trigger support. */
1298 for (i = 0, j = 0; i < 16; ++i) {
1299 if (devc->trigger.risingmask & (1 << i) ||
1300 devc->trigger.fallingmask & (1 << i))
1301 masks[j++] = 1 << i;
1304 build_lut_entry(masks[0], masks[0], lut->m0d);
1305 build_lut_entry(masks[1], masks[1], lut->m1d);
1307 /* Add glue logic */
1308 if (masks[0] || masks[1]) {
1309 /* Transition trigger. */
1310 if (masks[0] & devc->trigger.risingmask)
1311 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1312 if (masks[0] & devc->trigger.fallingmask)
1313 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1314 if (masks[1] & devc->trigger.risingmask)
1315 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1316 if (masks[1] & devc->trigger.fallingmask)
1317 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1319 /* Only value/mask trigger. */
1323 /* Triggertype: event. */
1324 lut->params.selres = 3;
1329 static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1331 struct dev_context *devc;
1332 struct clockselect_50 clockselect;
1333 int frac, triggerpin, ret;
1334 uint8_t triggerselect = 0;
1335 struct triggerinout triggerinout_conf;
1336 struct triggerlut lut;
1338 if (sdi->status != SR_ST_ACTIVE)
1339 return SR_ERR_DEV_CLOSED;
1343 if (configure_channels(sdi) != SR_OK) {
1344 sr_err("Failed to configure channels.");
1348 /* If the samplerate has not been set, default to 200 kHz. */
1349 if (devc->cur_firmware == -1) {
1350 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1354 /* Enter trigger programming mode. */
1355 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1357 /* 100 and 200 MHz mode. */
1358 if (devc->cur_samplerate >= SR_MHZ(100)) {
1359 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1361 /* Find which pin to trigger on from mask. */
1362 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1363 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1367 /* Set trigger pin and light LED on trigger. */
1368 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1370 /* Default rising edge. */
1371 if (devc->trigger.fallingmask)
1372 triggerselect |= 1 << 3;
1374 /* All other modes. */
1375 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1376 build_basic_trigger(&lut, devc);
1378 sigma_write_trigger_lut(&lut, devc);
1380 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1383 /* Setup trigger in and out pins to default values. */
1384 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1385 triggerinout_conf.trgout_bytrigger = 1;
1386 triggerinout_conf.trgout_enable = 1;
1388 sigma_write_register(WRITE_TRIGGER_OPTION,
1389 (uint8_t *) &triggerinout_conf,
1390 sizeof(struct triggerinout), devc);
1392 /* Go back to normal mode. */
1393 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1395 /* Set clock select register. */
1396 if (devc->cur_samplerate == SR_MHZ(200))
1397 /* Enable 4 channels. */
1398 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1399 else if (devc->cur_samplerate == SR_MHZ(100))
1400 /* Enable 8 channels. */
1401 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1404 * 50 MHz mode (or fraction thereof). Any fraction down to
1405 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1407 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1409 clockselect.async = 0;
1410 clockselect.fraction = frac;
1411 clockselect.disabled_channels = 0;
1413 sigma_write_register(WRITE_CLOCK_SELECT,
1414 (uint8_t *) &clockselect,
1415 sizeof(clockselect), devc);
1418 /* Setup maximum post trigger time. */
1419 sigma_set_register(WRITE_POST_TRIGGER,
1420 (devc->capture_ratio * 255) / 100, devc);
1422 /* Start acqusition. */
1423 gettimeofday(&devc->start_tv, 0);
1424 sigma_set_register(WRITE_MODE, 0x0d, devc);
1426 devc->cb_data = cb_data;
1428 /* Send header packet to the session bus. */
1429 std_session_send_df_header(cb_data, LOG_PREFIX);
1431 /* Add capture source. */
1432 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1434 devc->state.state = SIGMA_CAPTURE;
1439 static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1441 struct dev_context *devc;
1446 devc->state.state = SIGMA_IDLE;
1448 sr_source_remove(0);
1453 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1454 .name = "asix-sigma",
1455 .longname = "ASIX SIGMA/SIGMA2",
1460 .dev_list = dev_list,
1461 .dev_clear = dev_clear,
1462 .config_get = config_get,
1463 .config_set = config_set,
1464 .config_list = config_list,
1465 .dev_open = dev_open,
1466 .dev_close = dev_close,
1467 .dev_acquisition_start = dev_acquisition_start,
1468 .dev_acquisition_stop = dev_acquisition_stop,