2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
38 #define TRIGGER_TYPES "rf10"
40 static GSList *device_instances = NULL;
42 // XXX These should be per device
43 static struct ftdi_context ftdic;
44 static uint64_t cur_samplerate = 0;
45 static uint32_t limit_msec = 0;
46 static struct timeval start_tv;
47 static int cur_firmware = -1;
48 static int num_probes = 0;
49 static int samples_per_event = 0;
50 static int capture_ratio = 50;
51 static struct sigma_trigger trigger;
53 static uint64_t supported_samplerates[] = {
67 static struct samplerates samplerates = {
71 supported_samplerates,
74 static int capabilities[] = {
84 /* Force the FPGA to reboot. */
85 static uint8_t suicide[] = {
86 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
89 /* Prepare to upload firmware (FPGA specific). */
90 static uint8_t init[] = {
91 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
94 /* Initialize the logic analyzer mode. */
95 static uint8_t logic_mode_start[] = {
96 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
97 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
100 static const char *firmware_files[] = {
101 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
102 "asix-sigma-100.fw", /* 100 MHz */
103 "asix-sigma-200.fw", /* 200 MHz */
104 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
105 "asix-sigma-phasor.fw", /* Frequency counter */
108 static int sigma_read(void *buf, size_t size)
112 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
114 g_warning("ftdi_read_data failed: %s",
115 ftdi_get_error_string(&ftdic));
121 static int sigma_write(void *buf, size_t size)
125 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
127 g_warning("ftdi_write_data failed: %s",
128 ftdi_get_error_string(&ftdic));
129 } else if ((size_t) ret != size) {
130 g_warning("ftdi_write_data did not complete write\n");
136 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
139 uint8_t buf[len + 2];
142 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
143 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
145 for (i = 0; i < len; ++i) {
146 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
147 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
150 return sigma_write(buf, idx);
153 static int sigma_set_register(uint8_t reg, uint8_t value)
155 return sigma_write_register(reg, &value, 1);
158 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
162 buf[0] = REG_ADDR_LOW | (reg & 0xf);
163 buf[1] = REG_ADDR_HIGH | (reg >> 4);
164 buf[2] = REG_READ_ADDR;
166 sigma_write(buf, sizeof(buf));
168 return sigma_read(data, len);
171 static uint8_t sigma_get_register(uint8_t reg)
175 if (1 != sigma_read_register(reg, &value, 1)) {
176 g_warning("Sigma_get_register: 1 byte expected");
183 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
186 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
197 sigma_write(buf, sizeof(buf));
199 sigma_read(result, sizeof(result));
201 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
202 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
204 /* Not really sure why this must be done, but according to spec. */
205 if ((--*stoppos & 0x1ff) == 0x1ff)
208 if ((*--triggerpos & 0x1ff) == 0x1ff)
214 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
220 /* Send the startchunk. Index start with 1. */
221 buf[0] = startchunk >> 8;
222 buf[1] = startchunk & 0xff;
223 sigma_write_register(WRITE_MEMROW, buf, 2);
226 buf[idx++] = REG_DRAM_BLOCK;
227 buf[idx++] = REG_DRAM_WAIT_ACK;
229 for (i = 0; i < numchunks; ++i) {
230 /* Alternate bit to copy from DRAM to cache. */
231 if (i != (numchunks - 1))
232 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
234 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
236 if (i != (numchunks - 1))
237 buf[idx++] = REG_DRAM_WAIT_ACK;
240 sigma_write(buf, idx);
242 return sigma_read(data, numchunks * CHUNK_SIZE);
245 /* Upload trigger look-up tables to Sigma. */
246 static int sigma_write_trigger_lut(struct triggerlut *lut)
252 /* Transpose the table and send to Sigma. */
253 for (i = 0; i < 16; ++i) {
258 if (lut->m2d[0] & bit)
260 if (lut->m2d[1] & bit)
262 if (lut->m2d[2] & bit)
264 if (lut->m2d[3] & bit)
274 if (lut->m0d[0] & bit)
276 if (lut->m0d[1] & bit)
278 if (lut->m0d[2] & bit)
280 if (lut->m0d[3] & bit)
283 if (lut->m1d[0] & bit)
285 if (lut->m1d[1] & bit)
287 if (lut->m1d[2] & bit)
289 if (lut->m1d[3] & bit)
292 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp));
293 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i);
296 /* Send the parameters */
297 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
298 sizeof(lut->params));
303 /* Generate the bitbang stream for programming the FPGA. */
304 static int bin2bitbang(const char *filename,
305 unsigned char **buf, size_t *buf_size)
309 unsigned long offset = 0;
311 uint8_t *compressed_buf, *firmware;
312 uLongf csize, fwsize;
313 const int buffer_size = 65536;
316 uint32_t imm = 0x3f6df2ab;
318 f = fopen(filename, "r");
320 g_warning("fopen(\"%s\", \"r\")", filename);
324 if (-1 == fseek(f, 0, SEEK_END)) {
325 g_warning("fseek on %s failed", filename);
330 file_size = ftell(f);
332 fseek(f, 0, SEEK_SET);
334 compressed_buf = g_malloc(file_size);
335 firmware = g_malloc(buffer_size);
337 if (!compressed_buf || !firmware) {
338 g_warning("Error allocating buffers");
343 while ((c = getc(f)) != EOF) {
344 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
345 compressed_buf[csize++] = c ^ imm;
349 fwsize = buffer_size;
350 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
352 g_free(compressed_buf);
354 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
358 g_free(compressed_buf);
360 *buf_size = fwsize * 2 * 8;
362 *buf = p = (unsigned char *)g_malloc(*buf_size);
365 g_warning("Error allocating buffers");
369 for (i = 0; i < fwsize; ++i) {
370 for (bit = 7; bit >= 0; --bit) {
371 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
372 p[offset++] = v | 0x01;
379 if (offset != *buf_size) {
381 g_warning("Error reading firmware %s "
382 "offset=%ld, file_size=%ld, buf_size=%zd\n",
383 filename, offset, file_size, *buf_size);
391 static int hw_init(char *deviceinfo)
393 struct sigrok_device_instance *sdi;
395 deviceinfo = deviceinfo;
399 /* Look for SIGMAs. */
400 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
401 USB_DESCRIPTION, NULL) < 0)
404 /* Register SIGMA device. */
405 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
406 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
410 device_instances = g_slist_append(device_instances, sdi);
412 /* We will open the device again when we need it. */
413 ftdi_usb_close(&ftdic);
418 static int upload_firmware(int firmware_idx)
424 unsigned char result[32];
425 char firmware_path[128];
427 /* Make sure it's an ASIX SIGMA. */
428 if ((ret = ftdi_usb_open_desc(&ftdic,
429 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
430 g_warning("ftdi_usb_open failed: %s",
431 ftdi_get_error_string(&ftdic));
435 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
436 g_warning("ftdi_set_bitmode failed: %s",
437 ftdi_get_error_string(&ftdic));
441 /* Four times the speed of sigmalogan - Works well. */
442 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
443 g_warning("ftdi_set_baudrate failed: %s",
444 ftdi_get_error_string(&ftdic));
448 /* Force the FPGA to reboot. */
449 sigma_write(suicide, sizeof(suicide));
450 sigma_write(suicide, sizeof(suicide));
451 sigma_write(suicide, sizeof(suicide));
452 sigma_write(suicide, sizeof(suicide));
454 /* Prepare to upload firmware (FPGA specific). */
455 sigma_write(init, sizeof(init));
457 ftdi_usb_purge_buffers(&ftdic);
459 /* Wait until the FPGA asserts INIT_B. */
461 ret = sigma_read(result, 1);
462 if (result[0] & 0x20)
466 /* Prepare firmware. */
467 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
468 firmware_files[firmware_idx]);
470 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
471 g_warning("An error occured while reading the firmware: %s",
476 /* Upload firmare. */
477 sigma_write(buf, buf_size);
481 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
482 g_warning("ftdi_set_bitmode failed: %s",
483 ftdi_get_error_string(&ftdic));
487 ftdi_usb_purge_buffers(&ftdic);
489 /* Discard garbage. */
490 while (1 == sigma_read(&pins, 1))
493 /* Initialize the logic analyzer mode. */
494 sigma_write(logic_mode_start, sizeof(logic_mode_start));
496 /* Expect a 3 byte reply. */
497 ret = sigma_read(result, 3);
499 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
500 g_warning("Configuration failed. Invalid reply received.");
504 cur_firmware = firmware_idx;
509 static int hw_opendev(int device_index)
511 struct sigrok_device_instance *sdi;
514 /* Make sure it's an ASIX SIGMA. */
515 if ((ret = ftdi_usb_open_desc(&ftdic,
516 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
518 g_warning("ftdi_usb_open failed: %s",
519 ftdi_get_error_string(&ftdic));
524 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
527 sdi->status = ST_ACTIVE;
532 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
538 for (i = 0; supported_samplerates[i]; i++) {
539 if (supported_samplerates[i] == samplerate)
542 if (supported_samplerates[i] == 0)
543 return SIGROK_ERR_SAMPLERATE;
545 if (samplerate <= MHZ(50)) {
546 ret = upload_firmware(0);
549 if (samplerate == MHZ(100)) {
550 ret = upload_firmware(1);
553 else if (samplerate == MHZ(200)) {
554 ret = upload_firmware(2);
558 cur_samplerate = samplerate;
559 samples_per_event = 16 / num_probes;
561 g_message("Firmware uploaded");
567 * In 100 and 200 MHz mode, only a single pin rising/falling can be
568 * set as trigger. In other modes, two rising/falling triggers can be set,
569 * in addition to value/mask trigger for any number of probes.
571 * The Sigma supports complex triggers using boolean expressions, but this
572 * has not been implemented yet.
574 static int configure_probes(GSList *probes)
580 memset(&trigger, 0, sizeof(struct sigma_trigger));
582 for (l = probes; l; l = l->next) {
583 probe = (struct probe *)l->data;
585 if (!probe->enabled || !probe->trigger)
588 if (cur_samplerate >= MHZ(100)) {
589 /* Fast trigger support. */
591 g_warning("Asix Sigma only supports a single pin trigger "
592 "in 100 and 200 MHz mode.");
595 if (probe->trigger[0] == 'f')
596 trigger.fast_fall = 1;
597 else if (probe->trigger[0] == 'r')
598 trigger.fast_fall = 0;
600 g_warning("Asix Sigma only supports "
601 "rising/falling trigger in 100 "
602 "and 200 MHz mode.");
606 trigger.fast_pin = probe->index - 1;
610 /* Simple trigger support (event). */
611 if (probe->trigger[0] == '1') {
612 trigger.simplevalue |= 1 << (probe->index - 1);
613 trigger.simplemask |= 1 << (probe->index - 1);
615 else if (probe->trigger[0] == '0') {
616 trigger.simplevalue |= 0 << (probe->index - 1);
617 trigger.simplemask |= 1 << (probe->index - 1);
619 else if (probe->trigger[0] == 'f') {
620 trigger.fallingmask |= 1 << (probe->index - 1);
623 else if (probe->trigger[0] == 'r') {
624 trigger.risingmask |= 1 << (probe->index - 1);
628 if (trigger_set > 2) {
629 g_warning("Asix Sigma only supports 2 rising/"
630 "falling triggers.");
639 static void hw_closedev(int device_index)
641 device_index = device_index;
643 ftdi_usb_close(&ftdic);
646 static void hw_cleanup(void)
650 static void *hw_get_device_info(int device_index, int device_info_id)
652 struct sigrok_device_instance *sdi;
655 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
656 fprintf(stderr, "It's NULL.\n");
660 switch (device_info_id) {
665 info = GINT_TO_POINTER(16);
670 case DI_TRIGGER_TYPES:
671 info = (char *)TRIGGER_TYPES;
673 case DI_CUR_SAMPLERATE:
674 info = &cur_samplerate;
681 static int hw_get_status(int device_index)
683 struct sigrok_device_instance *sdi;
685 sdi = get_sigrok_device_instance(device_instances, device_index);
692 static int *hw_get_capabilities(void)
697 static int hw_set_configuration(int device_index, int capability, void *value)
699 struct sigrok_device_instance *sdi;
702 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
705 if (capability == HWCAP_SAMPLERATE) {
706 ret = set_samplerate(sdi, *(uint64_t*) value);
707 } else if (capability == HWCAP_PROBECONFIG) {
708 ret = configure_probes(value);
709 } else if (capability == HWCAP_LIMIT_MSEC) {
710 limit_msec = strtoull(value, NULL, 10);
712 } else if (capability == HWCAP_CAPTURE_RATIO) {
713 capture_ratio = strtoull(value, NULL, 10);
715 } else if (capability == HWCAP_PROBECONFIG) {
716 ret = configure_probes((GSList *) value);
725 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
726 * Each event is 20ns apart, and can contain multiple samples.
728 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
729 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
730 * For 50 MHz and below, events contain one sample for each channel,
731 * spread 20 ns apart.
733 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
734 uint16_t *lastsample, int triggerpos, void *user_data)
737 uint16_t samples[65536 * samples_per_event];
738 struct datafeed_packet packet;
739 int i, j, k, l, numpad, tosend;
740 size_t n = 0, sent = 0;
741 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
747 /* Check if trigger is in this chunk. */
748 if (triggerpos != -1) {
749 if (cur_samplerate <= MHZ(50))
750 triggerpos -= EVENTS_PER_CLUSTER;
757 /* Find in which cluster the trigger occured. */
758 triggerts = triggerpos / 7;
762 for (i = 0; i < 64; ++i) {
763 ts = *(uint16_t *) &buf[i * 16];
764 tsdiff = ts - *lastts;
767 /* Pad last sample up to current point. */
768 numpad = tsdiff * samples_per_event - clustersize;
770 for (j = 0; j < numpad; ++j)
771 samples[j] = *lastsample;
776 /* Send samples between previous and this timestamp to sigrok. */
779 tosend = MIN(2048, n - sent);
781 packet.type = DF_LOGIC16;
782 packet.length = tosend * sizeof(uint16_t);
783 packet.payload = samples + sent;
784 session_bus(user_data, &packet);
790 event = (uint16_t *) &buf[i * 16 + 2];
793 /* For each event in cluster. */
794 for (j = 0; j < 7; ++j) {
796 /* For each sample in event. */
797 for (k = 0; k < samples_per_event; ++k) {
800 /* For each probe. */
801 for (l = 0; l < num_probes; ++l)
802 cur_sample |= (!!(event[j] & (1 << (l *
803 samples_per_event + k))))
806 samples[n++] = cur_sample;
810 /* Send data up to trigger point (if triggered). */
812 if (i == triggerts) {
814 * Trigger is presumptively not accurate to sample.
815 * However, it always trigger before the actual event,
816 * so it would be possible to forward to correct position
817 * here by manually checking for trigger condition.
820 tosend = (triggerpos % 7) - triggeroff;
823 packet.type = DF_LOGIC16;
824 packet.length = tosend * sizeof(uint16_t);
825 packet.payload = samples;
826 session_bus(user_data, &packet);
831 packet.type = DF_TRIGGER;
834 session_bus(user_data, &packet);
837 /* Send rest of the chunk to sigrok. */
840 packet.type = DF_LOGIC16;
841 packet.length = tosend * sizeof(uint16_t);
842 packet.payload = samples + sent;
843 session_bus(user_data, &packet);
845 *lastsample = samples[n - 1];
851 static int receive_data(int fd, int revents, void *user_data)
853 struct datafeed_packet packet;
854 const int chunks_per_read = 32;
855 unsigned char buf[chunks_per_read * CHUNK_SIZE];
856 int bufsz, numchunks, curchunk, i, newchunks;
857 uint32_t triggerpos, stoppos, running_msec;
860 uint16_t lastsample = 0;
862 int triggerchunk = -1;
867 /* Get the current position. */
868 sigma_read_pos(&stoppos, &triggerpos);
869 numchunks = stoppos / 512;
871 /* Check if the has expired, or memory is full. */
872 gettimeofday(&tv, 0);
873 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
874 (tv.tv_usec - start_tv.tv_usec) / 1000;
876 if (running_msec < limit_msec && numchunks < 32767)
879 /* Stop acqusition. */
880 sigma_set_register(WRITE_MODE, 0x11);
882 /* Set SDRAM Read Enable. */
883 sigma_set_register(WRITE_MODE, 0x02);
885 /* Get the current position. */
886 sigma_read_pos(&stoppos, &triggerpos);
888 /* Check if trigger has fired. */
889 modestatus = sigma_get_register(READ_MODE);
890 if (modestatus & 0x20) {
891 triggerchunk = triggerpos / 512;
894 /* Download sample data. */
895 for (curchunk = 0; curchunk < numchunks;) {
896 newchunks = MIN(chunks_per_read, numchunks - curchunk);
898 g_message("Downloading sample data: %.0f %%",
899 100.0 * curchunk / numchunks);
901 bufsz = sigma_read_dram(curchunk, newchunks, buf);
905 lastts = *(uint16_t *) buf - 1;
907 /* Decode chunks and send them to sigrok. */
908 for (i = 0; i < newchunks; ++i) {
909 if (curchunk + i == triggerchunk)
910 decode_chunk_ts(buf + (i * CHUNK_SIZE),
911 &lastts, &lastsample,
912 triggerpos & 0x1ff, user_data);
914 decode_chunk_ts(buf + (i * CHUNK_SIZE),
915 &lastts, &lastsample,
919 curchunk += newchunks;
923 packet.type = DF_END;
925 session_bus(user_data, &packet);
930 /* Build a LUT entry used by the trigger functions. */
931 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
935 /* For each quad probe. */
936 for (i = 0; i < 4; ++i) {
939 /* For each bit in LUT. */
940 for (j = 0; j < 16; ++j)
942 /* For each probe in quad. */
943 for (k = 0; k < 4; ++k) {
944 bit = 1 << (i * 4 + k);
946 /* Set bit in entry */
950 entry[i] &= ~(1 << j);
955 /* Add a logical function to LUT mask. */
956 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
957 int index, int neg, uint16_t *mask)
960 int x[2][2], tmp, a, b, aset, bset, rset;
962 memset(x, 0, 4 * sizeof(int));
964 /* Trigger detect condition. */
1000 /* Transpose if neg is set. */
1002 for (i = 0; i < 2; ++i)
1003 for (j = 0; j < 2; ++j) {
1005 x[i][j] = x[1-i][1-j];
1010 /* Update mask with function. */
1011 for (i = 0; i < 16; ++i) {
1012 a = (i >> (2 * index + 0)) & 1;
1013 b = (i >> (2 * index + 1)) & 1;
1015 aset = (*mask >> i) & 1;
1018 if (func == FUNC_AND || func == FUNC_NAND)
1020 else if (func == FUNC_OR || func == FUNC_NOR)
1022 else if (func == FUNC_XOR || func == FUNC_NXOR)
1025 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1036 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1037 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1038 * set at any time, but a full mask and value can be set (0/1).
1040 static int build_basic_trigger(struct triggerlut *lut)
1043 uint16_t masks[2] = { 0, 0 };
1045 memset(lut, 0, sizeof(struct triggerlut));
1047 /* Contant for simple triggers. */
1050 /* Value/mask trigger support. */
1051 build_lut_entry(trigger.simplevalue, trigger.simplemask, lut->m2d);
1053 /* Rise/fall trigger support. */
1054 for (i = 0, j = 0; i < 16; ++i) {
1055 if (trigger.risingmask & (1 << i) ||
1056 trigger.fallingmask & (1 << i))
1057 masks[j++] = 1 << i;
1060 build_lut_entry(masks[0], masks[0], lut->m0d);
1061 build_lut_entry(masks[1], masks[1], lut->m1d);
1063 /* Add glue logic */
1064 if (masks[0] || masks[1]) {
1065 /* Transition trigger. */
1066 if (masks[0] & trigger.risingmask)
1067 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1068 if (masks[0] & trigger.fallingmask)
1069 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1070 if (masks[1] & trigger.risingmask)
1071 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1072 if (masks[1] & trigger.fallingmask)
1073 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1075 /* Only value/mask trigger. */
1079 /* Triggertype: event. */
1080 lut->params.selres = 3;
1085 static int hw_start_acquisition(int device_index, gpointer session_device_id)
1087 struct sigrok_device_instance *sdi;
1088 struct datafeed_packet packet;
1089 struct datafeed_header header;
1090 struct clockselect_50 clockselect;
1092 uint8_t triggerselect;
1093 struct triggerinout triggerinout_conf;
1094 struct triggerlut lut;
1096 session_device_id = session_device_id;
1098 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
1101 device_index = device_index;
1103 /* If the samplerate has not been set, default to 50 MHz. */
1104 if (cur_firmware == -1)
1105 set_samplerate(sdi, MHZ(50));
1107 /* Enter trigger programming mode. */
1108 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
1110 /* 100 and 200 MHz mode. */
1111 if (cur_samplerate >= MHZ(100)) {
1112 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81);
1114 triggerselect = (1 << LEDSEL1) | (trigger.fast_fall << 3) |
1115 (trigger.fast_pin & 0x7);
1117 /* All other modes. */
1118 } else if (cur_samplerate <= MHZ(50)) {
1119 build_basic_trigger(&lut);
1121 sigma_write_trigger_lut(&lut);
1123 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1126 /* Setup trigger in and out pins to default values. */
1127 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1128 triggerinout_conf.trgout_bytrigger = 1;
1129 triggerinout_conf.trgout_enable = 1;
1131 sigma_write_register(WRITE_TRIGGER_OPTION,
1132 (uint8_t *) &triggerinout_conf,
1133 sizeof(struct triggerinout));
1135 /* Go back to normal mode. */
1136 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect);
1138 /* Set clock select register. */
1139 if (cur_samplerate == MHZ(200))
1140 /* Enable 4 probes. */
1141 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
1142 else if (cur_samplerate == MHZ(100))
1143 /* Enable 8 probes. */
1144 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
1147 * 50 MHz mode (or fraction thereof). Any fraction down to
1148 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1150 frac = MHZ(50) / cur_samplerate - 1;
1152 clockselect.async = 0;
1153 clockselect.fraction = frac;
1154 clockselect.disabled_probes = 0;
1156 sigma_write_register(WRITE_CLOCK_SELECT,
1157 (uint8_t *) &clockselect,
1158 sizeof(clockselect));
1161 /* Setup maximum post trigger time. */
1162 sigma_set_register(WRITE_POST_TRIGGER, (capture_ratio * 255) / 100);
1164 /* Start acqusition. */
1165 gettimeofday(&start_tv, 0);
1166 sigma_set_register(WRITE_MODE, 0x0d);
1168 /* Send header packet to the session bus. */
1169 packet.type = DF_HEADER;
1170 packet.length = sizeof(struct datafeed_header);
1171 packet.payload = &header;
1172 header.feed_version = 1;
1173 gettimeofday(&header.starttime, NULL);
1174 header.samplerate = cur_samplerate;
1175 header.protocol_id = PROTO_RAW;
1176 header.num_probes = num_probes;
1177 session_bus(session_device_id, &packet);
1179 /* Add capture source. */
1180 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
1185 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
1187 device_index = device_index;
1188 session_device_id = session_device_id;
1190 /* Stop acquisition. */
1191 sigma_set_register(WRITE_MODE, 0x11);
1193 // XXX Set some state to indicate that data should be sent to sigrok
1194 // Now, we just wait for timeout
1197 struct device_plugin asix_sigma_plugin_info = {
1206 hw_get_capabilities,
1207 hw_set_configuration,
1208 hw_start_acquisition,
1209 hw_stop_acquisition,