2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX Sigma Logic Analyzer Driver
30 #include "asix-sigma.h"
32 #define USB_VENDOR 0xa600
33 #define USB_PRODUCT 0xa000
34 #define USB_DESCRIPTION "ASIX SIGMA"
35 #define USB_VENDOR_NAME "ASIX"
36 #define USB_MODEL_NAME "SIGMA"
37 #define USB_MODEL_VERSION ""
39 static GSList *device_instances = NULL;
41 // XXX These should be per device
42 static struct ftdi_context ftdic;
43 static uint64_t cur_samplerate = 0;
44 static uint32_t limit_msec = 0;
45 static struct timeval start_tv;
46 static int cur_firmware = -1;
47 static int num_probes = 0;
48 static int samples_per_event = 0;
50 static uint64_t supported_samplerates[] = {
64 static struct samplerates samplerates = {
68 supported_samplerates,
71 static int capabilities[] = {
75 /* These are really implemented in the driver, not the hardware. */
80 /* Force the FPGA to reboot. */
81 static uint8_t suicide[] = {
82 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
85 /* Prepare to upload firmware (FPGA specific). */
86 static uint8_t init[] = {
87 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
90 /* Initialize the logic analyzer mode. */
91 static uint8_t logic_mode_start[] = {
92 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
93 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
96 static const char *firmware_files[] =
98 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
99 "asix-sigma-100.fw", /* 100 MHz */
100 "asix-sigma-200.fw", /* 200 MHz */
101 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
102 "asix-sigma-phasor.fw", /* Frequency counter */
105 static int sigma_read(void *buf, size_t size)
109 ret = ftdi_read_data(&ftdic, (unsigned char *)buf, size);
111 g_warning("ftdi_read_data failed: %s",
112 ftdi_get_error_string(&ftdic));
118 static int sigma_write(void *buf, size_t size)
122 ret = ftdi_write_data(&ftdic, (unsigned char *)buf, size);
124 g_warning("ftdi_write_data failed: %s",
125 ftdi_get_error_string(&ftdic));
126 } else if ((size_t) ret != size) {
127 g_warning("ftdi_write_data did not complete write\n");
133 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len)
136 uint8_t buf[len + 2];
139 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
140 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
142 for (i = 0; i < len; ++i) {
143 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
144 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
147 return sigma_write(buf, idx);
150 static int sigma_set_register(uint8_t reg, uint8_t value)
152 return sigma_write_register(reg, &value, 1);
155 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len)
159 buf[0] = REG_ADDR_LOW | (reg & 0xf);
160 buf[1] = REG_ADDR_HIGH | (reg >> 4);
161 buf[2] = REG_READ_ADDR;
163 sigma_write(buf, sizeof(buf));
165 return sigma_read(data, len);
168 static uint8_t sigma_get_register(uint8_t reg)
172 if (1 != sigma_read_register(reg, &value, 1)) {
173 g_warning("Sigma_get_register: 1 byte expected");
180 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos)
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
194 sigma_write(buf, sizeof(buf));
196 sigma_read(result, sizeof(result));
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
204 static int sigma_read_dram(uint16_t startchunk, size_t numchunks, uint8_t *data)
210 /* Send the startchunk. Index start with 1. */
211 buf[0] = startchunk >> 8;
212 buf[1] = startchunk & 0xff;
213 sigma_write_register(WRITE_MEMROW, buf, 2);
216 buf[idx++] = REG_DRAM_BLOCK;
217 buf[idx++] = REG_DRAM_WAIT_ACK;
219 for (i = 0; i < numchunks; ++i) {
220 /* Alternate bit to copy from DRAM to cache. */
221 if (i != (numchunks - 1))
222 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
224 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
226 if (i != (numchunks - 1))
227 buf[idx++] = REG_DRAM_WAIT_ACK;
230 sigma_write(buf, idx);
232 return sigma_read(data, numchunks * CHUNK_SIZE);
235 /* Generate the bitbang stream for programming the FPGA. */
236 static int bin2bitbang(const char *filename,
237 unsigned char **buf, size_t *buf_size)
241 unsigned long offset = 0;
243 uint8_t *compressed_buf, *firmware;
244 uLongf csize, fwsize;
245 const int buffer_size = 65536;
248 uint32_t imm = 0x3f6df2ab;
250 f = fopen(filename, "r");
252 g_warning("fopen(\"%s\", \"r\")", filename);
256 if (-1 == fseek(f, 0, SEEK_END)) {
257 g_warning("fseek on %s failed", filename);
262 file_size = ftell(f);
264 fseek(f, 0, SEEK_SET);
266 compressed_buf = g_malloc(file_size);
267 firmware = g_malloc(buffer_size);
269 if (!compressed_buf || !firmware) {
270 g_warning("Error allocating buffers");
275 while ((c = getc(f)) != EOF) {
276 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
277 compressed_buf[csize++] = c ^ imm;
281 fwsize = buffer_size;
282 ret = uncompress(firmware, &fwsize, compressed_buf, csize);
284 g_free(compressed_buf);
286 g_warning("Could not unpack Sigma firmware. (Error %d)\n", ret);
290 g_free(compressed_buf);
292 *buf_size = fwsize * 2 * 8;
294 *buf = p = (unsigned char *)g_malloc(*buf_size);
297 g_warning("Error allocating buffers");
301 for (i = 0; i < fwsize; ++i) {
302 for (bit = 7; bit >= 0; --bit) {
303 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
304 p[offset++] = v | 0x01;
311 if (offset != *buf_size) {
313 g_warning("Error reading firmware %s "
314 "offset=%ld, file_size=%ld, buf_size=%zd\n",
315 filename, offset, file_size, *buf_size);
323 static int hw_init(char *deviceinfo)
325 struct sigrok_device_instance *sdi;
327 deviceinfo = deviceinfo;
331 /* Look for SIGMAs. */
332 if (ftdi_usb_open_desc(&ftdic, USB_VENDOR, USB_PRODUCT,
333 USB_DESCRIPTION, NULL) < 0)
336 /* Register SIGMA device. */
337 sdi = sigrok_device_instance_new(0, ST_INITIALIZING,
338 USB_VENDOR_NAME, USB_MODEL_NAME, USB_MODEL_VERSION);
342 device_instances = g_slist_append(device_instances, sdi);
344 /* We will open the device again when we need it. */
345 ftdi_usb_close(&ftdic);
350 static int upload_firmware(int firmware_idx)
356 unsigned char result[32];
357 char firmware_path[128];
359 /* Make sure it's an ASIX SIGMA. */
360 if ((ret = ftdi_usb_open_desc(&ftdic,
361 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
362 g_warning("ftdi_usb_open failed: %s",
363 ftdi_get_error_string(&ftdic));
367 if ((ret = ftdi_set_bitmode(&ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
368 g_warning("ftdi_set_bitmode failed: %s",
369 ftdi_get_error_string(&ftdic));
373 /* Four times the speed of sigmalogan - Works well. */
374 if ((ret = ftdi_set_baudrate(&ftdic, 750000)) < 0) {
375 g_warning("ftdi_set_baudrate failed: %s",
376 ftdi_get_error_string(&ftdic));
380 /* Force the FPGA to reboot. */
381 sigma_write(suicide, sizeof(suicide));
382 sigma_write(suicide, sizeof(suicide));
383 sigma_write(suicide, sizeof(suicide));
384 sigma_write(suicide, sizeof(suicide));
386 /* Prepare to upload firmware (FPGA specific). */
387 sigma_write(init, sizeof(init));
389 ftdi_usb_purge_buffers(&ftdic);
391 /* Wait until the FPGA asserts INIT_B. */
393 ret = sigma_read(result, 1);
394 if (result[0] & 0x20)
398 /* Prepare firmware. */
399 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
400 firmware_files[firmware_idx]);
402 if (-1 == bin2bitbang(firmware_path, &buf, &buf_size)) {
403 g_warning("An error occured while reading the firmware: %s",
408 /* Upload firmare. */
409 sigma_write(buf, buf_size);
413 if ((ret = ftdi_set_bitmode(&ftdic, 0x00, BITMODE_RESET)) < 0) {
414 g_warning("ftdi_set_bitmode failed: %s",
415 ftdi_get_error_string(&ftdic));
419 ftdi_usb_purge_buffers(&ftdic);
421 /* Discard garbage. */
422 while (1 == sigma_read(&pins, 1))
425 /* Initialize the logic analyzer mode. */
426 sigma_write(logic_mode_start, sizeof(logic_mode_start));
428 /* Expect a 3 byte reply. */
429 ret = sigma_read(result, 3);
431 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
432 g_warning("Configuration failed. Invalid reply received.");
436 cur_firmware = firmware_idx;
441 static int hw_opendev(int device_index)
443 struct sigrok_device_instance *sdi;
446 /* Make sure it's an ASIX SIGMA. */
447 if ((ret = ftdi_usb_open_desc(&ftdic,
448 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
450 g_warning("ftdi_usb_open failed: %s",
451 ftdi_get_error_string(&ftdic));
456 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
459 sdi->status = ST_ACTIVE;
464 static int set_samplerate(struct sigrok_device_instance *sdi, uint64_t samplerate)
470 for (i = 0; supported_samplerates[i]; i++) {
471 if (supported_samplerates[i] == samplerate)
474 if (supported_samplerates[i] == 0)
475 return SIGROK_ERR_SAMPLERATE;
477 if (samplerate <= MHZ(50)) {
478 ret = upload_firmware(0);
481 if (samplerate == MHZ(100)) {
482 ret = upload_firmware(1);
485 else if (samplerate == MHZ(200)) {
486 ret = upload_firmware(2);
490 cur_samplerate = samplerate;
491 samples_per_event = 16 / num_probes;
493 g_message("Firmware uploaded");
498 static void hw_closedev(int device_index)
500 device_index = device_index;
502 ftdi_usb_close(&ftdic);
505 static void hw_cleanup(void)
509 static void *hw_get_device_info(int device_index, int device_info_id)
511 struct sigrok_device_instance *sdi;
514 if (!(sdi = get_sigrok_device_instance(device_instances, device_index))) {
515 fprintf(stderr, "It's NULL.\n");
519 switch (device_info_id) {
524 info = GINT_TO_POINTER(16);
529 case DI_TRIGGER_TYPES:
532 case DI_CUR_SAMPLERATE:
533 info = &cur_samplerate;
540 static int hw_get_status(int device_index)
542 struct sigrok_device_instance *sdi;
544 sdi = get_sigrok_device_instance(device_instances, device_index);
551 static int *hw_get_capabilities(void)
556 static int hw_set_configuration(int device_index, int capability, void *value)
558 struct sigrok_device_instance *sdi;
561 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
564 if (capability == HWCAP_SAMPLERATE) {
565 ret = set_samplerate(sdi, *(uint64_t*) value);
566 } else if (capability == HWCAP_PROBECONFIG) {
568 } else if (capability == HWCAP_LIMIT_MSEC) {
569 limit_msec = strtoull(value, NULL, 10);
579 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
580 * Each event is 20ns apart, and can contain multiple samples.
582 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
583 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
584 * For 50 MHz and below, events contain one sample for each channel,
585 * spread 20 ns apart.
587 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
588 uint16_t *lastsample, void *user_data)
591 uint16_t samples[65536 * samples_per_event];
592 struct datafeed_packet packet;
593 int i, j, k, l, numpad, tosend;
594 size_t n = 0, sent = 0;
595 int clustersize = EVENTS_PER_CLUSTER * samples_per_event;
600 for (i = 0; i < 64; ++i) {
601 ts = *(uint16_t *) &buf[i * 16];
602 tsdiff = ts - *lastts;
605 /* Pad last sample up to current point. */
606 numpad = tsdiff * samples_per_event - clustersize;
608 for (j = 0; j < numpad; ++j)
609 samples[j] = *lastsample;
614 event = (uint16_t *) &buf[i * 16 + 2];
618 /* For each event in cluster. */
619 for (j = 0; j < 7; ++j) {
621 /* For each sample in event. */
622 for (k = 0; k < samples_per_event; ++k) {
625 /* For each probe. */
626 for (l = 0; l < num_probes; ++l)
627 cur_sample |= (!!(event[j] & (1 << (l *
628 samples_per_event + k))))
631 samples[n++] = cur_sample;
635 *lastsample = samples[n - 1];
637 /* Send to sigrok. */
640 tosend = MIN(2048, n - sent);
642 packet.type = DF_LOGIC16;
643 packet.length = tosend * sizeof(uint16_t);
644 packet.payload = samples + sent;
645 session_bus(user_data, &packet);
654 static int receive_data(int fd, int revents, void *user_data)
656 struct datafeed_packet packet;
657 const int chunks_per_read = 32;
658 unsigned char buf[chunks_per_read * CHUNK_SIZE];
659 int bufsz, numchunks, curchunk, i, newchunks;
660 uint32_t triggerpos, stoppos, running_msec;
663 uint16_t lastsample = 0;
668 /* Get the current position. */
669 sigma_read_pos(&stoppos, &triggerpos);
670 numchunks = stoppos / 512;
672 /* Check if the has expired, or memory is full. */
673 gettimeofday(&tv, 0);
674 running_msec = (tv.tv_sec - start_tv.tv_sec) * 1000 +
675 (tv.tv_usec - start_tv.tv_usec) / 1000;
677 if (running_msec < limit_msec && numchunks < 32767)
680 /* Stop acqusition. */
681 sigma_set_register(WRITE_MODE, 0x11);
683 /* Set SDRAM Read Enable. */
684 sigma_set_register(WRITE_MODE, 0x02);
686 /* Get the current position. */
687 sigma_read_pos(&stoppos, &triggerpos);
689 /* Read mode status. We will care for this later. */
690 sigma_get_register(READ_MODE);
692 /* Download sample data. */
693 for (curchunk = 0; curchunk < numchunks;) {
694 newchunks = MIN(chunks_per_read, numchunks - curchunk);
696 g_message("Downloading sample data: %.0f %%",
697 100.0 * curchunk / numchunks);
699 bufsz = sigma_read_dram(curchunk, newchunks, buf);
703 lastts = *(uint16_t *) buf - 1;
705 /* Decode chunks and send them to sigrok. */
706 for (i = 0; i < newchunks; ++i) {
707 decode_chunk_ts(buf + (i * CHUNK_SIZE),
708 &lastts, &lastsample, user_data);
711 curchunk += newchunks;
715 packet.type = DF_END;
717 session_bus(user_data, &packet);
722 static int hw_start_acquisition(int device_index, gpointer session_device_id)
724 struct sigrok_device_instance *sdi;
725 struct datafeed_packet packet;
726 struct datafeed_header header;
727 uint8_t trigger_option[2] = { 0x38, 0x00 };
728 struct clockselect_50 clockselect;
731 session_device_id = session_device_id;
733 if (!(sdi = get_sigrok_device_instance(device_instances, device_index)))
736 device_index = device_index;
738 /* If the samplerate has not been set, default to 50 MHz. */
739 if (cur_firmware == -1)
740 set_samplerate(sdi, MHZ(50));
742 /* Setup trigger (by trigger-in). */
743 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20);
745 /* More trigger setup. */
746 sigma_write_register(WRITE_TRIGGER_OPTION,
747 trigger_option, sizeof(trigger_option));
749 /* Trigger normal (falling edge). */
750 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x08);
752 /* Set clock select register. */
753 if (cur_samplerate == MHZ(200))
754 /* Enable 4 probes. */
755 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0);
756 else if (cur_samplerate == MHZ(100))
757 /* Enable 8 probes. */
758 sigma_set_register(WRITE_CLOCK_SELECT, 0x00);
761 * 50 MHz mode (or fraction thereof). Any fraction down to
762 * 50 MHz / 256 can be used, but is not suppoted by sigrok API.
764 frac = MHZ(50) / cur_samplerate - 1;
766 clockselect.async = 0;
767 clockselect.fraction = frac;
768 clockselect.disabled_probes = 0;
770 sigma_write_register(WRITE_CLOCK_SELECT,
771 (uint8_t *) &clockselect,
772 sizeof(clockselect));
775 /* Setup maximum post trigger time. */
776 sigma_set_register(WRITE_POST_TRIGGER, 0xff);
778 /* Start acqusition (software trigger start). */
779 gettimeofday(&start_tv, 0);
780 sigma_set_register(WRITE_MODE, 0x0d);
782 /* Add capture source. */
783 source_add(0, G_IO_IN, 10, receive_data, session_device_id);
785 receive_data(0, 1, session_device_id);
787 /* Send header packet to the session bus. */
788 packet.type = DF_HEADER;
789 packet.length = sizeof(struct datafeed_header);
790 packet.payload = &header;
791 header.feed_version = 1;
792 gettimeofday(&header.starttime, NULL);
793 header.samplerate = cur_samplerate;
794 header.protocol_id = PROTO_RAW;
795 header.num_probes = num_probes;
796 session_bus(session_device_id, &packet);
801 static void hw_stop_acquisition(int device_index, gpointer session_device_id)
803 device_index = device_index;
804 session_device_id = session_device_id;
806 /* Stop acquisition. */
807 sigma_set_register(WRITE_MODE, 0x11);
809 // XXX Set some state to indicate that data should be sent to sigrok
810 // Now, we just wait for timeout
813 struct device_plugin asix_sigma_plugin_info = {
823 hw_set_configuration,
824 hw_start_acquisition,