2 * This file is part of the sigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPES "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *adi = &asix_sigma_driver_info;
46 static const uint64_t supported_samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
85 static const struct sr_samplerates samplerates = {
89 supported_samplerates,
92 static const int hwcaps[] = {
93 SR_HWCAP_LOGIC_ANALYZER,
95 SR_HWCAP_CAPTURE_RATIO,
102 /* Force the FPGA to reboot. */
103 static uint8_t suicide[] = {
104 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
107 /* Prepare to upload firmware (FPGA specific). */
108 static uint8_t init[] = {
109 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
112 /* Initialize the logic analyzer mode. */
113 static uint8_t logic_mode_start[] = {
114 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
115 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
118 static const char *firmware_files[] = {
119 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
120 "asix-sigma-100.fw", /* 100 MHz */
121 "asix-sigma-200.fw", /* 200 MHz */
122 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
123 "asix-sigma-phasor.fw", /* Frequency counter */
126 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
129 static int sigma_read(void *buf, size_t size, struct context *ctx)
133 ret = ftdi_read_data(&ctx->ftdic, (unsigned char *)buf, size);
135 sr_err("sigma: ftdi_read_data failed: %s",
136 ftdi_get_error_string(&ctx->ftdic));
142 static int sigma_write(void *buf, size_t size, struct context *ctx)
146 ret = ftdi_write_data(&ctx->ftdic, (unsigned char *)buf, size);
148 sr_err("sigma: ftdi_write_data failed: %s",
149 ftdi_get_error_string(&ctx->ftdic));
150 } else if ((size_t) ret != size) {
151 sr_err("sigma: ftdi_write_data did not complete write.");
157 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
161 uint8_t buf[len + 2];
164 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
165 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
167 for (i = 0; i < len; ++i) {
168 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
169 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
172 return sigma_write(buf, idx, ctx);
175 static int sigma_set_register(uint8_t reg, uint8_t value, struct context *ctx)
177 return sigma_write_register(reg, &value, 1, ctx);
180 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
185 buf[0] = REG_ADDR_LOW | (reg & 0xf);
186 buf[1] = REG_ADDR_HIGH | (reg >> 4);
187 buf[2] = REG_READ_ADDR;
189 sigma_write(buf, sizeof(buf), ctx);
191 return sigma_read(data, len, ctx);
194 static uint8_t sigma_get_register(uint8_t reg, struct context *ctx)
198 if (1 != sigma_read_register(reg, &value, 1, ctx)) {
199 sr_err("sigma: sigma_get_register: 1 byte expected");
206 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
210 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
212 REG_READ_ADDR | NEXT_REG,
213 REG_READ_ADDR | NEXT_REG,
214 REG_READ_ADDR | NEXT_REG,
215 REG_READ_ADDR | NEXT_REG,
216 REG_READ_ADDR | NEXT_REG,
217 REG_READ_ADDR | NEXT_REG,
221 sigma_write(buf, sizeof(buf), ctx);
223 sigma_read(result, sizeof(result), ctx);
225 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
226 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
228 /* Not really sure why this must be done, but according to spec. */
229 if ((--*stoppos & 0x1ff) == 0x1ff)
232 if ((*--triggerpos & 0x1ff) == 0x1ff)
238 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
239 uint8_t *data, struct context *ctx)
245 /* Send the startchunk. Index start with 1. */
246 buf[0] = startchunk >> 8;
247 buf[1] = startchunk & 0xff;
248 sigma_write_register(WRITE_MEMROW, buf, 2, ctx);
251 buf[idx++] = REG_DRAM_BLOCK;
252 buf[idx++] = REG_DRAM_WAIT_ACK;
254 for (i = 0; i < numchunks; ++i) {
255 /* Alternate bit to copy from DRAM to cache. */
256 if (i != (numchunks - 1))
257 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
259 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
261 if (i != (numchunks - 1))
262 buf[idx++] = REG_DRAM_WAIT_ACK;
265 sigma_write(buf, idx, ctx);
267 return sigma_read(data, numchunks * CHUNK_SIZE, ctx);
270 /* Upload trigger look-up tables to Sigma. */
271 static int sigma_write_trigger_lut(struct triggerlut *lut, struct context *ctx)
277 /* Transpose the table and send to Sigma. */
278 for (i = 0; i < 16; ++i) {
283 if (lut->m2d[0] & bit)
285 if (lut->m2d[1] & bit)
287 if (lut->m2d[2] & bit)
289 if (lut->m2d[3] & bit)
299 if (lut->m0d[0] & bit)
301 if (lut->m0d[1] & bit)
303 if (lut->m0d[2] & bit)
305 if (lut->m0d[3] & bit)
308 if (lut->m1d[0] & bit)
310 if (lut->m1d[1] & bit)
312 if (lut->m1d[2] & bit)
314 if (lut->m1d[3] & bit)
317 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
319 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, ctx);
322 /* Send the parameters */
323 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
324 sizeof(lut->params), ctx);
329 /* Generate the bitbang stream for programming the FPGA. */
330 static int bin2bitbang(const char *filename,
331 unsigned char **buf, size_t *buf_size)
334 unsigned long file_size;
335 unsigned long offset = 0;
338 unsigned long fwsize = 0;
339 const int buffer_size = 65536;
342 uint32_t imm = 0x3f6df2ab;
344 f = g_fopen(filename, "rb");
346 sr_err("sigma: g_fopen(\"%s\", \"rb\")", filename);
350 if (-1 == fseek(f, 0, SEEK_END)) {
351 sr_err("sigma: fseek on %s failed", filename);
356 file_size = ftell(f);
358 fseek(f, 0, SEEK_SET);
360 if (!(firmware = g_try_malloc(buffer_size))) {
361 sr_err("sigma: %s: firmware malloc failed", __func__);
363 return SR_ERR_MALLOC;
366 while ((c = getc(f)) != EOF) {
367 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
368 firmware[fwsize++] = c ^ imm;
372 if(fwsize != file_size) {
373 sr_err("sigma: %s: Error reading firmware", filename);
379 *buf_size = fwsize * 2 * 8;
381 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
383 sr_err("sigma: %s: buf/p malloc failed", __func__);
385 return SR_ERR_MALLOC;
388 for (i = 0; i < fwsize; ++i) {
389 for (bit = 7; bit >= 0; --bit) {
390 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
391 p[offset++] = v | 0x01;
398 if (offset != *buf_size) {
400 sr_err("sigma: Error reading firmware %s "
401 "offset=%ld, file_size=%ld, buf_size=%zd.",
402 filename, offset, file_size, *buf_size);
410 static void clear_instances(void)
413 struct sr_dev_inst *sdi;
416 /* Properly close all devices. */
417 for (l = adi->instances; l; l = l->next) {
418 if (!(sdi = l->data)) {
419 /* Log error, but continue cleaning up the rest. */
420 sr_err("sigma: %s: sdi was NULL, continuing", __func__);
425 ftdi_free(&ctx->ftdic);
428 sr_dev_inst_free(sdi);
430 g_slist_free(adi->instances);
431 adi->instances = NULL;
435 static int hw_init(void)
443 static GSList *hw_scan(GSList *options)
445 struct sr_dev_inst *sdi;
448 struct ftdi_device_list *devlist;
457 if (!(ctx = g_try_malloc(sizeof(struct context)))) {
458 sr_err("sigma: %s: ctx malloc failed", __func__);
462 ftdi_init(&ctx->ftdic);
464 /* Look for SIGMAs. */
466 if ((ret = ftdi_usb_find_all(&ctx->ftdic, &devlist,
467 USB_VENDOR, USB_PRODUCT)) <= 0) {
469 sr_err("ftdi_usb_find_all(): %d", ret);
473 /* Make sure it's a version 1 or 2 SIGMA. */
474 ftdi_usb_get_strings(&ctx->ftdic, devlist->dev, NULL, 0, NULL, 0,
475 serial_txt, sizeof(serial_txt));
476 sscanf(serial_txt, "%x", &serial);
478 if (serial < 0xa6010000 || serial > 0xa602ffff) {
479 sr_err("sigma: Only SIGMA and SIGMA2 are supported "
480 "in this version of sigrok.");
484 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
486 ctx->cur_samplerate = 0;
489 ctx->cur_firmware = -1;
491 ctx->samples_per_event = 0;
492 ctx->capture_ratio = 50;
493 ctx->use_triggers = 0;
495 /* Register SIGMA device. */
496 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
497 USB_MODEL_NAME, USB_MODEL_VERSION))) {
498 sr_err("sigma: %s: sdi was NULL", __func__);
502 devices = g_slist_append(devices, sdi);
503 adi->instances = g_slist_append(adi->instances, sdi);
506 /* We will open the device again when we need it. */
507 ftdi_list_free(&devlist);
512 ftdi_deinit(&ctx->ftdic);
517 static int upload_firmware(int firmware_idx, struct context *ctx)
523 unsigned char result[32];
524 char firmware_path[128];
526 /* Make sure it's an ASIX SIGMA. */
527 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
528 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
529 sr_err("sigma: ftdi_usb_open failed: %s",
530 ftdi_get_error_string(&ctx->ftdic));
534 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
535 sr_err("sigma: ftdi_set_bitmode failed: %s",
536 ftdi_get_error_string(&ctx->ftdic));
540 /* Four times the speed of sigmalogan - Works well. */
541 if ((ret = ftdi_set_baudrate(&ctx->ftdic, 750000)) < 0) {
542 sr_err("sigma: ftdi_set_baudrate failed: %s",
543 ftdi_get_error_string(&ctx->ftdic));
547 /* Force the FPGA to reboot. */
548 sigma_write(suicide, sizeof(suicide), ctx);
549 sigma_write(suicide, sizeof(suicide), ctx);
550 sigma_write(suicide, sizeof(suicide), ctx);
551 sigma_write(suicide, sizeof(suicide), ctx);
553 /* Prepare to upload firmware (FPGA specific). */
554 sigma_write(init, sizeof(init), ctx);
556 ftdi_usb_purge_buffers(&ctx->ftdic);
558 /* Wait until the FPGA asserts INIT_B. */
560 ret = sigma_read(result, 1, ctx);
561 if (result[0] & 0x20)
565 /* Prepare firmware. */
566 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
567 firmware_files[firmware_idx]);
569 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
570 sr_err("sigma: An error occured while reading the firmware: %s",
575 /* Upload firmare. */
576 sr_info("sigma: Uploading firmware %s", firmware_files[firmware_idx]);
577 sigma_write(buf, buf_size, ctx);
581 if ((ret = ftdi_set_bitmode(&ctx->ftdic, 0x00, BITMODE_RESET)) < 0) {
582 sr_err("sigma: ftdi_set_bitmode failed: %s",
583 ftdi_get_error_string(&ctx->ftdic));
587 ftdi_usb_purge_buffers(&ctx->ftdic);
589 /* Discard garbage. */
590 while (1 == sigma_read(&pins, 1, ctx))
593 /* Initialize the logic analyzer mode. */
594 sigma_write(logic_mode_start, sizeof(logic_mode_start), ctx);
596 /* Expect a 3 byte reply. */
597 ret = sigma_read(result, 3, ctx);
599 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
600 sr_err("sigma: Configuration failed. Invalid reply received.");
604 ctx->cur_firmware = firmware_idx;
606 sr_info("sigma: Firmware uploaded");
611 static int hw_dev_open(struct sr_dev_inst *sdi)
618 /* Make sure it's an ASIX SIGMA. */
619 if ((ret = ftdi_usb_open_desc(&ctx->ftdic,
620 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
622 sr_err("sigma: ftdi_usb_open failed: %s",
623 ftdi_get_error_string(&ctx->ftdic));
628 sdi->status = SR_ST_ACTIVE;
633 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
636 struct context *ctx = sdi->priv;
638 for (i = 0; supported_samplerates[i]; i++) {
639 if (supported_samplerates[i] == samplerate)
642 if (supported_samplerates[i] == 0)
643 return SR_ERR_SAMPLERATE;
645 if (samplerate <= SR_MHZ(50)) {
646 ret = upload_firmware(0, ctx);
647 ctx->num_probes = 16;
649 if (samplerate == SR_MHZ(100)) {
650 ret = upload_firmware(1, ctx);
653 else if (samplerate == SR_MHZ(200)) {
654 ret = upload_firmware(2, ctx);
658 ctx->cur_samplerate = samplerate;
659 ctx->period_ps = 1000000000000 / samplerate;
660 ctx->samples_per_event = 16 / ctx->num_probes;
661 ctx->state.state = SIGMA_IDLE;
667 * In 100 and 200 MHz mode, only a single pin rising/falling can be
668 * set as trigger. In other modes, two rising/falling triggers can be set,
669 * in addition to value/mask trigger for any number of probes.
671 * The Sigma supports complex triggers using boolean expressions, but this
672 * has not been implemented yet.
674 static int configure_probes(const struct sr_dev_inst *sdi, const GSList *probes)
676 struct context *ctx = sdi->priv;
677 const struct sr_probe *probe;
682 memset(&ctx->trigger, 0, sizeof(struct sigma_trigger));
684 for (l = probes; l; l = l->next) {
685 probe = (struct sr_probe *)l->data;
686 probebit = 1 << (probe->index);
688 if (!probe->enabled || !probe->trigger)
691 if (ctx->cur_samplerate >= SR_MHZ(100)) {
692 /* Fast trigger support. */
694 sr_err("sigma: ASIX SIGMA only supports a single "
695 "pin trigger in 100 and 200MHz mode.");
698 if (probe->trigger[0] == 'f')
699 ctx->trigger.fallingmask |= probebit;
700 else if (probe->trigger[0] == 'r')
701 ctx->trigger.risingmask |= probebit;
703 sr_err("sigma: ASIX SIGMA only supports "
704 "rising/falling trigger in 100 "
711 /* Simple trigger support (event). */
712 if (probe->trigger[0] == '1') {
713 ctx->trigger.simplevalue |= probebit;
714 ctx->trigger.simplemask |= probebit;
716 else if (probe->trigger[0] == '0') {
717 ctx->trigger.simplevalue &= ~probebit;
718 ctx->trigger.simplemask |= probebit;
720 else if (probe->trigger[0] == 'f') {
721 ctx->trigger.fallingmask |= probebit;
724 else if (probe->trigger[0] == 'r') {
725 ctx->trigger.risingmask |= probebit;
730 * Actually, Sigma supports 2 rising/falling triggers,
731 * but they are ORed and the current trigger syntax
732 * does not permit ORed triggers.
734 if (trigger_set > 1) {
735 sr_err("sigma: ASIX SIGMA only supports 1 "
736 "rising/falling triggers.");
742 ctx->use_triggers = 1;
748 static int hw_dev_close(struct sr_dev_inst *sdi)
752 if (!(ctx = sdi->priv)) {
753 sr_err("sigma: %s: sdi->priv was NULL", __func__);
758 if (sdi->status == SR_ST_ACTIVE)
759 ftdi_usb_close(&ctx->ftdic);
761 sdi->status = SR_ST_INACTIVE;
766 static int hw_cleanup(void)
774 static int hw_info_get(int info_id, const void **data,
775 const struct sr_dev_inst *sdi)
786 case SR_DI_NUM_PROBES:
787 *data = GINT_TO_POINTER(NUM_PROBES);
789 case SR_DI_PROBE_NAMES:
792 case SR_DI_SAMPLERATES:
793 *data = &samplerates;
795 case SR_DI_TRIGGER_TYPES:
796 *data = (char *)TRIGGER_TYPES;
798 case SR_DI_CUR_SAMPLERATE:
801 *data = &ctx->cur_samplerate;
812 static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
820 if (hwcap == SR_HWCAP_SAMPLERATE) {
821 ret = set_samplerate(sdi, *(const uint64_t *)value);
822 } else if (hwcap == SR_HWCAP_PROBECONFIG) {
823 ret = configure_probes(sdi, value);
824 } else if (hwcap == SR_HWCAP_LIMIT_MSEC) {
825 ctx->limit_msec = *(const uint64_t *)value;
826 if (ctx->limit_msec > 0)
830 } else if (hwcap == SR_HWCAP_CAPTURE_RATIO) {
831 ctx->capture_ratio = *(const uint64_t *)value;
832 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100)
843 /* Software trigger to determine exact trigger position. */
844 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
845 struct sigma_trigger *t)
849 for (i = 0; i < 8; ++i) {
851 last_sample = samples[i-1];
853 /* Simple triggers. */
854 if ((samples[i] & t->simplemask) != t->simplevalue)
858 if ((last_sample & t->risingmask) != 0 || (samples[i] &
859 t->risingmask) != t->risingmask)
863 if ((last_sample & t->fallingmask) != t->fallingmask ||
864 (samples[i] & t->fallingmask) != 0)
870 /* If we did not match, return original trigger pos. */
875 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
876 * Each event is 20ns apart, and can contain multiple samples.
878 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
879 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
880 * For 50 MHz and below, events contain one sample for each channel,
881 * spread 20 ns apart.
883 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
884 uint16_t *lastsample, int triggerpos,
885 uint16_t limit_chunk, void *cb_data)
887 struct sr_dev_inst *sdi = cb_data;
888 struct context *ctx = sdi->priv;
890 uint16_t samples[65536 * ctx->samples_per_event];
891 struct sr_datafeed_packet packet;
892 struct sr_datafeed_logic logic;
893 int i, j, k, l, numpad, tosend;
894 size_t n = 0, sent = 0;
895 int clustersize = EVENTS_PER_CLUSTER * ctx->samples_per_event;
900 /* Check if trigger is in this chunk. */
901 if (triggerpos != -1) {
902 if (ctx->cur_samplerate <= SR_MHZ(50))
903 triggerpos -= EVENTS_PER_CLUSTER - 1;
908 /* Find in which cluster the trigger occured. */
909 triggerts = triggerpos / 7;
913 for (i = 0; i < 64; ++i) {
914 ts = *(uint16_t *) &buf[i * 16];
915 tsdiff = ts - *lastts;
918 /* Decode partial chunk. */
919 if (limit_chunk && ts > limit_chunk)
922 /* Pad last sample up to current point. */
923 numpad = tsdiff * ctx->samples_per_event - clustersize;
925 for (j = 0; j < numpad; ++j)
926 samples[j] = *lastsample;
931 /* Send samples between previous and this timestamp to sigrok. */
934 tosend = MIN(2048, n - sent);
936 packet.type = SR_DF_LOGIC;
937 packet.payload = &logic;
938 logic.length = tosend * sizeof(uint16_t);
940 logic.data = samples + sent;
941 sr_session_send(ctx->session_dev_id, &packet);
947 event = (uint16_t *) &buf[i * 16 + 2];
950 /* For each event in cluster. */
951 for (j = 0; j < 7; ++j) {
953 /* For each sample in event. */
954 for (k = 0; k < ctx->samples_per_event; ++k) {
957 /* For each probe. */
958 for (l = 0; l < ctx->num_probes; ++l)
959 cur_sample |= (!!(event[j] & (1 << (l *
960 ctx->samples_per_event + k)))) << l;
962 samples[n++] = cur_sample;
966 /* Send data up to trigger point (if triggered). */
968 if (i == triggerts) {
970 * Trigger is not always accurate to sample because of
971 * pipeline delay. However, it always triggers before
972 * the actual event. We therefore look at the next
973 * samples to pinpoint the exact position of the trigger.
975 tosend = get_trigger_offset(samples, *lastsample,
979 packet.type = SR_DF_LOGIC;
980 packet.payload = &logic;
981 logic.length = tosend * sizeof(uint16_t);
983 logic.data = samples;
984 sr_session_send(ctx->session_dev_id, &packet);
989 /* Only send trigger if explicitly enabled. */
990 if (ctx->use_triggers) {
991 packet.type = SR_DF_TRIGGER;
992 sr_session_send(ctx->session_dev_id, &packet);
996 /* Send rest of the chunk to sigrok. */
1000 packet.type = SR_DF_LOGIC;
1001 packet.payload = &logic;
1002 logic.length = tosend * sizeof(uint16_t);
1004 logic.data = samples + sent;
1005 sr_session_send(ctx->session_dev_id, &packet);
1008 *lastsample = samples[n - 1];
1014 static int receive_data(int fd, int revents, void *cb_data)
1016 struct sr_dev_inst *sdi = cb_data;
1017 struct context *ctx = sdi->priv;
1018 struct sr_datafeed_packet packet;
1019 const int chunks_per_read = 32;
1020 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1021 int bufsz, numchunks, i, newchunks;
1022 uint64_t running_msec;
1025 /* Avoid compiler warnings. */
1029 /* Get the current position. */
1030 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1032 numchunks = (ctx->state.stoppos + 511) / 512;
1034 if (ctx->state.state == SIGMA_IDLE)
1037 if (ctx->state.state == SIGMA_CAPTURE) {
1038 /* Check if the timer has expired, or memory is full. */
1039 gettimeofday(&tv, 0);
1040 running_msec = (tv.tv_sec - ctx->start_tv.tv_sec) * 1000 +
1041 (tv.tv_usec - ctx->start_tv.tv_usec) / 1000;
1043 if (running_msec < ctx->limit_msec && numchunks < 32767)
1044 return TRUE; /* While capturing... */
1046 hw_dev_acquisition_stop(sdi, sdi);
1048 } else if (ctx->state.state == SIGMA_DOWNLOAD) {
1049 if (ctx->state.chunks_downloaded >= numchunks) {
1050 /* End of samples. */
1051 packet.type = SR_DF_END;
1052 sr_session_send(ctx->session_dev_id, &packet);
1054 ctx->state.state = SIGMA_IDLE;
1059 newchunks = MIN(chunks_per_read,
1060 numchunks - ctx->state.chunks_downloaded);
1062 sr_info("sigma: Downloading sample data: %.0f %%",
1063 100.0 * ctx->state.chunks_downloaded / numchunks);
1065 bufsz = sigma_read_dram(ctx->state.chunks_downloaded,
1066 newchunks, buf, ctx);
1067 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1070 /* Find first ts. */
1071 if (ctx->state.chunks_downloaded == 0) {
1072 ctx->state.lastts = *(uint16_t *) buf - 1;
1073 ctx->state.lastsample = 0;
1076 /* Decode chunks and send them to sigrok. */
1077 for (i = 0; i < newchunks; ++i) {
1078 int limit_chunk = 0;
1080 /* The last chunk may potentially be only in part. */
1081 if (ctx->state.chunks_downloaded == numchunks - 1) {
1082 /* Find the last valid timestamp */
1083 limit_chunk = ctx->state.stoppos % 512 + ctx->state.lastts;
1086 if (ctx->state.chunks_downloaded + i == ctx->state.triggerchunk)
1087 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1089 &ctx->state.lastsample,
1090 ctx->state.triggerpos & 0x1ff,
1093 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1095 &ctx->state.lastsample,
1096 -1, limit_chunk, sdi);
1098 ++ctx->state.chunks_downloaded;
1105 /* Build a LUT entry used by the trigger functions. */
1106 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1110 /* For each quad probe. */
1111 for (i = 0; i < 4; ++i) {
1114 /* For each bit in LUT. */
1115 for (j = 0; j < 16; ++j)
1117 /* For each probe in quad. */
1118 for (k = 0; k < 4; ++k) {
1119 bit = 1 << (i * 4 + k);
1121 /* Set bit in entry */
1123 ((!(value & bit)) !=
1125 entry[i] &= ~(1 << j);
1130 /* Add a logical function to LUT mask. */
1131 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1132 int index, int neg, uint16_t *mask)
1135 int x[2][2], tmp, a, b, aset, bset, rset;
1137 memset(x, 0, 4 * sizeof(int));
1139 /* Trigger detect condition. */
1169 case OP_NOTRISEFALL:
1175 /* Transpose if neg is set. */
1177 for (i = 0; i < 2; ++i) {
1178 for (j = 0; j < 2; ++j) {
1180 x[i][j] = x[1-i][1-j];
1186 /* Update mask with function. */
1187 for (i = 0; i < 16; ++i) {
1188 a = (i >> (2 * index + 0)) & 1;
1189 b = (i >> (2 * index + 1)) & 1;
1191 aset = (*mask >> i) & 1;
1194 if (func == FUNC_AND || func == FUNC_NAND)
1196 else if (func == FUNC_OR || func == FUNC_NOR)
1198 else if (func == FUNC_XOR || func == FUNC_NXOR)
1201 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1212 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1213 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1214 * set at any time, but a full mask and value can be set (0/1).
1216 static int build_basic_trigger(struct triggerlut *lut, struct context *ctx)
1219 uint16_t masks[2] = { 0, 0 };
1221 memset(lut, 0, sizeof(struct triggerlut));
1223 /* Contant for simple triggers. */
1226 /* Value/mask trigger support. */
1227 build_lut_entry(ctx->trigger.simplevalue, ctx->trigger.simplemask,
1230 /* Rise/fall trigger support. */
1231 for (i = 0, j = 0; i < 16; ++i) {
1232 if (ctx->trigger.risingmask & (1 << i) ||
1233 ctx->trigger.fallingmask & (1 << i))
1234 masks[j++] = 1 << i;
1237 build_lut_entry(masks[0], masks[0], lut->m0d);
1238 build_lut_entry(masks[1], masks[1], lut->m1d);
1240 /* Add glue logic */
1241 if (masks[0] || masks[1]) {
1242 /* Transition trigger. */
1243 if (masks[0] & ctx->trigger.risingmask)
1244 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1245 if (masks[0] & ctx->trigger.fallingmask)
1246 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1247 if (masks[1] & ctx->trigger.risingmask)
1248 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1249 if (masks[1] & ctx->trigger.fallingmask)
1250 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1252 /* Only value/mask trigger. */
1256 /* Triggertype: event. */
1257 lut->params.selres = 3;
1262 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1265 struct context *ctx;
1266 struct sr_datafeed_packet *packet;
1267 struct sr_datafeed_header *header;
1268 struct sr_datafeed_meta_logic meta;
1269 struct clockselect_50 clockselect;
1270 int frac, triggerpin, ret;
1271 uint8_t triggerselect;
1272 struct triggerinout triggerinout_conf;
1273 struct triggerlut lut;
1277 /* If the samplerate has not been set, default to 200 kHz. */
1278 if (ctx->cur_firmware == -1) {
1279 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1283 /* Enter trigger programming mode. */
1284 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, ctx);
1286 /* 100 and 200 MHz mode. */
1287 if (ctx->cur_samplerate >= SR_MHZ(100)) {
1288 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, ctx);
1290 /* Find which pin to trigger on from mask. */
1291 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1292 if ((ctx->trigger.risingmask | ctx->trigger.fallingmask) &
1296 /* Set trigger pin and light LED on trigger. */
1297 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1299 /* Default rising edge. */
1300 if (ctx->trigger.fallingmask)
1301 triggerselect |= 1 << 3;
1303 /* All other modes. */
1304 } else if (ctx->cur_samplerate <= SR_MHZ(50)) {
1305 build_basic_trigger(&lut, ctx);
1307 sigma_write_trigger_lut(&lut, ctx);
1309 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1312 /* Setup trigger in and out pins to default values. */
1313 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1314 triggerinout_conf.trgout_bytrigger = 1;
1315 triggerinout_conf.trgout_enable = 1;
1317 sigma_write_register(WRITE_TRIGGER_OPTION,
1318 (uint8_t *) &triggerinout_conf,
1319 sizeof(struct triggerinout), ctx);
1321 /* Go back to normal mode. */
1322 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, ctx);
1324 /* Set clock select register. */
1325 if (ctx->cur_samplerate == SR_MHZ(200))
1326 /* Enable 4 probes. */
1327 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, ctx);
1328 else if (ctx->cur_samplerate == SR_MHZ(100))
1329 /* Enable 8 probes. */
1330 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, ctx);
1333 * 50 MHz mode (or fraction thereof). Any fraction down to
1334 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1336 frac = SR_MHZ(50) / ctx->cur_samplerate - 1;
1338 clockselect.async = 0;
1339 clockselect.fraction = frac;
1340 clockselect.disabled_probes = 0;
1342 sigma_write_register(WRITE_CLOCK_SELECT,
1343 (uint8_t *) &clockselect,
1344 sizeof(clockselect), ctx);
1347 /* Setup maximum post trigger time. */
1348 sigma_set_register(WRITE_POST_TRIGGER,
1349 (ctx->capture_ratio * 255) / 100, ctx);
1351 /* Start acqusition. */
1352 gettimeofday(&ctx->start_tv, 0);
1353 sigma_set_register(WRITE_MODE, 0x0d, ctx);
1355 ctx->session_dev_id = cb_data;
1357 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1358 sr_err("sigma: %s: packet malloc failed.", __func__);
1359 return SR_ERR_MALLOC;
1362 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1363 sr_err("sigma: %s: header malloc failed.", __func__);
1364 return SR_ERR_MALLOC;
1367 /* Send header packet to the session bus. */
1368 packet->type = SR_DF_HEADER;
1369 packet->payload = header;
1370 header->feed_version = 1;
1371 gettimeofday(&header->starttime, NULL);
1372 sr_session_send(ctx->session_dev_id, packet);
1374 /* Send metadata about the SR_DF_LOGIC packets to come. */
1375 packet->type = SR_DF_META_LOGIC;
1376 packet->payload = &meta;
1377 meta.samplerate = ctx->cur_samplerate;
1378 meta.num_probes = ctx->num_probes;
1379 sr_session_send(ctx->session_dev_id, packet);
1381 /* Add capture source. */
1382 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1387 ctx->state.state = SIGMA_CAPTURE;
1392 static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1395 struct context *ctx;
1398 /* Avoid compiler warnings. */
1401 if (!(ctx = sdi->priv)) {
1402 sr_err("sigma: %s: sdi->priv was NULL", __func__);
1406 /* Stop acquisition. */
1407 sigma_set_register(WRITE_MODE, 0x11, ctx);
1409 /* Set SDRAM Read Enable. */
1410 sigma_set_register(WRITE_MODE, 0x02, ctx);
1412 /* Get the current position. */
1413 sigma_read_pos(&ctx->state.stoppos, &ctx->state.triggerpos, ctx);
1415 /* Check if trigger has fired. */
1416 modestatus = sigma_get_register(READ_MODE, ctx);
1417 if (modestatus & 0x20)
1418 ctx->state.triggerchunk = ctx->state.triggerpos / 512;
1420 ctx->state.triggerchunk = -1;
1422 ctx->state.chunks_downloaded = 0;
1424 ctx->state.state = SIGMA_DOWNLOAD;
1429 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1430 .name = "asix-sigma",
1431 .longname = "ASIX SIGMA/SIGMA2",
1434 .cleanup = hw_cleanup,
1436 .dev_open = hw_dev_open,
1437 .dev_close = hw_dev_close,
1438 .info_get = hw_info_get,
1439 .dev_config_set = hw_dev_config_set,
1440 .dev_acquisition_start = hw_dev_acquisition_start,
1441 .dev_acquisition_stop = hw_dev_acquisition_stop,