2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # USB signalling (low-speed and full-speed) protocol decoder
24 import sigrokdecode as srd
26 # Low-/full-speed symbols.
27 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
30 # (<dp>, <dm>): <symbol/state>
37 # (<dp>, <dm>): <symbol/state>
46 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
47 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
50 class Decoder(srd.Decoder):
53 name = 'USB signalling'
54 longname = 'Universal Serial Bus (LS/FS) signalling'
55 desc = 'USB (low-speed and full-speed) signalling protocol.'
58 outputs = ['usb_signalling']
60 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
61 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
65 'signalling': ['Signalling', 'full-speed'],
69 ['sop', 'Start of packet (SOP)'],
70 ['eop', 'End of packet (EOP)'],
72 ['stuffbit', 'Stuff bit'],
77 self.oldsym = 'J' # The "idle" state is J.
86 self.samplenum_target = None
88 self.consecutive_ones = 0
91 def start(self, metadata):
92 self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb_signalling')
93 self.out_ann = self.add(srd.OUTPUT_ANN, 'usb_signalling')
94 self.bitrate = bitrates[self.options['signalling']]
95 self.bitwidth = float(metadata['samplerate']) / float(self.bitrate)
96 self.halfbit = int(self.bitwidth / 2)
101 def putpx(self, data):
102 self.put(self.samplenum, self.samplenum, self.out_proto, data)
104 def putx(self, data):
105 self.put(self.samplenum, self.samplenum, self.out_ann, data)
107 def putpm(self, data):
108 s, h = self.samplenum, self.halfbit
109 self.put(self.ss_block - h, self.samplenum + h, self.out_proto, data)
111 def putm(self, data):
112 s, h = self.samplenum, self.halfbit
113 self.put(self.ss_block - h, self.samplenum + h, self.out_ann, data)
115 def putpb(self, data):
116 s, h = self.samplenum, self.halfbit
117 self.put(s - h, s + h, self.out_proto, data)
119 def putb(self, data):
120 s, h = self.samplenum, self.halfbit
121 self.put(s - h, s + h, self.out_ann, data)
123 def set_new_target_samplenum(self):
124 bitpos = self.ss_sop + (self.bitwidth / 2)
125 bitpos += self.bitnum * self.bitwidth
126 self.samplenum_target = int(bitpos)
128 def wait_for_sop(self, sym):
129 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
133 self.ss_sop = self.samplenum
134 self.set_new_target_samplenum()
135 self.putpx(['SOP', None])
136 self.putx([1, ['SOP']])
137 self.state = 'GET BIT'
139 def handle_bit(self, sym, b):
140 if self.consecutive_ones == 6 and b == '0':
141 # Stuff bit. Don't add to the packet, reset self.consecutive_ones.
142 self.putb([4, ['SB: %s/%s' % (sym, b)]])
143 self.consecutive_ones = 0
145 # Normal bit. Add it to the packet, update self.consecutive_ones.
146 self.putb([3, ['%s/%s' % (sym, b)]])
149 self.consecutive_ones += 1
151 self.consecutive_ones = 0
153 def get_eop(self, sym):
154 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
155 self.syms.append(sym)
156 self.putpb(['SYM', sym])
157 self.putb([0, ['%s' % sym]])
159 self.set_new_target_samplenum()
161 if self.syms[-2:] == ['SE0', 'J']:
162 # Got an EOP, i.e. we now have a full packet.
163 self.putpm(['EOP', None])
164 self.putm([2, ['EOP']])
165 self.ss_block = self.ss_sop
166 self.putpm(['PACKET', self.packet])
167 self.putm([5, ['PACKET: %s' % self.packet]])
168 self.bitnum, self.packet, self.syms, self.state = 0, '', [], 'IDLE'
169 self.consecutive_ones = 0
171 def get_bit(self, sym):
173 # Start of an EOP. Change state, run get_eop() for this bit.
174 self.state = 'GET EOP'
175 self.ss_block = self.samplenum
178 self.syms.append(sym)
179 self.putpb(['SYM', sym])
180 b = '0' if self.oldsym != sym else '1'
181 self.handle_bit(sym, b)
183 self.set_new_target_samplenum()
186 def decode(self, ss, es, data):
187 for (self.samplenum, pins) in data:
189 if self.state == 'IDLE':
190 # Ignore identical samples early on (for performance reasons).
191 if self.oldpins == pins:
194 sym = symbols[self.options['signalling']][tuple(pins)]
195 self.wait_for_sop(sym)
196 elif self.state in ('GET BIT', 'GET EOP'):
197 # Wait until we're in the middle of the desired bit.
198 if self.samplenum < self.samplenum_target:
200 sym = symbols[self.options['signalling']][tuple(pins)]
201 if self.state == 'GET BIT':
203 elif self.state == 'GET EOP':
206 raise Exception('Invalid state: %s' % self.state)