2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
41 - 'J', 'K', 'SE0', or 'SE1'
45 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
48 # Low-/full-speed symbols.
49 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
52 # (<dp>, <dm>): <symbol/state>
59 # (<dp>, <dm>): <symbol/state>
66 # (<dp>, <dm>): <symbol/state>
72 # After a PREamble PID, the bus segment between Host and Hub uses LS
73 # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
74 # both upstream and downstream low-speed data, the hub is responsible for
75 # inverting the polarity of the data before transmitting to/from a
78 # (<dp>, <dm>): <symbol/state>
87 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
88 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
89 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
96 'SE0': [2, ['SE0', '0']],
97 'SE1': [3, ['SE1', '1']],
100 class SamplerateError(Exception):
103 class Decoder(srd.Decoder):
105 id = 'usb_signalling'
106 name = 'USB signalling'
107 longname = 'Universal Serial Bus (LS/FS) signalling'
108 desc = 'USB (low-speed and full-speed) signalling protocol.'
111 outputs = ['usb_signalling']
113 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
114 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
117 {'id': 'signalling', 'desc': 'Signalling',
118 'default': 'automatic', 'values': ('automatic', 'full-speed', 'low-speed')},
121 ('sym-j', 'J symbol'),
122 ('sym-k', 'K symbol'),
123 ('sym-se0', 'SE0 symbol'),
124 ('sym-se1', 'SE1 symbol'),
125 ('sop', 'Start of packet (SOP)'),
126 ('eop', 'End of packet (EOP)'),
128 ('stuffbit', 'Stuff bit'),
130 ('keep-alive', 'Low-speed keep-alive'),
134 ('bits', 'Bits', (4, 5, 6, 7, 8, 9, 10)),
135 ('symbols', 'Symbols', (0, 1, 2, 3)),
139 self.samplerate = None
140 self.oldsym = 'J' # The "idle" state is J.
145 self.samplepos = None
146 self.samplenum_target = None
147 self.samplenum_edge = None
148 self.samplenum_lastedge = 0
151 self.consecutive_ones = 0
156 self.out_python = self.register(srd.OUTPUT_PYTHON)
157 self.out_ann = self.register(srd.OUTPUT_ANN)
159 def metadata(self, key, value):
160 if key == srd.SRD_CONF_SAMPLERATE:
161 self.samplerate = value
162 self.signalling = self.options['signalling']
163 if self.signalling != 'automatic':
164 self.update_bitrate()
166 def update_bitrate(self):
167 self.bitrate = bitrates[self.signalling]
168 self.bitwidth = float(self.samplerate) / float(self.bitrate)
170 def putpx(self, data):
171 s = self.samplenum_edge
172 self.put(s, s, self.out_python, data)
174 def putx(self, data):
175 s = self.samplenum_edge
176 self.put(s, s, self.out_ann, data)
178 def putpm(self, data):
179 e = self.samplenum_edge
180 self.put(self.ss_block, e, self.out_python, data)
182 def putm(self, data):
183 e = self.samplenum_edge
184 self.put(self.ss_block, e, self.out_ann, data)
186 def putpb(self, data):
187 s, e = self.samplenum_lastedge, self.samplenum_edge
188 self.put(s, e, self.out_python, data)
190 def putb(self, data):
191 s, e = self.samplenum_lastedge, self.samplenum_edge
192 self.put(s, e, self.out_ann, data)
194 def set_new_target_samplenum(self):
195 self.samplepos += self.bitwidth;
196 self.samplenum_target = int(self.samplepos)
197 self.samplenum_lastedge = self.samplenum_edge
198 self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
200 def wait_for_sop(self, sym):
201 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
202 if sym != 'K' or self.oldsym != 'J':
204 self.consecutive_ones = 0
206 self.update_bitrate()
207 self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
208 self.set_new_target_samplenum()
209 self.putpx(['SOP', None])
210 self.putx([4, ['SOP', 'S']])
211 self.state = 'GET BIT'
213 def handle_bit(self, b):
214 if self.consecutive_ones == 6:
217 self.putpb(['STUFF BIT', None])
218 self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
219 self.consecutive_ones = 0
221 self.putpb(['ERR', None])
222 self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
225 # Normal bit (not a stuff bit).
226 self.putpb(['BIT', b])
227 self.putb([6, ['%s' % b]])
229 self.consecutive_ones += 1
231 self.consecutive_ones = 0
233 def get_eop(self, sym):
234 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
235 self.set_new_target_samplenum()
236 self.putpb(['SYM', sym])
237 self.putb(sym_annotation[sym])
243 self.putpm(['EOP', None])
244 self.putm([5, ['EOP', 'E']])
245 self.state = 'WAIT IDLE'
247 self.putpm(['ERR', None])
248 self.putm([8, ['EOP Error', 'EErr', 'E']])
251 def get_bit(self, sym):
252 self.set_new_target_samplenum()
253 b = '0' if self.oldsym != sym else '1'
256 # Start of an EOP. Change state, save edge
257 self.state = 'GET EOP'
258 self.ss_block = self.samplenum_lastedge
261 self.putpb(['SYM', sym])
262 self.putb(sym_annotation[sym])
263 if len(self.bits) <= 16:
265 if len(self.bits) == 16 and self.bits == '0000000100111100':
266 # Sync and low-speed PREamble seen
267 self.putpx(['EOP', None])
269 self.signalling = 'low-speed-rp'
270 self.update_bitrate()
273 edgesym = symbols[self.signalling][tuple(self.edgepins)]
274 if edgesym not in ('SE0', 'SE1'):
276 self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
277 self.samplepos = self.samplepos - (0.01 * self.bitwidth)
279 self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
280 self.samplepos = self.samplepos + (0.01 * self.bitwidth)
282 def handle_idle(self, sym):
283 self.samplenum_edge = self.samplenum
284 se0_length = float(self.samplenum - self.samplenum_lastedge) / self.samplerate
285 if se0_length > 2.5e-6: # 2.5us
286 self.putpb(['RESET', None])
287 self.putb([10, ['Reset', 'Res', 'R']])
288 self.signalling = self.options['signalling']
289 elif se0_length > 1.2e-6 and self.signalling == 'low-speed':
290 self.putpb(['KEEP ALIVE', None])
291 self.putb([9, ['Keep-alive', 'KA', 'A']])
294 self.signalling = 'full-speed'
295 self.update_bitrate()
297 self.signalling = 'low-speed'
298 self.update_bitrate()
302 def decode(self, ss, es, data):
303 if not self.samplerate:
304 raise SamplerateError('Cannot decode without samplerate.')
305 for (self.samplenum, pins) in data:
307 if self.state == 'IDLE':
308 # Ignore identical samples early on (for performance reasons).
309 if self.oldpins == pins:
312 sym = symbols[self.signalling][tuple(pins)]
314 self.samplenum_lastedge = self.samplenum
315 self.state = 'WAIT IDLE'
317 self.wait_for_sop(sym)
319 elif self.state in ('GET BIT', 'GET EOP'):
320 # Wait until we're in the middle of the desired bit.
321 if self.samplenum == self.samplenum_edge:
323 if self.samplenum < self.samplenum_target:
325 sym = symbols[self.signalling][tuple(pins)]
326 if self.state == 'GET BIT':
328 elif self.state == 'GET EOP':
331 elif self.state == 'WAIT IDLE':
332 if tuple(pins) == (0, 0):
334 if self.samplenum - self.samplenum_lastedge > 1:
335 sym = symbols[self.options['signalling']][tuple(pins)]
336 self.handle_idle(sym)
338 sym = symbols[self.signalling][tuple(pins)]
339 self.wait_for_sop(sym)
342 elif self.state == 'INIT':
343 sym = symbols[self.options['signalling']][tuple(pins)]
344 self.handle_idle(sym)