2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
21 import sigrokdecode as srd
40 - 'J', 'K', 'SE0', or 'SE1'
44 - Note: Symbols like SE0, SE1, and the J that's part of EOP don't yield 'BIT'.
47 # Low-/full-speed symbols.
48 # Note: Low-speed J and K are inverted compared to the full-speed J and K!
51 # (<dp>, <dm>): <symbol/state>
58 # (<dp>, <dm>): <symbol/state>
65 # (<dp>, <dm>): <symbol/state>
71 # After a PREamble PID, the bus segment between Host and Hub uses LS
72 # signalling rate and FS signalling polarity (USB 2.0 spec, 11.8.4: "For
73 # both upstream and downstream low-speed data, the hub is responsible for
74 # inverting the polarity of the data before transmitting to/from a
77 # (<dp>, <dm>): <symbol/state>
86 'low-speed': 1500000, # 1.5Mb/s (+/- 1.5%)
87 'low-speed-rp': 1500000, # 1.5Mb/s (+/- 1.5%)
88 'full-speed': 12000000, # 12Mb/s (+/- 0.25%)
95 'SE0': [2, ['SE0', '0']],
96 'SE1': [3, ['SE1', '1']],
99 class SamplerateError(Exception):
102 class Decoder(srd.Decoder):
104 id = 'usb_signalling'
105 name = 'USB signalling'
106 longname = 'Universal Serial Bus (LS/FS) signalling'
107 desc = 'USB (low-speed and full-speed) signalling protocol.'
110 outputs = ['usb_signalling']
112 {'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
113 {'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
116 {'id': 'signalling', 'desc': 'Signalling',
117 'default': 'automatic', 'values': ('automatic', 'full-speed', 'low-speed')},
120 ('sym-j', 'J symbol'),
121 ('sym-k', 'K symbol'),
122 ('sym-se0', 'SE0 symbol'),
123 ('sym-se1', 'SE1 symbol'),
124 ('sop', 'Start of packet (SOP)'),
125 ('eop', 'End of packet (EOP)'),
127 ('stuffbit', 'Stuff bit'),
129 ('keep-alive', 'Low-speed keep-alive'),
133 ('bits', 'Bits', (4, 5, 6, 7, 8, 9, 10)),
134 ('symbols', 'Symbols', (0, 1, 2, 3)),
138 self.samplerate = None
139 self.oldsym = 'J' # The "idle" state is J.
144 self.samplepos = None
145 self.samplenum_target = None
146 self.samplenum_edge = None
147 self.samplenum_lastedge = 0
149 self.consecutive_ones = 0
154 self.out_python = self.register(srd.OUTPUT_PYTHON)
155 self.out_ann = self.register(srd.OUTPUT_ANN)
157 def metadata(self, key, value):
158 if key == srd.SRD_CONF_SAMPLERATE:
159 self.samplerate = value
160 self.signalling = self.options['signalling']
161 if self.signalling != 'automatic':
162 self.update_bitrate()
164 def update_bitrate(self):
165 self.bitrate = bitrates[self.signalling]
166 self.bitwidth = float(self.samplerate) / float(self.bitrate)
168 def putpx(self, data):
169 s = self.samplenum_edge
170 self.put(s, s, self.out_python, data)
172 def putx(self, data):
173 s = self.samplenum_edge
174 self.put(s, s, self.out_ann, data)
176 def putpm(self, data):
177 e = self.samplenum_edge
178 self.put(self.ss_block, e, self.out_python, data)
180 def putm(self, data):
181 e = self.samplenum_edge
182 self.put(self.ss_block, e, self.out_ann, data)
184 def putpb(self, data):
185 s, e = self.samplenum_lastedge, self.samplenum_edge
186 self.put(s, e, self.out_python, data)
188 def putb(self, data):
189 s, e = self.samplenum_lastedge, self.samplenum_edge
190 self.put(s, e, self.out_ann, data)
192 def set_new_target_samplenum(self):
193 self.samplepos += self.bitwidth;
194 self.samplenum_target = int(self.samplepos)
195 self.samplenum_lastedge = self.samplenum_edge
196 self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
198 def wait_for_sop(self, sym):
199 # Wait for a Start of Packet (SOP), i.e. a J->K symbol change.
200 if sym != 'K' or self.oldsym != 'J':
202 self.consecutive_ones = 0
204 self.update_bitrate()
205 self.samplepos = self.samplenum - (self.bitwidth / 2) + 0.5
206 self.set_new_target_samplenum()
207 self.putpx(['SOP', None])
208 self.putx([4, ['SOP', 'S']])
209 self.state = 'GET BIT'
211 def handle_bit(self, b):
212 if self.consecutive_ones == 6:
215 self.putpb(['STUFF BIT', None])
216 self.putb([7, ['Stuff bit: 0', 'SB: 0', '0']])
217 self.consecutive_ones = 0
219 self.putpb(['ERR', None])
220 self.putb([8, ['Bit stuff error', 'BS ERR', 'B']])
223 # Normal bit (not a stuff bit).
224 self.putpb(['BIT', b])
225 self.putb([6, ['%s' % b]])
227 self.consecutive_ones += 1
229 self.consecutive_ones = 0
231 def get_eop(self, sym):
232 # EOP: SE0 for >= 1 bittime (usually 2 bittimes), then J.
233 self.set_new_target_samplenum()
234 self.putpb(['SYM', sym])
235 self.putb(sym_annotation[sym])
241 self.putpm(['EOP', None])
242 self.putm([5, ['EOP', 'E']])
243 self.state = 'WAIT IDLE'
245 self.putpm(['ERR', None])
246 self.putm([8, ['EOP Error', 'EErr', 'E']])
249 def get_bit(self, sym):
250 self.set_new_target_samplenum()
251 b = '0' if self.oldsym != sym else '1'
254 # Start of an EOP. Change state, save edge
255 self.state = 'GET EOP'
256 self.ss_block = self.samplenum_lastedge
259 self.putpb(['SYM', sym])
260 self.putb(sym_annotation[sym])
261 if len(self.bits) <= 16:
263 if len(self.bits) == 16 and self.bits == '0000000100111100':
264 # Sync and low-speed PREamble seen
265 self.putpx(['EOP', None])
267 self.signalling = 'low-speed-rp'
268 self.update_bitrate()
271 edgesym = symbols[self.signalling][tuple(self.edgepins)]
272 if edgesym not in ('SE0', 'SE1'):
274 self.bitwidth = self.bitwidth - (0.001 * self.bitwidth)
275 self.samplepos = self.samplepos - (0.01 * self.bitwidth)
277 self.bitwidth = self.bitwidth + (0.001 * self.bitwidth)
278 self.samplepos = self.samplepos + (0.01 * self.bitwidth)
280 def handle_idle(self, sym):
281 self.samplenum_edge = self.samplenum
282 se0_length = float(self.samplenum - self.samplenum_lastedge) / self.samplerate
283 if se0_length > 2.5e-6: # 2.5us
284 self.putpb(['RESET', None])
285 self.putb([10, ['Reset', 'Res', 'R']])
286 self.signalling = self.options['signalling']
287 elif se0_length > 1.2e-6 and self.signalling == 'low-speed':
288 self.putpb(['KEEP ALIVE', None])
289 self.putb([9, ['Keep-alive', 'KA', 'A']])
292 self.signalling = 'full-speed'
293 self.update_bitrate()
295 self.signalling = 'low-speed'
296 self.update_bitrate()
301 if not self.samplerate:
302 raise SamplerateError('Cannot decode without samplerate.')
304 # Seed internal state from the very first sample.
306 sym = symbols[self.options['signalling']][pins]
307 self.handle_idle(sym)
311 if self.state == 'IDLE':
312 # Wait for any edge on either DP and/or DM.
313 pins = self.wait([{0: 'e'}, {1: 'e'}])
314 sym = symbols[self.signalling][pins]
316 self.samplenum_lastedge = self.samplenum
317 self.state = 'WAIT IDLE'
319 self.wait_for_sop(sym)
321 elif self.state in ('GET BIT', 'GET EOP'):
322 # Wait until we're in the middle of the desired bit.
323 self.edgepins = self.wait([{'skip': self.samplenum_edge - self.samplenum}])
324 pins = self.wait([{'skip': self.samplenum_target - self.samplenum}])
326 sym = symbols[self.signalling][pins]
327 if self.state == 'GET BIT':
329 elif self.state == 'GET EOP':
331 elif self.state == 'WAIT IDLE':
332 # Skip "all-low" input. Wait for high level on either DP or DM.
334 while not pins[0] and not pins[1]:
335 pins = self.wait([{0: 'h'}, {1: 'h'}])
336 if self.samplenum - self.samplenum_lastedge > 1:
337 sym = symbols[self.options['signalling']][pins]
338 self.handle_idle(sym)
340 sym = symbols[self.signalling][pins]
341 self.wait_for_sop(sym)