2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
21 from common.srdhelper import bitpack
22 from math import floor, ceil
28 [<ptype>, <rxtx>, <pdata>]
30 This is the list of <ptype>s and their respective <pdata> values:
31 - 'STARTBIT': The data is the (integer) value of the start bit (0/1).
32 - 'DATA': This is always a tuple containing two items:
33 - 1st item: the (integer) value of the UART data. Valid values
34 range from 0 to 511 (as the data can be up to 9 bits in size).
35 - 2nd item: the list of individual data bits and their ss/es numbers.
36 - 'PARITYBIT': The data is the (integer) value of the parity bit (0/1).
37 - 'STOPBIT': The data is the (integer) value of the stop bit (0 or 1).
38 - 'INVALID STARTBIT': The data is the (integer) value of the start bit (0/1).
39 - 'INVALID STOPBIT': The data is the (integer) value of the stop bit (0/1).
40 - 'PARITY ERROR': The data is a tuple with two entries. The first one is
41 the expected parity value, the second is the actual parity value.
42 - 'BREAK': The data is always 0.
43 - 'FRAME': The data is always a tuple containing two items: The (integer)
44 value of the UART data, and a boolean which reflects the validity of the
46 - 'IDLE': The data is always 0.
48 The <rxtx> field is 0 for RX packets, 1 for TX packets.
51 # Used for differentiating between the two data directions.
55 # Given a parity type to check (odd, even, zero, one), the value of the
56 # parity bit, the value of the data, and the length of the data (5-9 bits,
57 # usually 8 bits) return True if the parity is correct, False otherwise.
58 # 'none' is _not_ allowed as value for 'parity_type'.
59 def parity_ok(parity_type, parity_bit, data, data_bits):
61 if parity_type == 'ignore':
64 # Handle easy cases first (parity bit is always 1 or 0).
65 if parity_type == 'zero':
66 return parity_bit == 0
67 elif parity_type == 'one':
68 return parity_bit == 1
70 # Count number of 1 (high) bits in the data (and the parity bit itself!).
71 ones = bin(data).count('1') + parity_bit
73 # Check for odd/even parity.
74 if parity_type == 'odd':
75 return (ones % 2) == 1
76 elif parity_type == 'even':
77 return (ones % 2) == 0
79 class SamplerateError(Exception):
82 class ChannelError(Exception):
86 RX_DATA, TX_DATA, RX_START, TX_START, RX_PARITY_OK, TX_PARITY_OK, \
87 RX_PARITY_ERR, TX_PARITY_ERR, RX_STOP, TX_STOP, RX_WARN, TX_WARN, \
88 RX_DATA_BIT, TX_DATA_BIT, RX_BREAK, TX_BREAK, RX_PACKET, TX_PACKET = \
92 RX, TX, RXTX = range(3)
94 class Decoder(srd.Decoder):
98 longname = 'Universal Asynchronous Receiver/Transmitter'
99 desc = 'Asynchronous, serial bus.'
103 tags = ['Embedded/industrial']
104 optional_channels = (
105 # Allow specifying only one of the signals, e.g. if only one data
106 # direction exists (or is relevant).
107 {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
108 {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
111 {'id': 'baudrate', 'desc': 'Baud rate', 'default': 115200},
112 {'id': 'data_bits', 'desc': 'Data bits', 'default': 8,
113 'values': (5, 6, 7, 8, 9)},
114 {'id': 'parity', 'desc': 'Parity', 'default': 'none',
115 'values': ('none', 'odd', 'even', 'zero', 'one', 'ignore')},
116 {'id': 'stop_bits', 'desc': 'Stop bits', 'default': 1.0,
117 'values': (0.0, 0.5, 1.0, 1.5, 2.0)},
118 {'id': 'bit_order', 'desc': 'Bit order', 'default': 'lsb-first',
119 'values': ('lsb-first', 'msb-first')},
120 {'id': 'format', 'desc': 'Data format', 'default': 'hex',
121 'values': ('ascii', 'dec', 'hex', 'oct', 'bin')},
122 {'id': 'invert_rx', 'desc': 'Invert RX', 'default': 'no',
123 'values': ('yes', 'no')},
124 {'id': 'invert_tx', 'desc': 'Invert TX', 'default': 'no',
125 'values': ('yes', 'no')},
126 {'id': 'sample_point', 'desc': 'Sample point (%)', 'default': 50},
127 {'id': 'rx_packet_delim', 'desc': 'RX packet delimiter (decimal)',
129 {'id': 'tx_packet_delim', 'desc': 'TX packet delimiter (decimal)',
131 {'id': 'rx_packet_len', 'desc': 'RX packet length', 'default': -1},
132 {'id': 'tx_packet_len', 'desc': 'TX packet length', 'default': -1},
135 ('rx-data', 'RX data'),
136 ('tx-data', 'TX data'),
137 ('rx-start', 'RX start bit'),
138 ('tx-start', 'TX start bit'),
139 ('rx-parity-ok', 'RX parity OK bit'),
140 ('tx-parity-ok', 'TX parity OK bit'),
141 ('rx-parity-err', 'RX parity error bit'),
142 ('tx-parity-err', 'TX parity error bit'),
143 ('rx-stop', 'RX stop bit'),
144 ('tx-stop', 'TX stop bit'),
145 ('rx-warning', 'RX warning'),
146 ('tx-warning', 'TX warning'),
147 ('rx-data-bit', 'RX data bit'),
148 ('tx-data-bit', 'TX data bit'),
149 ('rx-break', 'RX break'),
150 ('tx-break', 'TX break'),
151 ('rx-packet', 'RX packet'),
152 ('tx-packet', 'TX packet'),
155 ('rx-data-bits', 'RX bits', (Ann.RX_DATA_BIT,)),
156 ('rx-data-vals', 'RX data', (Ann.RX_DATA, Ann.RX_START, Ann.RX_PARITY_OK, Ann.RX_PARITY_ERR, Ann.RX_STOP)),
157 ('rx-warnings', 'RX warnings', (Ann.RX_WARN,)),
158 ('rx-breaks', 'RX breaks', (Ann.RX_BREAK,)),
159 ('rx-packets', 'RX packets', (Ann.RX_PACKET,)),
160 ('tx-data-bits', 'TX bits', (Ann.TX_DATA_BIT,)),
161 ('tx-data-vals', 'TX data', (Ann.TX_DATA, Ann.TX_START, Ann.TX_PARITY_OK, Ann.TX_PARITY_ERR, Ann.TX_STOP)),
162 ('tx-warnings', 'TX warnings', (Ann.TX_WARN,)),
163 ('tx-breaks', 'TX breaks', (Ann.TX_BREAK,)),
164 ('tx-packets', 'TX packets', (Ann.TX_PACKET,)),
169 ('rxtx', 'RX/TX dump'),
171 idle_state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
173 def putx(self, rxtx, data):
174 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
175 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
177 def putx_packet(self, rxtx, data):
178 s, halfbit = self.ss_packet[rxtx], self.bit_width / 2.0
179 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_ann, data)
181 def putpx(self, rxtx, data):
182 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
183 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_python, data)
185 def putg(self, data):
186 s, halfbit = self.samplenum, self.bit_width / 2.0
187 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_ann, data)
189 def putp(self, data):
190 s, halfbit = self.samplenum, self.bit_width / 2.0
191 self.put(s - floor(halfbit), s + ceil(halfbit), self.out_python, data)
193 def putgse(self, ss, es, data):
194 self.put(ss, es, self.out_ann, data)
196 def putpse(self, ss, es, data):
197 self.put(ss, es, self.out_python, data)
199 def putbin(self, rxtx, data):
200 s, halfbit = self.startsample[rxtx], self.bit_width / 2.0
201 self.put(s - floor(halfbit), self.samplenum + ceil(halfbit), self.out_binary, data)
207 self.samplerate = None
208 self.frame_start = [-1, -1]
209 self.frame_valid = [None, None]
210 self.startbit = [-1, -1]
211 self.cur_data_bit = [0, 0]
212 self.datavalue = [0, 0]
213 self.paritybit = [-1, -1]
214 self.stopbits = [[], []]
215 self.startsample = [-1, -1]
216 self.state = ['WAIT FOR START BIT', 'WAIT FOR START BIT']
217 self.databits = [[], []]
218 self.break_start = [None, None]
219 self.packet_cache = [[], []]
220 self.ss_packet, self.es_packet = [None, None], [None, None]
221 self.idle_start = [None, None]
224 self.out_python = self.register(srd.OUTPUT_PYTHON)
225 self.out_binary = self.register(srd.OUTPUT_BINARY)
226 self.out_ann = self.register(srd.OUTPUT_ANN)
227 self.bw = (self.options['data_bits'] + 7) // 8
229 def metadata(self, key, value):
230 if key == srd.SRD_CONF_SAMPLERATE:
231 self.samplerate = value
232 # The width of one UART bit in number of samples.
233 self.bit_width = float(self.samplerate) / float(self.options['baudrate'])
235 def get_sample_point(self, rxtx, bitnum):
236 # Determine absolute sample number of a bit slot's sample point.
237 # Counts for UART bits start from 0 (0 = start bit, 1..x = data,
238 # x+1 = parity bit (if used) or the first stop bit, and so on).
239 # Accept a position in the range of 1-99% of the full bit width.
240 # Assume 50% for invalid input specs for backwards compatibility.
241 perc = self.options['sample_point'] or 50
242 if not perc or perc not in range(1, 100):
245 bitpos = (self.bit_width - 1) * perc
246 bitpos += self.frame_start[rxtx]
247 bitpos += bitnum * self.bit_width
250 def wait_for_start_bit(self, rxtx, signal):
251 # Save the sample number where the start bit begins.
252 self.frame_start[rxtx] = self.samplenum
253 self.frame_valid[rxtx] = True
255 self.advance_state(rxtx, signal)
257 def get_start_bit(self, rxtx, signal):
258 self.startbit[rxtx] = signal
260 # The startbit must be 0. If not, we report an error and wait
261 # for the next start bit (assuming this one was spurious).
262 if self.startbit[rxtx] != 0:
263 self.putp(['INVALID STARTBIT', rxtx, self.startbit[rxtx]])
264 self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
265 self.frame_valid[rxtx] = False
266 es = self.samplenum + ceil(self.bit_width / 2.0)
267 self.putpse(self.frame_start[rxtx], es, ['FRAME', rxtx,
268 (self.datavalue[rxtx], self.frame_valid[rxtx])])
269 self.advance_state(rxtx, signal, fatal = True, idle = es)
272 # Reset internal state for the pending UART frame.
273 self.cur_data_bit[rxtx] = 0
274 self.datavalue[rxtx] = 0
275 self.paritybit[rxtx] = -1
276 self.stopbits[rxtx].clear()
277 self.startsample[rxtx] = -1
278 self.databits[rxtx].clear()
280 self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
281 self.putg([Ann.RX_START + rxtx, ['Start bit', 'Start', 'S']])
283 self.advance_state(rxtx, signal)
285 def handle_packet(self, rxtx):
286 d = 'rx' if (rxtx == RX) else 'tx'
287 delim = self.options[d + '_packet_delim']
288 plen = self.options[d + '_packet_len']
289 if delim == -1 and plen == -1:
292 # Cache data values until we see the delimiter and/or the specified
293 # packet length has been reached (whichever happens first).
294 if len(self.packet_cache[rxtx]) == 0:
295 self.ss_packet[rxtx] = self.startsample[rxtx]
296 self.packet_cache[rxtx].append(self.datavalue[rxtx])
297 if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
298 self.es_packet[rxtx] = self.samplenum
300 for b in self.packet_cache[rxtx]:
301 s += self.format_value(b)
302 if self.options['format'] != 'ascii':
304 if self.options['format'] != 'ascii' and s[-1] == ' ':
305 s = s[:-1] # Drop trailing space.
306 self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
307 self.packet_cache[rxtx] = []
309 def get_data_bits(self, rxtx, signal):
310 # Save the sample number of the middle of the first data bit.
311 if self.startsample[rxtx] == -1:
312 self.startsample[rxtx] = self.samplenum
314 self.putg([Ann.RX_DATA_BIT + rxtx, ['%d' % signal]])
316 # Store individual data bits and their start/end samplenumbers.
317 s, halfbit = self.samplenum, int(self.bit_width / 2)
318 self.databits[rxtx].append([signal, s - halfbit, s + halfbit])
320 # Return here, unless we already received all data bits.
321 self.cur_data_bit[rxtx] += 1
322 if self.cur_data_bit[rxtx] < self.options['data_bits']:
325 # Convert accumulated data bits to a data value.
326 bits = [b[0] for b in self.databits[rxtx]]
327 if self.options['bit_order'] == 'msb-first':
329 self.datavalue[rxtx] = bitpack(bits)
330 self.putpx(rxtx, ['DATA', rxtx,
331 (self.datavalue[rxtx], self.databits[rxtx])])
333 b = self.datavalue[rxtx]
334 formatted = self.format_value(b)
335 if formatted is not None:
336 self.putx(rxtx, [rxtx, [formatted]])
338 bdata = b.to_bytes(self.bw, byteorder='big')
339 self.putbin(rxtx, [Bin.RX + rxtx, bdata])
340 self.putbin(rxtx, [Bin.RXTX, bdata])
342 self.handle_packet(rxtx)
344 self.databits[rxtx] = []
346 self.advance_state(rxtx, signal)
348 def format_value(self, v):
349 # Format value 'v' according to configured options.
350 # Reflects the user selected kind of representation, as well as
351 # the number of data bits in the UART frames.
353 fmt, bits = self.options['format'], self.options['data_bits']
355 # Assume "is printable" for values from 32 to including 126,
356 # below 32 is "control" and thus not printable, above 127 is
357 # "not ASCII" in its strict sense, 127 (DEL) is not printable,
358 # fall back to hex representation for non-printables.
360 if v in range(32, 126 + 1):
362 hexfmt = "[{:02X}]" if bits <= 8 else "[{:03X}]"
363 return hexfmt.format(v)
365 # Mere number to text conversion without prefix and padding
366 # for the "decimal" output format.
368 return "{:d}".format(v)
370 # Padding with leading zeroes for hex/oct/bin formats, but
371 # without a prefix for density -- since the format is user
372 # specified, there is no ambiguity.
374 digits = (bits + 4 - 1) // 4
377 digits = (bits + 3 - 1) // 3
384 if fmtchar is not None:
385 fmt = "{{:0{:d}{:s}}}".format(digits, fmtchar)
390 def get_parity_bit(self, rxtx, signal):
391 self.paritybit[rxtx] = signal
393 if parity_ok(self.options['parity'], self.paritybit[rxtx],
394 self.datavalue[rxtx], self.options['data_bits']):
395 self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
396 self.putg([Ann.RX_PARITY_OK + rxtx, ['Parity bit', 'Parity', 'P']])
398 # TODO: Return expected/actual parity values.
399 self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
400 self.putg([Ann.RX_PARITY_ERR + rxtx, ['Parity error', 'Parity err', 'PE']])
401 self.frame_valid[rxtx] = False
403 self.advance_state(rxtx, signal)
405 def get_stop_bits(self, rxtx, signal):
406 self.stopbits[rxtx].append(signal)
408 # Stop bits must be 1. If not, we report an error.
410 self.putp(['INVALID STOPBIT', rxtx, signal])
411 self.putg([Ann.RX_WARN + rxtx, ['Frame error', 'Frame err', 'FE']])
412 self.frame_valid[rxtx] = False
414 self.putp(['STOPBIT', rxtx, signal])
415 self.putg([Ann.RX_STOP + rxtx, ['Stop bit', 'Stop', 'T']])
417 # Postprocess the UART frame after all STOP bits were seen.
418 if len(self.stopbits[rxtx]) < self.options['stop_bits']:
420 self.advance_state(rxtx, signal)
422 def advance_state(self, rxtx, signal = None, fatal = False, idle = None):
423 # Advances the protocol decoder's internal state for all regular
424 # UART frame inspection. Deals with either edges, sample points,
425 # or other .wait() conditions. Also gracefully handles extreme
426 # undersampling. Each turn takes one .wait() call which in turn
427 # corresponds to at least one sample. That is why as many state
428 # transitions are done here as required within a single call.
429 frame_end = self.frame_start[rxtx] + self.frame_len_sample_count
431 # When requested by the caller, start another (potential)
432 # IDLE period after the caller specified position.
433 self.idle_start[rxtx] = idle
435 # When requested by the caller, don't advance to the next
436 # UART frame's field, but to the start of the next START bit
438 self.state[rxtx] = 'WAIT FOR START BIT'
440 # Advance to the next UART frame's field that we expect. Cope
441 # with absence of optional fields. Force scan for next IDLE
442 # after the (optional) STOP bit field, so that callers need
443 # not deal with optional field presence. Also handles the cases
444 # where the decoder navigates to edges which are not strictly
445 # a field's sampling point.
446 if self.state[rxtx] == 'WAIT FOR START BIT':
447 self.state[rxtx] = 'GET START BIT'
449 if self.state[rxtx] == 'GET START BIT':
450 self.state[rxtx] = 'GET DATA BITS'
452 if self.state[rxtx] == 'GET DATA BITS':
453 self.state[rxtx] = 'GET PARITY BIT'
454 if self.options['parity'] != 'none':
457 if self.state[rxtx] == 'GET PARITY BIT':
458 self.state[rxtx] = 'GET STOP BITS'
459 if self.options['stop_bits']:
462 if self.state[rxtx] == 'GET STOP BITS':
463 # Postprocess the previously received UART frame. Advance
464 # the read position to after the frame's last bit time. So
465 # that the start of the next START bit won't fall into the
466 # end of the previously received UART frame. This improves
467 # robustness in the presence of glitchy input data.
468 ss = self.frame_start[rxtx]
469 es = self.samplenum + ceil(self.bit_width / 2.0)
470 self.handle_frame(rxtx, ss, es)
471 self.state[rxtx] = 'WAIT FOR START BIT'
472 self.idle_start[rxtx] = frame_end
474 # Unhandled state, actually a programming error. Emit diagnostics?
475 self.state[rxtx] = 'WAIT FOR START BIT'
477 def handle_frame(self, rxtx, ss, es):
478 # Pass the complete UART frame to upper layers.
479 self.putpse(ss, es, ['FRAME', rxtx,
480 (self.datavalue[rxtx], self.frame_valid[rxtx])])
482 def handle_idle(self, rxtx, ss, es):
483 self.putpse(ss, es, ['IDLE', rxtx, 0])
485 def handle_break(self, rxtx, ss, es):
486 self.putpse(ss, es, ['BREAK', rxtx, 0])
487 self.putgse(ss, es, [Ann.RX_BREAK + rxtx,
488 ['Break condition', 'Break', 'Brk', 'B']])
489 self.state[rxtx] = 'WAIT FOR START BIT'
491 def get_wait_cond(self, rxtx, inv):
492 # Return condititions that are suitable for Decoder.wait(). Those
493 # conditions either match the falling edge of the START bit, or
494 # the sample point of the next bit time.
495 state = self.state[rxtx]
496 if state == 'WAIT FOR START BIT':
497 return {rxtx: 'r' if inv else 'f'}
498 if state == 'GET START BIT':
500 elif state == 'GET DATA BITS':
501 bitnum = 1 + self.cur_data_bit[rxtx]
502 elif state == 'GET PARITY BIT':
503 bitnum = 1 + self.options['data_bits']
504 elif state == 'GET STOP BITS':
505 # TODO: Currently does not support half STOP bits.
506 bitnum = 1 + self.options['data_bits']
507 bitnum += 0 if self.options['parity'] == 'none' else 1
508 bitnum += len(self.stopbits[rxtx])
509 want_num = ceil(self.get_sample_point(rxtx, bitnum))
510 return {'skip': want_num - self.samplenum}
512 def get_idle_cond(self, rxtx, inv):
513 # Return a condition that corresponds to the (expected) end of
514 # the next frame, assuming that it will be an "idle frame"
515 # (constant high input level for the frame's length).
516 if self.idle_start[rxtx] is None:
518 end_of_frame = self.idle_start[rxtx] + self.frame_len_sample_count
519 if end_of_frame < self.samplenum:
521 return {'skip': end_of_frame - self.samplenum}
523 def inspect_sample(self, rxtx, signal, inv):
524 # Inspect a sample returned by .wait() for the specified UART line.
528 state = self.state[rxtx]
529 if state == 'WAIT FOR START BIT':
530 self.wait_for_start_bit(rxtx, signal)
531 elif state == 'GET START BIT':
532 self.get_start_bit(rxtx, signal)
533 elif state == 'GET DATA BITS':
534 self.get_data_bits(rxtx, signal)
535 elif state == 'GET PARITY BIT':
536 self.get_parity_bit(rxtx, signal)
537 elif state == 'GET STOP BITS':
538 self.get_stop_bits(rxtx, signal)
540 def inspect_edge(self, rxtx, signal, inv):
541 # Inspect edges, independently from traffic, to detect break conditions.
545 # Signal went low. Start another interval.
546 self.break_start[rxtx] = self.samplenum
548 # Signal went high. Was there an extended period with low signal?
549 if self.break_start[rxtx] is None:
551 diff = self.samplenum - self.break_start[rxtx]
552 if diff >= self.break_min_sample_count:
553 ss, es = self.frame_start[rxtx], self.samplenum
554 self.handle_break(rxtx, ss, es)
555 self.break_start[rxtx] = None
557 def inspect_idle(self, rxtx, signal, inv):
558 # Check each edge and each period of stable input (either level).
559 # Can derive the "idle frame period has passed" condition.
563 # Low input, cease inspection.
564 self.idle_start[rxtx] = None
566 # High input, either just reached, or still stable.
567 if self.idle_start[rxtx] is None:
568 self.idle_start[rxtx] = self.samplenum
569 diff = self.samplenum - self.idle_start[rxtx]
570 if diff < self.frame_len_sample_count:
572 ss, es = self.idle_start[rxtx], self.samplenum
573 self.handle_idle(rxtx, ss, es)
574 self.idle_start[rxtx] = es
577 if not self.samplerate:
578 raise SamplerateError('Cannot decode without samplerate.')
580 has_pin = [self.has_channel(ch) for ch in (RX, TX)]
581 if not True in has_pin:
582 raise ChannelError('Need at least one of TX or RX pins.')
585 inv = [opt['invert_rx'] == 'yes', opt['invert_tx'] == 'yes']
586 cond_data_idx = [None] * len(has_pin)
588 # Determine the number of samples for a complete frame's time span.
589 # A period of low signal (at least) that long is a break condition.
590 frame_samples = 1 # START
591 frame_samples += self.options['data_bits']
592 frame_samples += 0 if self.options['parity'] == 'none' else 1
593 frame_samples += self.options['stop_bits']
594 frame_samples *= self.bit_width
595 self.frame_len_sample_count = ceil(frame_samples)
596 self.break_min_sample_count = self.frame_len_sample_count
597 cond_edge_idx = [None] * len(has_pin)
598 cond_idle_idx = [None] * len(has_pin)
603 cond_data_idx[RX] = len(conds)
604 conds.append(self.get_wait_cond(RX, inv[RX]))
605 cond_edge_idx[RX] = len(conds)
606 conds.append({RX: 'e'})
607 cond_idle_idx[RX] = None
608 idle_cond = self.get_idle_cond(RX, inv[RX])
610 cond_idle_idx[RX] = len(conds)
611 conds.append(idle_cond)
613 cond_data_idx[TX] = len(conds)
614 conds.append(self.get_wait_cond(TX, inv[TX]))
615 cond_edge_idx[TX] = len(conds)
616 conds.append({TX: 'e'})
617 cond_idle_idx[TX] = None
618 idle_cond = self.get_idle_cond(TX, inv[TX])
620 cond_idle_idx[TX] = len(conds)
621 conds.append(idle_cond)
622 (rx, tx) = self.wait(conds)
623 if cond_data_idx[RX] is not None and self.matched[cond_data_idx[RX]]:
624 self.inspect_sample(RX, rx, inv[RX])
625 if cond_edge_idx[RX] is not None and self.matched[cond_edge_idx[RX]]:
626 self.inspect_edge(RX, rx, inv[RX])
627 self.inspect_idle(RX, rx, inv[RX])
628 if cond_idle_idx[RX] is not None and self.matched[cond_idle_idx[RX]]:
629 self.inspect_idle(RX, rx, inv[RX])
630 if cond_data_idx[TX] is not None and self.matched[cond_data_idx[TX]]:
631 self.inspect_sample(TX, tx, inv[TX])
632 if cond_edge_idx[TX] is not None and self.matched[cond_edge_idx[TX]]:
633 self.inspect_edge(TX, tx, inv[TX])
634 self.inspect_idle(TX, tx, inv[TX])
635 if cond_idle_idx[TX] is not None and self.matched[cond_idle_idx[TX]]:
636 self.inspect_idle(TX, tx, inv[TX])