2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
28 # Clock polarity options
29 CPOL_0 = 0 # Clock is low when inactive
30 CPOL_1 = 1 # Clock is high when inactive
33 CPHA_0 = 0 # Data is valid on the leading clock edge
34 CPHA_1 = 1 # Data is valid on the trailing clock edge
40 # Key: (CPOL, CPHA). Value: SPI mode.
51 class Decoder(srd.Decoder):
55 longname = 'Serial Peripheral Interface'
57 longdesc = '...longdesc...'
62 {'id': 'miso', 'name': 'MISO',
63 'desc': 'SPI MISO line (Master in, slave out)'},
64 {'id': 'mosi', 'name': 'MOSI',
65 'desc': 'SPI MOSI line (Master out, slave in)'},
66 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
67 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
69 optional_probes = [] # TODO
71 'cs_polarity': ['CS# polarity', ACTIVE_LOW],
72 'cpol': ['Clock polarity', CPOL_0],
73 'cpha': ['Clock phase', CPHA_0],
74 'bitorder': ['Bit order within the SPI data', MSB_FIRST],
75 'wordsize': ['Word size of SPI data', 8], # 1-64?
78 ['Hex', 'SPI data bytes in hex format'],
86 self.bytesreceived = 0
88 self.cs_was_deasserted_during_data_word = 0
90 def start(self, metadata):
91 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
92 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
95 return 'SPI: %d bytes received' % self.bytesreceived
97 def decode(self, ss, es, data):
98 # TODO: Either MISO or MOSI could be optional. CS# is optional.
99 for (samplenum, (miso, mosi, sck, cs)) in data:
101 self.samplenum += 1 # FIXME
103 # Ignore sample if the clock pin hasn't changed.
104 if sck == self.oldsck:
109 # Sample data on rising/falling clock edge (depends on mode).
110 mode = spi_mode[self.options['cpol'], self.options['cpha']]
111 if mode == 0 and sck == 0: # Sample on rising clock edge
113 elif mode == 1 and sck == 1: # Sample on falling clock edge
115 elif mode == 2 and sck == 1: # Sample on falling clock edge
117 elif mode == 3 and sck == 0: # Sample on rising clock edge
120 # If this is the first bit, save its sample number.
121 if self.bitcount == 0:
122 self.start_sample = samplenum
123 active_low = (self.options['cs_polarity'] == ACTIVE_LOW)
124 deasserted = cs if active_low else not cs
126 self.cs_was_deasserted_during_data_word = 1
128 ws = self.options['wordsize']
130 # Receive MOSI bit into our shift register.
131 if self.options['bitorder'] == MSB_FIRST:
132 self.mosidata |= mosi << (ws - 1 - self.bitcount)
134 self.mosidata |= mosi << self.bitcount
136 # Receive MISO bit into our shift register.
137 if self.options['bitorder'] == MSB_FIRST:
138 self.misodata |= miso << (ws - 1 - self.bitcount)
140 self.misodata |= miso << self.bitcount
144 # Continue to receive if not enough bits were received, yet.
145 if self.bitcount != ws:
148 self.put(self.start_sample, self.samplenum, self.out_proto,
149 ['data', self.mosidata, self.misodata])
150 self.put(self.start_sample, self.samplenum, self.out_ann,
151 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
154 if self.cs_was_deasserted_during_data_word:
155 self.put(self.start_sample, self.samplenum, self.out_ann,
156 [ANN_HEX, ['WARNING: CS# was deasserted during this '
159 # Reset decoder state.
164 # Keep stats for summary.
165 self.bytesreceived += 1