2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 import sigrokdecode as srd
23 from collections import namedtuple
25 Data = namedtuple('Data', ['ss', 'es', 'val'])
31 [<ptype>, <data1>, <data2>]
34 - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data.
35 The data is _usually_ 8 bits (but can also be fewer or more bits).
36 Both data items are Python numbers (not strings), or None if the respective
37 channel was not supplied.
38 - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
39 item, and for each of those also their respective start-/endsample numbers.
40 - 'CS-CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
41 Both data items are Python numbers (0/1), not strings. At the beginning of
42 the decoding a packet is generated with <data1> = None and <data2> being the
43 initial state of the CS# pin or None if the chip select pin is not supplied.
44 - 'TRANSFER': <data1>/<data2> contain a list of Data() namedtuples for each
45 byte transferred during this block of CS# asserted time. Each Data() has
46 fields ss, es, and val.
49 ['CS-CHANGE', None, 1]
52 ['BITS', [[1, 80, 82], [1, 83, 84], [1, 85, 86], [1, 87, 88],
53 [1, 89, 90], [1, 91, 92], [1, 93, 94], [1, 95, 96]],
54 [[0, 80, 82], [1, 83, 84], [0, 85, 86], [1, 87, 88],
55 [1, 89, 90], [1, 91, 92], [0, 93, 94], [0, 95, 96]]]
60 ['TRANSFER', [Data(ss=80, es=96, val=0xff), ...],
61 [Data(ss=80, es=96, val=0x3a), ...]]
64 # Key: (CPOL, CPHA). Value: SPI mode.
65 # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive.
66 # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge.
74 class SamplerateError(Exception):
77 class ChannelError(Exception):
80 class Decoder(srd.Decoder):
84 longname = 'Serial Peripheral Interface'
85 desc = 'Full-duplex, synchronous, serial bus.'
90 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
93 {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
94 {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
95 {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
98 {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
99 'values': ('active-low', 'active-high')},
100 {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
102 {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
104 {'id': 'bitorder', 'desc': 'Bit order',
105 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
106 {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
109 ('miso-data', 'MISO data'),
110 ('mosi-data', 'MOSI data'),
111 ('miso-bits', 'MISO bits'),
112 ('mosi-bits', 'MOSI bits'),
113 ('warnings', 'Human-readable warnings'),
116 ('miso-data', 'MISO data', (0,)),
117 ('miso-bits', 'MISO bits', (2,)),
118 ('mosi-data', 'MOSI data', (1,)),
119 ('mosi-bits', 'MOSI bits', (3,)),
120 ('other', 'Other', (4,)),
128 self.samplerate = None
131 self.misodata = self.mosidata = 0
138 self.ss_transfer = -1
139 self.cs_was_deasserted = False
142 self.have_cs = self.have_miso = self.have_mosi = None
143 self.no_cs_notification = False
145 def metadata(self, key, value):
146 if key == srd.SRD_CONF_SAMPLERATE:
147 self.samplerate = value
150 self.out_python = self.register(srd.OUTPUT_PYTHON)
151 self.out_ann = self.register(srd.OUTPUT_ANN)
152 self.out_bin = self.register(srd.OUTPUT_BINARY)
153 self.out_bitrate = self.register(srd.OUTPUT_META,
154 meta=(int, 'Bitrate', 'Bitrate during transfers'))
156 def putw(self, data):
157 self.put(self.ss_block, self.samplenum, self.out_ann, data)
160 # Pass MISO and MOSI bits and then data to the next PD up the stack.
161 so = self.misodata if self.have_miso else None
162 si = self.mosidata if self.have_mosi else None
163 so_bits = self.misobits if self.have_miso else None
164 si_bits = self.mosibits if self.have_mosi else None
167 ss, es = self.misobits[-1][1], self.misobits[0][2]
168 self.put(ss, es, self.out_bin, (0, bytes([so])))
170 ss, es = self.mosibits[-1][1], self.mosibits[0][2]
171 self.put(ss, es, self.out_bin, (1, bytes([si])))
173 self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
174 self.put(ss, es, self.out_python, ['DATA', si, so])
177 self.misobytes.append(Data(ss=ss, es=es, val=so))
179 self.mosibytes.append(Data(ss=ss, es=es, val=si))
183 for bit in self.misobits:
184 self.put(bit[1], bit[2], self.out_ann, [2, ['%d' % bit[0]]])
186 for bit in self.mosibits:
187 self.put(bit[1], bit[2], self.out_ann, [3, ['%d' % bit[0]]])
189 # Dataword annotations.
191 self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
193 self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
195 def reset_decoder_state(self):
196 self.misodata = 0 if self.have_miso else None
197 self.mosidata = 0 if self.have_mosi else None
198 self.misobits = [] if self.have_miso else None
199 self.mosibits = [] if self.have_mosi else None
202 def cs_asserted(self, cs):
203 active_low = (self.options['cs_polarity'] == 'active-low')
204 return (cs == 0) if active_low else (cs == 1)
206 def handle_bit(self, miso, mosi, clk, cs):
207 # If this is the first bit of a dataword, save its sample number.
208 if self.bitcount == 0:
209 self.ss_block = self.samplenum
210 self.cs_was_deasserted = \
211 not self.cs_asserted(cs) if self.have_cs else False
213 ws = self.options['wordsize']
215 # Receive MISO bit into our shift register.
217 if self.options['bitorder'] == 'msb-first':
218 self.misodata |= miso << (ws - 1 - self.bitcount)
220 self.misodata |= miso << self.bitcount
222 # Receive MOSI bit into our shift register.
224 if self.options['bitorder'] == 'msb-first':
225 self.mosidata |= mosi << (ws - 1 - self.bitcount)
227 self.mosidata |= mosi << self.bitcount
229 # Guesstimate the endsample for this bit (can be overridden below).
231 if self.bitcount > 0:
233 es += self.samplenum - self.misobits[0][1]
235 es += self.samplenum - self.mosibits[0][1]
238 self.misobits.insert(0, [miso, self.samplenum, es])
240 self.mosibits.insert(0, [mosi, self.samplenum, es])
242 if self.bitcount > 0 and self.have_miso:
243 self.misobits[1][2] = self.samplenum
244 if self.bitcount > 0 and self.have_mosi:
245 self.mosibits[1][2] = self.samplenum
249 # Continue to receive if not enough bits were received, yet.
250 if self.bitcount != ws:
256 elapsed = 1 / float(self.samplerate)
257 elapsed *= (self.samplenum - self.ss_block + 1)
258 bitrate = int(1 / elapsed * self.options['wordsize'])
259 self.put(self.ss_block, self.samplenum, self.out_bitrate, bitrate)
261 if self.have_cs and self.cs_was_deasserted:
262 self.putw([4, ['CS# was deasserted during this data word!']])
264 self.reset_decoder_state()
266 def find_clk_edge(self, miso, mosi, clk, cs):
267 if self.have_cs and self.oldcs != cs:
268 # Send all CS# pin value changes.
269 self.put(self.samplenum, self.samplenum, self.out_python,
270 ['CS-CHANGE', self.oldcs, cs])
273 if self.cs_asserted(cs):
274 self.ss_transfer = self.samplenum
278 self.put(self.ss_transfer, self.samplenum, self.out_python,
279 ['TRANSFER', self.mosibytes, self.misobytes])
281 # Reset decoder state when CS# changes (and the CS# pin is used).
282 self.reset_decoder_state()
284 # We only care about samples if CS# is asserted.
285 if self.have_cs and not self.cs_asserted(cs):
288 # Ignore sample if the clock pin hasn't changed.
289 if clk == self.oldclk:
294 # Sample data on rising/falling clock edge (depends on mode).
295 mode = spi_mode[self.options['cpol'], self.options['cpha']]
296 if mode == 0 and clk == 0: # Sample on rising clock edge
298 elif mode == 1 and clk == 1: # Sample on falling clock edge
300 elif mode == 2 and clk == 1: # Sample on falling clock edge
302 elif mode == 3 and clk == 0: # Sample on rising clock edge
305 # Found the correct clock edge, now get the SPI bit(s).
306 self.handle_bit(miso, mosi, clk, cs)
308 def decode(self, ss, es, data):
309 if not self.samplerate:
310 raise SamplerateError('Cannot decode without samplerate.')
311 # Either MISO or MOSI can be omitted (but not both). CS# is optional.
312 for (self.samplenum, pins) in data:
314 # Ignore identical samples early on (for performance reasons).
315 if self.oldpins == pins:
317 self.oldpins, (clk, miso, mosi, cs) = pins, pins
318 self.have_miso = (miso in (0, 1))
319 self.have_mosi = (mosi in (0, 1))
320 self.have_cs = (cs in (0, 1))
322 # Either MISO or MOSI (but not both) can be omitted.
323 if not (self.have_miso or self.have_mosi):
324 raise ChannelError('Either MISO or MOSI (or both) pins required.')
326 # Tell stacked decoders that we don't have a CS# signal.
327 if not self.no_cs_notification and not self.have_cs:
328 self.put(0, 0, self.out_python, ['CS-CHANGE', None, None])
329 self.no_cs_notification = True
331 self.find_clk_edge(miso, mosi, clk, cs)