2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # Parallel (sync) bus protocol decoder
23 import sigrokdecode as srd
26 Protocol output format:
32 - 'ITEM', [<item>, <itembitsize>]
33 - 'WORD', [<word>, <wordbitsize>, <worditemcount>]
36 - A single item (a number). It can be of arbitrary size. The max. number
37 of bits in this item is specified in <itembitsize>.
40 - The size of an item (in bits). For a 4-bit parallel bus this is 4,
41 for a 16-bit parallel bus this is 16, and so on.
44 - A single word (a number). It can be of arbitrary size. The max. number
45 of bits in this word is specified in <wordbitsize>. The (exact) number
46 of items in this word is specified in <worditemcount>.
49 - The size of a word (in bits). For a 2-item word with 8-bit items
50 <wordbitsize> is 16, for a 3-item word with 4-bit items <wordbitsize>
54 - The size of a word (in number of items). For a 4-item word (no matter
55 how many bits each item consists of) <worditemcount> is 4, for a 7-item
56 word <worditemcount> is 7, and so on.
59 def probe_list(num_probes):
61 for i in range(num_probes):
62 d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
66 class Decoder(srd.Decoder):
70 longname = 'Parallel sync bus'
71 desc = 'Generic parallel synchronous bus.'
74 outputs = ['parallel']
76 {'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'},
78 optional_probes = probe_list(8)
80 'clock_edge': ['Clock edge to sample on', 'rising'],
81 'wordsize': ['Word size of the data', 1],
82 'endianness': ['Endianness of the data', 'little'],
83 'format': ['Data format', 'hex'],
94 self.saved_item = None
97 self.ss_item = self.es_item = None
102 self.out_proto = self.register(srd.OUTPUT_PYTHON)
103 self.out_ann = self.register(srd.OUTPUT_ANN)
105 def putpb(self, data):
106 self.put(self.ss_item, self.es_item, self.out_proto, data)
108 def putb(self, data):
109 self.put(self.ss_item, self.es_item, self.out_ann, data)
111 def putpw(self, data):
112 self.put(self.ss_word, self.es_word, self.out_proto, data)
114 def putw(self, data):
115 self.put(self.ss_word, self.es_word, self.out_ann, data)
117 def handle_bits(self, datapins):
118 # If this is the first item in a word, save its sample number.
119 if self.itemcount == 0:
120 self.ss_word = self.samplenum
122 # Get the bits for this item.
123 item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00')
124 for i in range(used_pins):
125 item |= datapins[i] << i
127 self.items.append(item)
130 if self.first == True:
131 # Save the start sample and item for later (no output yet).
132 self.ss_item = self.samplenum
134 self.saved_item = item
136 # Output the saved item (from the last CLK edge to the current).
137 self.es_item = self.samplenum
138 self.putpb(['ITEM', self.saved_item])
139 self.putb([0, ['%X' % self.saved_item]])
140 self.ss_item = self.samplenum
141 self.saved_item = item
143 endian, ws = self.options['endianness'], self.options['wordsize']
145 # Get as many items as the configured wordsize says.
146 if self.itemcount < ws:
149 # Output annotations/proto for a word (a collection of items).
152 if endian == 'little':
153 word |= self.items[i] << ((ws - 1 - i) * used_pins)
154 elif endian == 'big':
155 word |= self.items[i] << (i * used_pins)
157 self.es_word = self.samplenum
158 # self.putpw(['WORD', word])
159 # self.putw([1, ['%X' % word]])
160 self.ss_word = self.samplenum
162 self.itemcount, self.items = 0, []
164 def find_clk_edge(self, clk, datapins):
165 # Ignore sample if the clock pin hasn't changed.
166 if clk == self.oldclk:
170 # Sample data on rising/falling clock edge (depends on config).
171 c = self.options['clock_edge']
172 if c == 'rising' and clk == 0: # Sample on rising clock edge.
174 elif c == 'falling' and clk == 1: # Sample on falling clock edge.
177 # Found the correct clock edge, now get the bits.
178 self.handle_bits(datapins)
180 def decode(self, ss, es, data):
181 for (self.samplenum, pins) in data:
183 # Ignore identical samples early on (for performance reasons).
184 if self.oldpins == pins:
189 if self.state == 'IDLE':
190 self.find_clk_edge(pins[0], pins[1:])
192 raise Exception('Invalid state: %s' % self.state)