2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
30 - 'ITEM', [<item>, <itembitsize>]
31 - 'WORD', [<word>, <wordbitsize>, <worditemcount>]
34 - A single item (a number). It can be of arbitrary size. The max. number
35 of bits in this item is specified in <itembitsize>.
38 - The size of an item (in bits). For a 4-bit parallel bus this is 4,
39 for a 16-bit parallel bus this is 16, and so on.
42 - A single word (a number). It can be of arbitrary size. The max. number
43 of bits in this word is specified in <wordbitsize>. The (exact) number
44 of items in this word is specified in <worditemcount>.
47 - The size of a word (in bits). For a 2-item word with 8-bit items
48 <wordbitsize> is 16, for a 3-item word with 4-bit items <wordbitsize>
52 - The size of a word (in number of items). For a 4-item word (no matter
53 how many bits each item consists of) <worditemcount> is 4, for a 7-item
54 word <worditemcount> is 7, and so on.
57 def probe_list(num_probes):
58 l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
59 for i in range(num_probes):
60 d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
64 class Decoder(srd.Decoder):
68 longname = 'Parallel sync bus'
69 desc = 'Generic parallel synchronous bus.'
72 outputs = ['parallel']
73 optional_probes = probe_list(8)
75 {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
76 'default': 'rising', 'values': ('rising', 'falling')},
77 {'id': 'wordsize', 'desc': 'Word size of the data',
79 {'id': 'endianness', 'desc': 'Endianness of the data',
80 'default': 'little', 'values': ('little', 'big')},
91 self.saved_item = None
94 self.ss_item = self.es_item = None
99 self.out_python = self.register(srd.OUTPUT_PYTHON)
100 self.out_ann = self.register(srd.OUTPUT_ANN)
102 def putpb(self, data):
103 self.put(self.ss_item, self.es_item, self.out_python, data)
105 def putb(self, data):
106 self.put(self.ss_item, self.es_item, self.out_ann, data)
108 def putpw(self, data):
109 self.put(self.ss_word, self.es_word, self.out_python, data)
111 def putw(self, data):
112 self.put(self.ss_word, self.es_word, self.out_ann, data)
114 def handle_bits(self, datapins):
115 # If this is the first item in a word, save its sample number.
116 if self.itemcount == 0:
117 self.ss_word = self.samplenum
119 # Get the bits for this item.
120 item, used_pins = 0, datapins.count(b'\x01') + datapins.count(b'\x00')
121 for i in range(used_pins):
122 item |= datapins[i] << i
124 self.items.append(item)
127 if self.first == True:
128 # Save the start sample and item for later (no output yet).
129 self.ss_item = self.samplenum
131 self.saved_item = item
133 # Output the saved item (from the last CLK edge to the current).
134 self.es_item = self.samplenum
135 self.putpb(['ITEM', self.saved_item])
136 self.putb([0, ['%X' % self.saved_item]])
137 self.ss_item = self.samplenum
138 self.saved_item = item
140 endian, ws = self.options['endianness'], self.options['wordsize']
142 # Get as many items as the configured wordsize says.
143 if self.itemcount < ws:
146 # Output annotations/python for a word (a collection of items).
149 if endian == 'little':
150 word |= self.items[i] << ((ws - 1 - i) * used_pins)
151 elif endian == 'big':
152 word |= self.items[i] << (i * used_pins)
154 self.es_word = self.samplenum
155 # self.putpw(['WORD', word])
156 # self.putw([1, ['%X' % word]])
157 self.ss_word = self.samplenum
159 self.itemcount, self.items = 0, []
161 def find_clk_edge(self, clk, datapins):
162 # Ignore sample if the clock pin hasn't changed.
163 if clk == self.oldclk:
167 # Sample data on rising/falling clock edge (depends on config).
168 c = self.options['clock_edge']
169 if c == 'rising' and clk == 0: # Sample on rising clock edge.
171 elif c == 'falling' and clk == 1: # Sample on falling clock edge.
174 # Found the correct clock edge, now get the bits.
175 self.handle_bits(datapins)
177 def decode(self, ss, es, data):
178 for (self.samplenum, pins) in data:
180 # Ignore identical samples early on (for performance reasons).
181 if self.oldpins == pins:
186 if self.state == 'IDLE':
187 if pins[0] not in (0, 1):
188 self.handle_bits(pins[1:])
190 self.find_clk_edge(pins[0], pins[1:])
192 raise Exception('Invalid state: %s' % self.state)