2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2011-2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # 1-Wire protocol decoder
23 import sigrokdecode as srd
25 # Annotation feed formats
32 class Decoder(srd.Decoder):
37 desc = '1-Wire bus and MicroLan'
42 {'id': 'owr', 'name': 'OWR', 'desc': '1-Wire bus'},
45 {'id': 'pwr', 'name': 'PWR', 'desc': '1-Wire power'},
48 'overdrive': ['Overdrive', 0],
51 ['ASCII', 'Data bytes as ASCII characters'],
52 ['Decimal', 'Databytes as decimal, integer values'],
53 ['Hex', 'Data bytes in hex format'],
54 ['Octal', 'Data bytes as octal numbers'],
55 ['Bits', 'Data bytes in bit notation (sequence of 0/1 digits)'],
58 def __init__(self, **kwargs):
61 # Link layer variables
62 self.lnk_state = 'WAIT FOR FALLING EDGE'
63 self.lnk_event = 'NONE'
67 # Network layer variables
68 self.net_state = 'WAIT FOR COMMAND'
69 self.net_event = 'NONE'
72 # Transport layer variables
73 self.trn_state = 'WAIT FOR EVENT'
74 self.trn_event = 'NONE'
76 def start(self, metadata):
77 self.samplerate = metadata['samplerate']
78 self.out_proto = self.add(srd.OUTPUT_PROTO, 'onewire')
79 self.out_ann = self.add(srd.OUTPUT_ANN , 'onewire')
81 # The width of the 1-Wire time base (30us) in number of samples.
82 # TODO: optimize this value
83 self.time_base = float(self.samplerate) * float(0.000030)
84 print ("DEBUG: samplerate = %d, time_base = %d" % (self.samplerate, self.time_base))
89 def decode(self, ss, es, data):
90 for (self.samplenum, (owr, pwr)) in data:
91 # print ("DEBUG: sample = %d, owr = %d, pwr = %d, lnk_fall = %d, lnk_state = %s" % (self.samplenum, owr, pwr, self.lnk_fall, self.lnk_state))
96 self.lnk_event = "NONE"
98 if self.lnk_state == 'WAIT FOR FALLING EDGE':
99 # The start of a cycle is a falling edge.
101 # Save the sample number for the falling edge.
102 self.lnk_fall = self.samplenum
103 # Go to waiting for sample time
104 self.lnk_state = 'WAIT FOR DATA SAMPLE'
105 self.put(self.lnk_fall, self.samplenum, self.out_ann,
106 [ANN_DEC, ['LNK: NEGEDGE: ']])
107 print ("DEBUG: NEGEDGE t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
108 elif self.lnk_state == 'WAIT FOR DATA SAMPLE':
109 # Data should be sample one 'time unit' after a falling edge
110 if (self.samplenum - self.lnk_fall == 1*self.time_base):
111 self.lnk_bit = owr & 0x1
112 self.lnk_event = "DATA BIT"
113 if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
114 else : self.lnk_state = 'WAIT FOR RISING EDGE'
115 self.put(self.lnk_fall, self.samplenum, self.out_ann,
116 [ANN_DEC, ['LNK: BIT: ' + str(self.lnk_bit)]])
117 print ("DEBUG: BIT=%d t0=%d t+=%d" % (self.lnk_bit, self.lnk_fall, self.samplenum))
118 elif self.lnk_state == 'WAIT FOR RISING EDGE':
119 # The end of a cycle is a rising edge.
121 # A reset cycle is longer than 8T.
122 if (self.samplenum - self.lnk_fall > 8*self.time_base):
123 # Save the sample number for the falling edge.
124 self.lnk_rise = self.samplenum
125 # Send a reset event to the next protocol layer.
126 self.lnk_event = "RESET"
127 self.lnk_state = "WAIT FOR PRESENCE DETECT"
128 self.put(self.lnk_fall, self.samplenum, self.out_proto,
130 self.put(self.lnk_fall, self.samplenum, self.out_ann,
131 [ANN_DEC, ['LNK: RESET: ']])
132 print ("DEBUG: RESET t0=%d t+=%d" % (self.lnk_fall, self.samplenum))
134 self.lnk_fall = self.samplenum
135 # Otherwise this is assumed to be a data bit.
137 self.lnk_state = "WAIT FOR FALLING EDGE"
138 elif self.lnk_state == 'WAIT FOR PRESENCE DETECT':
139 # Data should be sample one 'time unit' after a falling edge
140 if (self.samplenum - self.lnk_rise == 2.5*self.time_base):
141 self.lnk_present = owr & 0x1
142 #self.lnk_event = "PRESENCE DETECT"
143 if (self.lnk_bit) : self.lnk_state = 'WAIT FOR FALLING EDGE'
144 else : self.lnk_state = 'WAIT FOR RISING EDGE'
145 self.put(self.lnk_fall, self.samplenum, self.out_ann,
146 [ANN_DEC, ['LNK: PRESENCE: ' + str(self.lnk_present)]])
147 print ("DEBUG: PRESENCE=%d t0=%d t+=%d" % (self.lnk_present, self.lnk_fall, self.samplenum))
149 raise Exception('Invalid lnk_state: %d' % self.lnk_state)
154 self.net_event = "RESET"
156 if (self.lnk_event == "RESET"):
157 self.net_state = "WAIT FOR COMMAND"
160 elif (self.lnk_event == "DATA BIT"):
161 if (self.net_state == "WAIT FOR COMMAND"):
162 self.net_cnt = self.net_cnt + 1
163 self.net_cmd = (self.net_cmd << 1) & self.lnk_bit
164 if (self.net_cnt == 8):
165 self.put(self.lnk_fall, self.samplenum,
166 self.out_proto, ['LNK: COMMAND', self.net_cmd])
167 self.put(self.lnk_fall, self.samplenum, self.out_ann,
168 [ANN_DEC, ['LNK: COMMAND: ' + self.net_cmd]])
169 if (self.net_cmd == 0x33):
172 elif (self.net_cmd == 0x0f):
175 elif (self.net_cmd == 0xcc):
178 elif (self.net_cmd == 0x55):
181 elif (self.net_cmd == 0xf0):
184 elif (self.net_cmd == 0x3c):
187 elif (self.net_cmd == 0x69):
188 # OVERDRIVE MATCH ROM
191 elif (self.net_state == "WAIT FOR ROM"):
195 raise Exception('Invalid net_state: %d' % self.net_state)
196 elif not (self.lnk_event == "NONE"):
197 raise Exception('Invalid lnk_event: %s' % self.lnk_event)
200 # if (self.samplenum == self.lnk_start + 8*self.time_base):
201 # self.put(self.lnk_fall, self.samplenum - 1, self.out_proto, ['RESET'])