2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
23 # Definitions of various bits in MXC6225XU registers.
32 # ORI[1:0] and OR[1:0] (same format)
34 0b00: 'vertical in upright orientation',
35 0b01: 'rotated 90 degrees clockwise',
36 0b10: 'vertical in inverted orientation',
37 0b11: 'rotated 90 degrees counterclockwise',
62 class Decoder(srd.Decoder):
66 longname = 'MEMSIC MXC6225XU'
67 desc = 'Digital Thermal Orientation Sensor (DTOS) protocol.'
70 outputs = ['mxc6225xu']
72 ('text', 'Human-readable text'),
75 def __init__(self, **kwargs):
79 self.out_ann = self.register(srd.OUTPUT_ANN)
82 self.put(self.ss, self.es, self.out_ann, data)
84 def handle_reg_0x00(self, b):
85 # XOUT: 8-bit x-axis acceleration output.
86 # Data is in 2's complement, values range from -128 to 127.
87 self.putx([0, ['XOUT: %d' % b]])
89 def handle_reg_0x01(self, b):
90 # YOUT: 8-bit y-axis acceleration output.
91 # Data is in 2's complement, values range from -128 to 127.
92 self.putx([0, ['YOUT: %d' % b]])
94 def handle_reg_0x02(self, b):
95 # STATUS: Orientation and shake status.
98 int_val = (b >> 7) & 1
99 s = 'unchanged and no' if (int_val == 0) else 'changed or'
100 ann = 'INT = %d: Orientation %s shake event occured\n' % (int_val, s)
103 sh = (((b >> 6) & 1) << 1) | ((b >> 5) & 1)
104 ann += 'SH[1:0] = %s: Shake event: %s\n' % \
105 (bin(sh)[2:], status['sh'][sh])
109 s = '' if (tilt == 0) else 'not '
110 ann += 'TILT = %d: Orientation measurement is %svalid\n' % (tilt, s)
112 # Bits[3:2]: ORI[1:0]
113 ori = (((b >> 3) & 1) << 1) | ((b >> 2) & 1)
114 ann += 'ORI[1:0] = %s: %s\n' % (bin(ori)[2:], status['ori'][ori])
117 or_val = (((b >> 1) & 1) << 1) | ((b >> 0) & 1)
118 ann += 'OR[1:0] = %s: %s\n' % (bin(or_val)[2:], status['ori'][or_val])
120 # ann += 'b = %s\n' % (bin(b))
122 self.putx([0, [ann]])
124 def handle_reg_0x03(self, b):
125 # DETECTION: Powerdown, orientation and shake detection parameters.
126 # Note: This is a write-only register.
130 s = 'Do not power down' if (pd == 0) else 'Power down'
131 ann = 'PD = %d: %s the device (into a low-power state)\n' % (pd, s)
135 ann = 'SHM = %d: Set shake mode to %d\n' % (shm, shm)
137 # Bits[5:4]: SHTH[1:0]
138 shth = (((b >> 5) & 1) << 1) | ((b >> 4) & 1)
139 ann += 'SHTH[1:0] = %s: Set shake threshold to %s\n' \
140 % (bin(shth)[2:], status['shth'][shth])
142 # Bits[3:2]: SHC[1:0]
143 shc = (((b >> 3) & 1) << 1) | ((b >> 2) & 1)
144 ann += 'SHC[1:0] = %s: Set shake count to %s readings\n' \
145 % (bin(shc)[2:], status['shc'][shc])
147 # Bits[1:0]: ORC[1:0]
148 orc = (((b >> 1) & 1) << 1) | ((b >> 0) & 1)
149 ann += 'ORC[1:0] = %s: Set orientation count to %s readings\n' \
150 % (bin(orc)[2:], status['orc'][orc])
152 self.putx([0, [ann]])
154 # TODO: Fixup, this is copy-pasted from another PD.
155 # TODO: Handle/check the ACKs/NACKs.
156 def decode(self, ss, es, data):
159 # Store the start/end samples of this I²C packet.
160 self.ss, self.es = ss, es
163 if self.state == 'IDLE':
164 # Wait for an I²C START condition.
167 self.state = 'GET SLAVE ADDR'
168 self.block_start_sample = ss
169 elif self.state == 'GET SLAVE ADDR':
170 # Wait for an address write operation.
171 # TODO: We should only handle packets to the slave(?)
172 if cmd != 'ADDRESS WRITE':
174 self.state = 'GET REG ADDR'
175 elif self.state == 'GET REG ADDR':
176 # Wait for a data write (master selects the slave register).
177 if cmd != 'DATA WRITE':
180 self.state = 'WRITE REGS'
181 elif self.state == 'WRITE REGS':
182 # If we see a Repeated Start here, it's a multi-byte read.
183 if cmd == 'START REPEAT':
184 self.state = 'READ REGS'
186 # Otherwise: Get data bytes until a STOP condition occurs.
187 if cmd == 'DATA WRITE':
188 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
191 # TODO: Check for NACK!
197 elif self.state == 'READ REGS':
198 # Wait for an address read operation.
199 # TODO: We should only handle packets to the slave(?)
200 if cmd == 'ADDRESS READ':
201 self.state = 'READ REGS2'
205 elif self.state == 'READ REGS2':
206 if cmd == 'DATA READ':
207 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
210 # TODO: Check for NACK!