2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2018 fenugrec <fenugrec@users.sourceforge.net>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
22 class ChannelError(Exception):
25 class Decoder(srd.Decoder):
29 longname = 'Intel MCS-48'
30 desc = 'Intel MCS-48 external memory access protocol.'
35 {'id': 'ale', 'name': 'ALE', 'desc': 'Address latch enable'},
36 {'id': 'psen', 'name': '/PSEN', 'desc': 'Program store enable'},
40 'desc': 'CPU data line %d' % i
41 } for i in range(0, 8)
45 'desc': 'CPU address line %d' % i
46 } for i in range(8, 12)
48 optional_channels = tuple({
51 'desc': 'CPU address line %d' % i
52 } for i in range(12, 13)
55 ('romdata', 'Address:Data'),
58 ('romdata', 'AAAA:DD'),
60 OFF_ALE, OFF_PSEN = 0, 1
61 OFF_DATA_BOT, OFF_DATA_TOP = 2, 10
62 OFF_ADDR_BOT, OFF_ADDR_TOP = 10, 14
63 OFF_BANK_BOT, OFF_BANK_TOP = 14, 15
74 # Flag to make sure we get an ALE pulse first.
78 self.out_ann = self.register(srd.OUTPUT_ANN)
79 self.out_bin = self.register(srd.OUTPUT_BINARY)
81 def newaddr(self, addr, data):
82 # Falling edge on ALE: reconstruct address.
84 addr = sum([bit << i for i, bit in enumerate(addr)])
86 addr |= sum([bit << i for i, bit in enumerate(data)])
88 self.addr_s = self.samplenum
90 def newdata(self, data):
91 # Edge on PSEN: get data.
92 data = sum([bit << i for i, bit in enumerate(data)])
94 self.data_s = self.samplenum
96 anntext = '{:04X}:{:02X}'.format(self.addr, self.data)
97 self.put(self.addr_s, self.data_s, self.out_ann, [0, [anntext]])
98 bindata = self.addr.to_bytes(2, byteorder='big')
99 bindata += self.data.to_bytes(1, byteorder='big')
100 self.put(self.addr_s, self.data_s, self.out_bin, [0, bindata])
103 # Address bits above A11 are optional, and are considered to be A12+.
104 # This logic needs more adjustment when more bank address pins are
105 # to get supported. For now, having just A12 is considered sufficient.
106 has_bank = self.has_channel(self.OFF_BANK_BOT)
107 bank_pin_count = 1 if has_bank else 0
108 # Sample address on the falling ALE edge.
109 # Save data on falling edge of PSEN.
111 pins = self.wait([{self.OFF_ALE: 'f'}, {self.OFF_PSEN: 'r'}])
112 data = pins[self.OFF_DATA_BOT:self.OFF_DATA_TOP]
113 addr = pins[self.OFF_ADDR_BOT:self.OFF_ADDR_TOP]
114 bank = pins[self.OFF_BANK_BOT:self.OFF_BANK_TOP]
116 addr += bank[:bank_pin_count]
117 # Handle those conditions (one or more) that matched this time.
119 self.newaddr(addr, data)