2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
25 # START field (indicates start or stop of a transaction)
27 0b0000: 'Start of cycle for a target',
29 0b0010: 'Grant for bus master 0',
30 0b0011: 'Grant for bus master 1',
40 0b1101: 'Start of cycle for a Firmware Memory Read cycle',
41 0b1110: 'Start of cycle for a Firmware Memory Write cycle',
42 0b1111: 'Stop/abort (end of a cycle for a target)',
44 # Cycle type / direction field
45 # Bit 0 (LAD[0]) is unused, should always be 0.
46 # Neither host nor peripheral are allowed to drive 0b11x0.
50 0b0100: 'Memory read',
51 0b0110: 'Memory write',
54 0b1100: 'Reserved / not allowed',
55 0b1110: 'Reserved / not allowed',
57 # SIZE field (determines how many bytes are to be transferred)
58 # Bits[3:2] are reserved, must be driven to 0b00.
59 # Neither host nor peripheral are allowed to drive 0b0010.
61 0b0000: '8 bits (1 byte)',
62 0b0001: '16 bits (2 bytes)',
63 0b0010: 'Reserved / not allowed',
64 0b0011: '32 bits (4 bytes)',
66 # CHANNEL field (bits[2:0] contain the DMA channel number)
77 # SYNC field (used to add wait states)
88 0b1001: 'Ready more (DMA only)',
98 class Decoder(srd.Decoder):
102 longname = 'Low-Pin-Count'
103 desc = 'Protocol for low-bandwidth devices on PC mainboards.'
108 {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
109 {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'},
110 {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'},
111 {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'},
112 {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'},
113 {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'},
116 {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
117 {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'},
118 {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'},
119 {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
120 {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'},
121 {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'},
122 {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'},
126 ['warnings', 'Warnings'],
128 ['cycle-type', 'Cycle-type/direction'],
130 ['tar1', 'Turn-around cycle 1'],
133 ['tar2', 'Turn-around cycle 2'],
136 def __init__(self, **kwargs):
149 self.ss_block = self.es_block = None
152 # self.out_proto = self.register(srd.OUTPUT_PYTHON)
153 self.out_ann = self.register(srd.OUTPUT_ANN)
155 def putb(self, data):
156 self.put(self.ss_block, self.es_block, self.out_ann, data)
158 def handle_get_start(self, lad, lad_bits, lframe):
159 # LAD[3:0]: START field (1 clock cycle).
161 # The last value of LAD[3:0] before LFRAME# gets de-asserted is what
162 # the peripherals must use. However, the host can keep LFRAME# asserted
163 # multiple clocks, and we output all START fields that occur, even
164 # though the peripherals are supposed to ignore all but the last one.
165 self.es_block = self.samplenum
166 self.putb([1, [fields['START'][lad], 'START', 'St', 'S']])
167 self.ss_block = self.samplenum
169 # Output a warning if LAD[3:0] changes while LFRAME# is low.
171 if (self.lad != -1 and self.lad != lad):
172 self.putb([0, ['LAD[3:0] changed while LFRAME# was asserted']])
174 # LFRAME# is asserted (low). Wait until it gets de-asserted again
175 # (the host is allowed to keep it asserted multiple clocks).
179 self.start_field = self.lad
180 self.state = 'GET CT/DR'
182 def handle_get_ct_dr(self, lad, lad_bits):
183 # LAD[3:0]: Cycle type / direction field (1 clock cycle).
185 self.cycle_type = fields['CT_DR'][lad]
187 # TODO: Warning/error on invalid cycle types.
188 if self.cycle_type == 'Reserved':
189 self.putb([0, ['Invalid cycle type (%s)' % lad_bits]])
191 self.es_block = self.samplenum
192 self.putb([2, ['Cycle type: %s' % self.cycle_type]])
193 self.ss_block = self.samplenum
195 self.state = 'GET ADDR'
199 def handle_get_addr(self, lad, lad_bits):
200 # LAD[3:0]: ADDR field (4/8/0 clock cycles).
202 # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
203 # DMA cycles: no ADDR clocks at all.
204 if self.cycle_type in ('I/O read', 'I/O write'):
205 addr_nibbles = 4 # Address is 16bits.
206 elif self.cycle_type in ('Memory read', 'Memory write'):
207 addr_nibbles = 8 # Address is 32bits.
209 addr_nibbles = 0 # TODO: How to handle later on?
211 # Addresses are driven MSN-first.
212 offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
213 self.addr |= (lad << offset)
215 # Continue if we haven't seen all ADDR cycles, yet.
216 if (self.cur_nibble < addr_nibbles - 1):
220 self.es_block = self.samplenum
221 s = 'Address: 0x%%0%dx' % addr_nibbles
222 self.putb([3, [s % self.addr]])
223 self.ss_block = self.samplenum
225 self.state = 'GET TAR'
228 def handle_get_tar(self, lad, lad_bits):
229 # LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
231 self.es_block = self.samplenum
232 self.putb([4, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
233 self.ss_block = self.samplenum
235 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
236 # either the host or peripheral. On the second clock cycle,
237 # the host or peripheral tri-states LAD[3:0], but its value
238 # should still be 1111, due to pull-ups on the LAD lines.
239 if lad_bits != '1111':
240 self.putb([0, ['TAR, cycle %d: %s (expected 1111)' % \
241 (self.tarcount, lad_bits)]])
243 if (self.tarcount != 1):
248 self.state = 'GET SYNC'
250 def handle_get_sync(self, lad, lad_bits):
251 # LAD[3:0]: SYNC field (1-n clock cycles).
253 self.sync_val = lad_bits
254 self.cycle_type = fields['SYNC'][lad]
256 # TODO: Warnings if reserved value are seen?
257 if self.cycle_type == 'Reserved':
258 self.putb([0, ['SYNC, cycle %d: %s (reserved value)' % \
259 (self.synccount, self.sync_val)]])
261 self.es_block = self.samplenum
262 self.putb([5, ['SYNC, cycle %d: %s' % (self.synccount, self.sync_val)]])
263 self.ss_block = self.samplenum
268 self.state = 'GET DATA'
270 def handle_get_data(self, lad, lad_bits):
271 # LAD[3:0]: DATA field (2 clock cycles).
273 # Data is driven LSN-first.
274 if (self.cycle_count == 0):
276 elif (self.cycle_count == 1):
277 self.databyte |= (lad << 4)
279 raise Exception('Invalid cycle_count: %d' % self.cycle_count)
281 if (self.cycle_count != 1):
282 self.cycle_count += 1
285 self.es_block = self.samplenum
286 self.putb([6, ['DATA: 0x%02x' % self.databyte]])
287 self.ss_block = self.samplenum
290 self.state = 'GET TAR2'
292 def handle_get_tar2(self, lad, lad_bits):
293 # LAD[3:0]: Second TAR field (2 clock cycles).
295 self.es_block = self.samplenum
296 self.putb([7, ['TAR, cycle %d: %s' % (self.tarcount, lad_bits)]])
297 self.ss_block = self.samplenum
299 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
300 # either the host or peripheral. On the second clock cycle,
301 # the host or peripheral tri-states LAD[3:0], but its value
302 # should still be 1111, due to pull-ups on the LAD lines.
303 if lad_bits != '1111':
304 self.putb([0, ['Warning: TAR, cycle %d: %s (expected 1111)'
305 % (self.tarcount, lad_bits)]])
307 if (self.tarcount != 1):
314 def decode(self, ss, es, data):
315 for (self.samplenum, pins) in data:
317 # If none of the pins changed, there's nothing to do.
318 if self.oldpins == pins:
321 # Store current pin values for the next round.
324 # Get individual pin values into local variables.
325 (lframe, lclk, lad0, lad1, lad2, lad3) = pins[:6]
326 (lreset, ldrq, serirq, clkrun, lpme, lpcpd, lsmi) = pins[6:]
328 # Only look at the signals upon rising LCLK edges. The LPC clock
329 # is the same as the PCI clock (which is sampled at rising edges).
330 if not (self.oldlclk == 0 and lclk == 1):
334 # Store LAD[3:0] bit values (one nibble) in local variables.
335 # Most (but not all) states need this.
336 if self.state != 'IDLE':
337 lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
338 lad_bits = bin(lad)[2:].zfill(4)
339 # self.putb([0, ['LAD: %s' % lad_bits]])
341 # TODO: Only memory read/write is currently supported/tested.
344 if self.state == 'IDLE':
345 # A valid LPC cycle starts with LFRAME# being asserted (low).
348 self.ss_block = self.samplenum
349 self.state = 'GET START'
352 elif self.state == 'GET START':
353 self.handle_get_start(lad, lad_bits, lframe)
354 elif self.state == 'GET CT/DR':
355 self.handle_get_ct_dr(lad, lad_bits)
356 elif self.state == 'GET ADDR':
357 self.handle_get_addr(lad, lad_bits)
358 elif self.state == 'GET TAR':
359 self.handle_get_tar(lad, lad_bits)
360 elif self.state == 'GET SYNC':
361 self.handle_get_sync(lad, lad_bits)
362 elif self.state == 'GET DATA':
363 self.handle_get_data(lad, lad_bits)
364 elif self.state == 'GET TAR2':
365 self.handle_get_tar2(lad, lad_bits)
367 raise Exception('Invalid state: %s' % self.state)