2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # ST STM32 JTAG protocol decoder
23 import sigrokdecode as srd
25 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
26 # Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
27 # as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
28 # Instead, BYPASS is decoded for any of these instructions.
30 '1111': ['BYPASS', 1], # Bypass register
31 '1110': ['IDCODE', 32], # ID code register
32 '1010': ['DPACC', 35], # Debug port access register
33 '1011': ['APACC', 35], # Access port access register
34 '1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
37 # ARM Cortex-M3 r1p1-01rel0 ID code
38 cm3_idcode = 0x3ba00477
40 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
42 0x06412041: 'Low-density device, rev. A',
43 0x06410041: 'Medium-density device, rev. A',
44 0x16410041: 'Medium-density device, rev. B/Z/Y',
45 0x06414041: 'High-density device, rev. A/Z/Y',
46 0x06430041: 'XL-density device, rev. A',
47 0x06418041: 'Connectivity-line device, rev. A/Z',
50 # ACK[2:0] in the DPACC/APACC registers
62 # 32bit debug port registers (addressed via A[3:2])
64 '00': 'Reserved', # Must be kept at reset value
70 # TODO: All start/end sample values in self.put() calls are bogus.
72 # Bits[31:28]: Version (here: 0x3)
73 # JTAG-DP: 0x3, SW-DP: 0x2
74 # Bits[27:12]: Part number (here: 0xba00)
75 # JTAG-DP: 0xba00, SW-DP: 0xba10
76 # Bits[11:1]: JEDEC (JEP-106) manufacturer ID (here: 0x23b)
77 # Bits[11:8]: Continuation code ('ARM Limited': 0x04)
78 # Bits[7:1]: Identity code ('ARM Limited': 0x3b)
79 # Bits[0:0]: Reserved (here: 0x1)
80 def decode_device_id_code(bits):
81 id_hex = '0x%x' % int('0b' + bits, 2)
82 ver = '0x%x' % int('0b' + bits[-32:-28], 2)
83 part = '0x%x' % int('0b' + bits[-28:-12], 2)
84 manuf = '0x%x' % int('0b' + bits[-12:-1], 2)
85 res = '0x%x' % int('0b' + bits[-1], 2)
86 return (id_hex, ver, part, manuf, res)
88 class Decoder(srd.Decoder):
92 longname = 'Joint Test Action Group / ST STM32'
93 desc = 'ST STM32-specific JTAG protocol.'
96 outputs = ['jtag_stm32']
101 ['Text', 'Human-readable text'],
104 def __init__(self, **kwargs):
106 # self.state = 'BYPASS'
108 def start(self, metadata):
109 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
110 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
115 def handle_reg_bypass(self, bits):
117 self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])
119 def handle_reg_idcode(self, bits):
121 self.put(self.ss, self.es, self.out_ann,
122 [0, ['IDCODE: %s (ver=%s, part=%s, manuf=%s, res=%s)' % \
123 decode_device_id_code(bits)]])
125 # When transferring data IN:
126 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
127 # Bits[2:1] = A[3:2]: 2-bit address of a debug port register
128 # Bits[0:0] = RnW: Read request (1) or write request (0)
129 # When transferring data OUT:
130 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
131 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
132 def handle_reg_dpacc(self, bits):
133 self.put(self.ss, self.es, self.out_ann, [0, ['DPACC: ' + bits]])
135 # TODO: When to use Data IN / Data OUT?
138 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
139 data_hex = '0x%x' % int('0b' + data, 2)
140 r = 'Read request' if (rnw == '1') else 'Write request'
141 s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
142 self.put(self.ss, self.es, self.out_ann, [0, [s]])
145 data, ack = bits[:-3], bits[-3:]
146 data_hex = '0x%x' % int('0b' + data, 2)
147 ack_meaning = ack_val[ack]
148 s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
149 self.put(self.ss, self.es, self.out_ann, [0, [s]])
151 # When transferring data IN:
152 # Bits[34:3] = DATA[31:0]: 32bit data to shift in (write request)
153 # Bits[2:1] = A[3:2]: 2-bit address (sub-address AP register)
154 # Bits[0:0] = RnW: Read request (1) or write request (0)
155 # When transferring data OUT:
156 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
157 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
158 def handle_reg_apacc(self, bits):
159 self.put(self.ss, self.es, self.out_ann, [0, ['APACC: ' + bits]])
161 # TODO: When to use Data IN / Data OUT?
164 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
165 data_hex = '0x%x' % int('0b' + data, 2)
166 r = 'Read request' if (rnw == '1') else 'Write request'
167 s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
168 self.put(self.ss, self.es, self.out_ann, [0, [s]])
171 data, ack = bits[:-3], bits[-3:]
172 data_hex = '0x%x' % int('0b' + data, 2)
173 ack_meaning = ack_val[ack]
174 s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
175 self.put(self.ss, self.es, self.out_ann, [0, [s]])
177 def handle_reg_abort(self, bits):
178 # Bits[31:1]: reserved. Bit[0]: DAPABORT.
179 a = '' if (bits[0] == '1') else 'No '
180 s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
181 self.put(self.ss, self.es, self.out_ann, [0, [s]])
183 # Warn if DAPABORT[31:1] contains non-zero bits.
184 if (bits[:-1] != ('0' * 31)):
185 self.put(self.ss, self.es, self.out_ann,
186 [0, ['WARNING: DAPABORT[31:1] reserved!']])
188 def handle_reg_unknown(self, bits):
189 self.put(self.ss, self.es, self.out_ann,
190 [0, ['Unknown instruction: ' % bits]]) # TODO
192 def decode(self, ss, es, data):
193 # Assumption: The right-most char in the 'val' bitstring is the LSB.
196 self.ss, self.es = ss, es
198 # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
201 if self.state == 'IDLE':
202 # Wait until a new instruction is shifted into the IR register.
205 # Switch to the state named after the instruction, or 'UNKNOWN'.
206 self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
207 self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
208 elif self.state in ('BYPASS'):
209 # In these states we're interested in incoming bits (TDI).
212 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
215 elif self.state in ('IDCODE', 'DPACC', 'APACC', 'ABORT', 'UNKNOWN'):
216 # In these states we're interested in outgoing bits (TDO).
218 # if cmd not in ('DR TDI', 'DR TDO'):
220 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
224 raise Exception('Invalid state: %s' % self.state)