2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # ST STM32 JTAG protocol decoder
23 import sigrokdecode as srd
25 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
27 '1111': ['BYPASS', 1], # Bypass register
28 '1110': ['IDCODE', 32], # ID code register
29 '1010': ['DPACC', 35], # Debug port access register
30 '1011': ['APACC', 35], # Access port access register
31 '1000': ['ABORT', 35], # Abort register # TODO: 32 bits? Datasheet typo?
34 # ARM Cortex-M3 r1p1-01rel0 ID code
35 cm3_idcode = 0x3ba00477
37 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
39 0x06412041: 'Low-density device, rev. A',
40 0x06410041: 'Medium-density device, rev. A',
41 0x16410041: 'Medium-density device, rev. B/Z/Y',
42 0x06414041: 'High-density device, rev. A/Z/Y',
43 0x06430041: 'XL-density device, rev. A',
44 0x06418041: 'Connectivity-line device, rev. A/Z',
47 # ACK[2:0] in the DPACC/APACC registers
59 # 32bit debug port registers (addressed via A[3:2])
61 '00': 'Reserved', # Must be kept at reset value
67 # TODO: All start/end sample values in self.put() calls are bogus.
69 class Decoder(srd.Decoder):
73 longname = 'Joint Test Action Group / ST STM32'
74 desc = 'ST STM32-specific JTAG protocol.'
77 outputs = ['jtag_stm32']
82 ['Text', 'Human-readable text'],
85 def __init__(self, **kwargs):
87 # self.state = 'BYPASS'
89 def start(self, metadata):
90 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
91 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
96 def handle_reg_bypass(self, bits):
98 self.put(self.ss, self.es, self.out_ann, [0, ['BYPASS: ' + bits]])
100 def handle_reg_idcode(self, bits):
102 self.put(self.ss, self.es, self.out_ann,
103 [0, ['IDCODE: 0x%x' % int('0b' + bits, 2)]])
105 # When transferring data IN:
106 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
107 # Bits[2:1] = A[3:2]: 2-bit address of a debug port register
108 # Bits[0:0] = RnW: Read request (1) or write request (0)
109 # When transferring data OUT:
110 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
111 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
112 def handle_reg_dpacc(self, bits):
113 self.put(self.ss, self.es, self.out_ann, [0, ['DPACC: ' + bits]])
115 # TODO: When to use Data IN / Data OUT?
118 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
119 data_hex = '0x%x' % int('0b' + data, 2)
120 r = 'Read request' if (rnw == '1') else 'Write request'
121 s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
122 self.put(self.ss, self.es, self.out_ann, [0, [s]])
125 data, ack = bits[:-3], bits[-3:]
126 data_hex = '0x%x' % int('0b' + data, 2)
127 ack_meaning = ack_val[ack]
128 s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
129 self.put(self.ss, self.es, self.out_ann, [0, [s]])
131 # When transferring data IN:
132 # Bits[34:3] = DATA[31:0]: 32bit data to shift in (write request)
133 # Bits[2:1] = A[3:2]: 2-bit address (sub-address AP register)
134 # Bits[0:0] = RnW: Read request (1) or write request (0)
135 # When transferring data OUT:
136 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
137 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
138 def handle_reg_apacc(self, bits):
139 self.put(self.ss, self.es, self.out_ann, [0, ['APACC: ' + bits]])
141 # TODO: When to use Data IN / Data OUT?
144 data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
145 data_hex = '0x%x' % int('0b' + data, 2)
146 r = 'Read request' if (rnw == '1') else 'Write request'
147 s = 'DATA: %s, A: %s, RnW: %s' % (data_hex, reg[a], r)
148 self.put(self.ss, self.es, self.out_ann, [0, [s]])
151 data, ack = bits[:-3], bits[-3:]
152 data_hex = '0x%x' % int('0b' + data, 2)
153 ack_meaning = ack_val[ack]
154 s = 'DATA: %s, ACK: %s' % (data_hex, ack_meaning)
155 self.put(self.ss, self.es, self.out_ann, [0, [s]])
157 def handle_reg_abort(self, bits):
158 # Bits[31:1]: reserved. Bit[0]: DAPABORT.
159 a = '' if (bits[0] == '1') else 'No '
160 s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
161 self.put(self.ss, self.es, self.out_ann, [0, [s]])
163 # Warn if DAPABORT[31:1] contains non-zero bits.
164 if (bits[:-1] != ('0' * 31)):
165 self.put(self.ss, self.es, self.out_ann,
166 [0, ['WARNING: DAPABORT[31:1] reserved!']])
168 def handle_reg_unknown(self, bits):
169 self.put(self.ss, self.es, self.out_ann,
170 [0, ['Unknown instruction: ' % bits]]) # TODO
172 def decode(self, ss, es, data):
173 # Assumption: The right-most char in the 'val' bitstring is the LSB.
176 self.ss, self.es = ss, es
178 # self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])
181 if self.state == 'IDLE':
182 # Wait until a new instruction is shifted into the IR register.
185 # Switch to the state named after the instruction, or 'UNKNOWN'.
186 self.state = ir.get(val[-4:], ['UNKNOWN', 0])[0]
187 self.put(self.ss, self.es, self.out_ann, [0, ['IR: ' + self.state]])
188 elif self.state in ('BYPASS'):
189 # In these states we're interested in incoming bits (TDI).
192 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
195 elif self.state in ('IDCODE', 'DPACC', 'APACC', 'ABORT', 'UNKNOWN'):
196 # In these states we're interested in outgoing bits (TDO).
197 # if cmd != 'DR TDO':
198 if cmd not in ('DR TDI', 'DR TDO'):
200 handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
204 raise Exception('Invalid state: %s' % self.state)