2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # ST STM32 JTAG protocol decoder
23 import sigrokdecode as srd
25 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
27 '1111': ['BYPASS', 1], # Bypass register
28 '1110': ['IDCODE', 32], # ID code register
29 '1010': ['DPACC', 35], # Debug port access register
30 '1011': ['APACC', 35], # Access port access register
31 '1000': ['ABORT', 35], # Abort register
34 # ARM Cortex-M3 r1p1-01rel0 ID code
35 cm3_idcode = 0x3ba00477
37 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
39 0x06412041: 'Low-density device, rev. A',
40 0x06410041: 'Medium-density device, rev. A',
41 0x16410041: 'Medium-density device, rev. B/Z/Y',
42 0x06414041: 'High-density device, rev. A/Z/Y',
43 0x06430041: 'XL-density device, rev. A',
44 0x06418041: 'Connectivity-line device, rev. A/Z',
47 # ACK[2:0] in the DPACC/APACC registers
59 # 32bit debug port registers (addressed via A[3:2])
61 '00': 'Reserved', # Must be kept at reset value
67 class Decoder(srd.Decoder):
71 longname = 'Joint Test Action Group / ST STM32'
72 desc = 'ST STM32-specific JTAG protocol.'
75 outputs = ['jtag_stm32']
80 ['ASCII', 'TODO: description'],
83 def __init__(self, **kwargs):
86 def start(self, metadata):
87 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag_stm32')
88 self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag_stm32')
93 def handle_reg_bypass(self, bits):
97 def handle_reg_idcode(self, bits):
101 # When transferring data IN:
102 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
103 # Bits[2:1] = A[3:2]: 2-bit address of a debug port register
104 # Bits[0:0] = RnW: Read request (1) or write request (0)
105 # When transferring data OUT:
106 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
107 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
108 def handle_reg_dpacc(self, bits):
109 self.put(self.ss, self.es, self.out_ann, [0, ['bits: ' + bits]])
112 data, a, rnw = bits[:-3], bits[-4:-1], bits[-1]
113 r = 'Read request' if (rnw == '1') else 'Write request'
114 s = 'DATA: %s, A: %s, RnW: %s' % (data, ack_val[a], r)
115 self.put(self.ss, self.es, self.out_ann, [0, [s]])
118 # data, ack = bits[:-3], bits[-3:]
119 # ack_meaning = ack_val[ack]
120 # s = 'DATA: %s, ACK: %s' % (data, ack_meaning)
121 # self.put(self.ss, self.es, self.out_ann, [0, [s]])
123 def handle_reg_apacc(self, bits):
127 def handle_reg_abort(self, bits):
128 # Bits[31:1]: reserved. Bit[0]: DAPABORT.
129 a = '' if (bits[0] == '1') else 'No '
130 s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
131 self.put(self.ss, self.es, self.out_ann, [0, [s]])
133 if (bits[:-1] != ('0' * 31)):
136 def decode(self, ss, es, data):
137 # Assumption: The right-most char in the 'val' bitstring is the LSB.
140 self.ss, self.es = ss, es
142 self.put(self.ss, self.es, self.out_ann, [0, [cmd + ' / ' + val]])