2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
30 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
31 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
32 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
33 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
34 'EXIT2-IR', 'UPDATE-IR'.
35 - 'IR TDI': Bitstring that was clocked into the IR register.
36 - 'IR TDO': Bitstring that was clocked out of the IR register.
37 - 'DR TDI': Bitstring that was clocked into the DR register.
38 - 'DR TDO': Bitstring that was clocked out of the DR register.
40 All bitstrings are a list consisting of two items. The first is a sequence
41 of '1' and '0' characters (the right-most character is the LSB. Example:
42 '01110001', where 1 is the LSB). The second item is a list of ss/es values
43 for each bit that is in the bitstring.
48 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
50 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
51 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
53 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
54 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
57 class Decoder(srd.Decoder):
61 longname = 'Joint Test Action Group (IEEE 1149.1)'
62 desc = 'Protocol for testing, debugging, and flashing ICs.'
67 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
68 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
69 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
70 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
73 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
74 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
75 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
77 annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
78 ('bit-tdi', 'Bit (TDI)'),
79 ('bit-tdo', 'Bit (TDO)'),
80 ('bitstring-tdi', 'Bitstring (TDI)'),
81 ('bitstring-tdo', 'Bitstring (TDO)'),
84 ('bits-tdi', 'Bits (TDI)', (16,)),
85 ('bits-tdo', 'Bits (TDO)', (17,)),
86 ('bitstrings-tdi', 'Bitstring (TDI)', (18,)),
87 ('bitstrings-tdo', 'Bitstring (TDO)', (19,)),
88 ('states', 'States', tuple(range(15 + 1))),
91 def __init__(self, **kwargs):
92 # self.state = 'TEST-LOGIC-RESET'
93 self.state = 'RUN-TEST/IDLE'
95 self.oldpins = (-1, -1, -1, -1)
99 self.bits_samplenums_tdi = []
100 self.bits_samplenums_tdo = []
102 self.ss_item = self.es_item = None
103 self.ss_bitstring = self.es_bitstring = None
104 self.saved_item = None
106 self.first_bit = True
109 self.out_python = self.register(srd.OUTPUT_PYTHON)
110 self.out_ann = self.register(srd.OUTPUT_ANN)
112 def putx(self, data):
113 self.put(self.ss_item, self.es_item, self.out_ann, data)
115 def putp(self, data):
116 self.put(self.ss_item, self.es_item, self.out_python, data)
118 def putx_bs(self, data):
119 self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
121 def putp_bs(self, data):
122 self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
124 def advance_state_machine(self, tms):
125 self.oldstate = self.state
128 if self.state == 'TEST-LOGIC-RESET':
129 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
130 elif self.state == 'RUN-TEST/IDLE':
131 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
134 elif self.state == 'SELECT-DR-SCAN':
135 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
136 elif self.state == 'CAPTURE-DR':
137 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
138 elif self.state == 'SHIFT-DR':
139 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
140 elif self.state == 'EXIT1-DR':
141 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
142 elif self.state == 'PAUSE-DR':
143 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
144 elif self.state == 'EXIT2-DR':
145 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
146 elif self.state == 'UPDATE-DR':
147 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
150 elif self.state == 'SELECT-IR-SCAN':
151 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
152 elif self.state == 'CAPTURE-IR':
153 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
154 elif self.state == 'SHIFT-IR':
155 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
156 elif self.state == 'EXIT1-IR':
157 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
158 elif self.state == 'PAUSE-IR':
159 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
160 elif self.state == 'EXIT2-IR':
161 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
162 elif self.state == 'UPDATE-IR':
163 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
165 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
166 # Rising TCK edges always advance the state machine.
167 self.advance_state_machine(tms)
170 # Save the start sample and item for later (no output yet).
171 self.ss_item = self.samplenum
174 # Output the saved item (from the last CLK edge to the current).
175 self.es_item = self.samplenum
176 # Output the old state (from last rising TCK edge to current one).
177 self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
178 self.putp(['NEW STATE', self.state])
180 # Upon SHIFT-IR/SHIFT-DR collect the current TDI/TDO values.
181 if self.state.startswith('SHIFT-'):
183 self.ss_bitstring = self.samplenum
184 self.first_bit = False
186 self.putx([16, [str(self.bits_tdi[0])]])
187 self.putx([17, [str(self.bits_tdo[0])]])
188 # Use self.samplenum as ES of the previous bit.
189 self.bits_samplenums_tdi[0][1] = self.samplenum
190 self.bits_samplenums_tdo[0][1] = self.samplenum
192 self.bits_tdi.insert(0, tdi)
193 self.bits_tdo.insert(0, tdo)
195 # Use self.samplenum as SS of the current bit.
196 self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
197 self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
199 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
200 if self.oldstate.startswith('SHIFT-') and \
201 self.state.startswith('EXIT1-'):
203 self.es_bitstring = self.samplenum
205 t = self.state[-2:] + ' TDI'
206 b = ''.join(map(str, self.bits_tdi))
207 h = ' (0x%x' % int('0b' + b, 2) + ')'
208 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
209 self.putx_bs([18, [s]])
210 self.bits_samplenums_tdi[0][1] = self.samplenum # ES of last bit.
211 self.putp_bs([t, [b, self.bits_samplenums_tdi]])
212 self.putx([16, [str(self.bits_tdi[0])]]) # Last bit.
214 self.bits_samplenums_tdi = []
216 t = self.state[-2:] + ' TDO'
217 b = ''.join(map(str, self.bits_tdo))
218 h = ' (0x%x' % int('0b' + b, 2) + ')'
219 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
220 self.putx_bs([19, [s]])
221 self.bits_samplenums_tdo[0][1] = self.samplenum # ES of last bit.
222 self.putp_bs([t, [b, self.bits_samplenums_tdo]])
223 self.putx([17, [str(self.bits_tdo[0])]]) # Last bit.
225 self.bits_samplenums_tdo = []
227 self.first_bit = True
229 self.ss_bitstring = self.samplenum
231 self.ss_item = self.samplenum
233 def decode(self, ss, es, data):
234 for (self.samplenum, pins) in data:
236 # If none of the pins changed, there's nothing to do.
237 if self.oldpins == pins:
240 # Store current pin values for the next round.
243 # Get individual pin values into local variables.
244 # Unused channels will have a value of > 1.
245 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
247 # We only care about TCK edges (either rising or falling).
248 if (self.oldtck == tck):
251 # Store start/end sample for later usage.
252 self.ss, self.es = ss, es
254 if (self.oldtck == 0 and tck == 1):
255 self.handle_rising_tck_edge(tdi, tdo, tck, tms)