2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
27 [<packet-type>, <data>]
29 <packet-type> is one of:
30 - 'NEW STATE': <data> is the new state of the JTAG state machine.
31 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
32 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
33 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
34 'EXIT2-IR', 'UPDATE-IR'.
35 - 'IR TDI': Bitstring that was clocked into the IR register.
36 - 'IR TDO': Bitstring that was clocked out of the IR register.
37 - 'DR TDI': Bitstring that was clocked into the DR register.
38 - 'DR TDO': Bitstring that was clocked out of the DR register.
41 All bitstrings are a sequence of '1' and '0' characters. The right-most
42 character in the bitstring is the LSB. Example: '01110001' (1 is LSB).
47 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
49 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
50 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
52 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
53 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
56 class Decoder(srd.Decoder):
60 longname = 'Joint Test Action Group (IEEE 1149.1)'
61 desc = 'Protocol for testing, debugging, and flashing ICs.'
66 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
67 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
68 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
69 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
72 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
73 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
74 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
77 annotations = [[s.lower(), s] for s in jtag_states]
79 def __init__(self, **kwargs):
80 # self.state = 'TEST-LOGIC-RESET'
81 self.state = 'RUN-TEST/IDLE'
83 self.oldpins = (-1, -1, -1, -1)
88 self.ss_item = self.es_item = None
89 self.saved_item = None
93 self.out_python = self.register(srd.OUTPUT_PYTHON)
94 self.out_ann = self.register(srd.OUTPUT_ANN)
97 self.put(self.ss_item, self.es_item, self.out_ann, data)
100 self.put(self.ss_item, self.es_item, self.out_python, data)
102 def advance_state_machine(self, tms):
103 self.oldstate = self.state
106 if self.state == 'TEST-LOGIC-RESET':
107 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
108 elif self.state == 'RUN-TEST/IDLE':
109 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
112 elif self.state == 'SELECT-DR-SCAN':
113 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
114 elif self.state == 'CAPTURE-DR':
115 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
116 elif self.state == 'SHIFT-DR':
117 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
118 elif self.state == 'EXIT1-DR':
119 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
120 elif self.state == 'PAUSE-DR':
121 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
122 elif self.state == 'EXIT2-DR':
123 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
124 elif self.state == 'UPDATE-DR':
125 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
128 elif self.state == 'SELECT-IR-SCAN':
129 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
130 elif self.state == 'CAPTURE-IR':
131 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
132 elif self.state == 'SHIFT-IR':
133 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
134 elif self.state == 'EXIT1-IR':
135 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
136 elif self.state == 'PAUSE-IR':
137 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
138 elif self.state == 'EXIT2-IR':
139 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
140 elif self.state == 'UPDATE-IR':
141 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
144 raise Exception('Invalid state: %s' % self.state)
146 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
147 # Rising TCK edges always advance the state machine.
148 self.advance_state_machine(tms)
150 if self.first == True:
151 # Save the start sample and item for later (no output yet).
152 self.ss_item = self.samplenum
154 self.saved_item = self.state
156 # Output the saved item (from the last CLK edge to the current).
157 self.es_item = self.samplenum
158 # Output the state we just switched to.
159 self.putx([jtag_states.index(self.state), [self.state]])
160 self.putp(['NEW STATE', self.state])
161 self.ss_item = self.samplenum
162 self.saved_item = self.state
164 # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
165 # collect the current TDI/TDO values (upon rising TCK edge).
166 if self.state.startswith('SHIFT-') and self.oldstate == self.state:
167 self.bits_tdi.insert(0, tdi)
168 self.bits_tdo.insert(0, tdo)
169 # TODO: ANN/PROTO output.
170 # self.putx([0, ['TDI add: ' + str(tdi)]])
171 # self.putp([0, ['TDO add: ' + str(tdo)]])
173 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
174 if self.oldstate.startswith('SHIFT-') and \
175 self.state.startswith('EXIT1-'):
177 t = self.state[-2:] + ' TDI'
178 b = ''.join(map(str, self.bits_tdi))
179 h = ' (0x%x' % int('0b' + b, 2) + ')'
180 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
181 # self.putx([0, [s]])
185 t = self.state[-2:] + ' TDO'
186 b = ''.join(map(str, self.bits_tdo))
187 h = ' (0x%x' % int('0b' + b, 2) + ')'
188 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
189 # self.putx([0, [s]])
193 def decode(self, ss, es, data):
194 for (self.samplenum, pins) in data:
196 # If none of the pins changed, there's nothing to do.
197 if self.oldpins == pins:
200 # Store current pin values for the next round.
203 # Get individual pin values into local variables.
204 # Unused probes will have a value of > 1.
205 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
207 # We only care about TCK edges (either rising or falling).
208 if (self.oldtck == tck):
211 # Store start/end sample for later usage.
212 self.ss, self.es = ss, es
214 # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
215 # % (tdi, tdo, tck, tms)]])
217 if (self.oldtck == 0 and tck == 1):
218 self.handle_rising_tck_edge(tdi, tdo, tck, tms)