2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
22 # Helper dictionary for edge detection.
24 'rising': lambda x, y: bool(not x and y),
25 'falling': lambda x, y: bool(x and not y),
26 'both': lambda x, y: bool(x ^ y),
29 class SamplerateError(Exception):
32 class Decoder(srd.Decoder):
36 longname = 'Timing jitter calculation'
37 desc = 'Retrieves the timing jitter between two digital signals.'
41 tags = ['Clock/timing', 'Util']
43 {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
44 {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
47 {'id': 'clk_polarity', 'desc': 'Clock edge polarity',
48 'default': 'rising', 'values': ('rising', 'falling', 'both')},
49 {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
50 'default': 'rising', 'values': ('rising', 'falling', 'both')},
53 ('jitter', 'Jitter value'),
54 ('clk_miss', 'Clock miss'),
55 ('sig_miss', 'Signal miss'),
58 ('jitter_vals', 'Jitter values', (0,)),
59 ('clk_misses', 'Clock misses', (1,)),
60 ('sig_misses', 'Signal misses', (2,)),
63 ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
71 self.samplerate = None
72 self.oldclk, self.oldsig = 0, 0
79 self.clk_edge = edge_detector[self.options['clk_polarity']]
80 self.sig_edge = edge_detector[self.options['sig_polarity']]
81 self.out_ann = self.register(srd.OUTPUT_ANN)
82 self.out_binary = self.register(srd.OUTPUT_BINARY)
83 self.out_clk_missed = self.register(srd.OUTPUT_META,
84 meta=(int, 'Clock missed', 'Clock transition missed'))
85 self.out_sig_missed = self.register(srd.OUTPUT_META,
86 meta=(int, 'Signal missed', 'Resulting signal transition missed'))
88 def metadata(self, key, value):
89 if key == srd.SRD_CONF_SAMPLERATE:
90 self.samplerate = value
92 # Helper function for jitter time annotations.
93 def putx(self, delta):
95 if delta == 0 or delta >= 1:
96 delta_s = '%.1fs' % (delta)
98 delta_s = '%.1ffs' % (delta * 1e15)
100 delta_s = '%.1fps' % (delta * 1e12)
102 delta_s = '%.1fns' % (delta * 1e9)
104 delta_s = '%.1fμs' % (delta * 1e6)
106 delta_s = '%.1fms' % (delta * 1e3)
108 self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
110 # Helper function for ASCII float jitter values (one value per line).
111 def putb(self, delta):
114 # Format the delta to an ASCII float value terminated by a newline.
115 x = str(delta) + '\n'
116 self.put(self.clk_start, self.sig_start, self.out_binary,
117 [0, x.encode('UTF-8')])
119 # Helper function for missed clock and signal annotations.
120 def putm(self, data):
121 self.put(self.samplenum, self.samplenum, self.out_ann, data)
123 def handle_clk(self, clk, sig):
124 if self.clk_start == self.samplenum:
125 # Clock transition already treated.
126 # We have done everything we can with this sample.
129 if self.clk_edge(self.oldclk, clk):
131 # We note the sample and move to the next state.
132 self.clk_start = self.samplenum
136 if self.sig_start is not None \
137 and self.sig_start != self.samplenum \
138 and self.sig_edge(self.oldsig, sig):
139 # If any transition in the resulting signal
140 # occurs while we are waiting for a clock,
141 # we increase the missed signal counter.
143 self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
144 self.putm([2, ['Missed signal', 'MS']])
145 # No clock edge found, we have done everything we
146 # can with this sample.
149 def handle_sig(self, clk, sig):
150 if self.sig_start == self.samplenum:
151 # Signal transition already treated.
152 # We have done everything we can with this sample.
155 if self.sig_edge(self.oldsig, sig):
157 # We note the sample, calculate the jitter
158 # and move to the next state.
159 self.sig_start = self.samplenum
161 # Calculate and report the timing jitter.
162 delta = (self.sig_start - self.clk_start) / self.samplerate
167 if self.clk_start != self.samplenum \
168 and self.clk_edge(self.oldclk, clk):
169 # If any transition in the clock signal
170 # occurs while we are waiting for a resulting
171 # signal, we increase the missed clock counter.
173 self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
174 self.putm([1, ['Missed clock', 'MC']])
175 # No resulting signal edge found, we have done
176 # everything we can with this sample.
180 if not self.samplerate:
181 raise SamplerateError('Cannot decode without samplerate.')
183 # Wait for a transition on CLK and/or SIG.
184 clk, sig = self.wait([{0: 'e'}, {1: 'e'}])
187 # For each sample we can move 2 steps forward in the state machine.
189 # Clock state has the lead.
190 if self.state == 'CLK':
191 if self.handle_clk(clk, sig):
193 if self.state == 'SIG':
194 if self.handle_sig(clk, sig):
197 # Save current CLK/SIG values for the next round.
198 self.oldclk, self.oldsig = clk, sig