2 ## This file is part of the sigrok project.
4 ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 # I2C protocol decoder
26 # The Inter-Integrated Circuit (I2C) bus is a bidirectional, multi-master
27 # bus using two signals (SCL = serial clock line, SDA = serial data line).
29 # There can be many devices on the same bus. Each device can potentially be
30 # master or slave (and that can change during runtime). Both slave and master
31 # can potentially play the transmitter or receiver role (this can also
34 # Possible maximum data rates:
35 # - Standard mode: 100 kbit/s
36 # - Fast mode: 400 kbit/s
37 # - Fast-mode Plus: 1 Mbit/s
38 # - High-speed mode: 3.4 Mbit/s
40 # START condition (S): SDA = falling, SCL = high
41 # Repeated START condition (Sr): same as S
42 # Data bit sampling: SCL = rising
43 # STOP condition (P): SDA = rising, SCL = high
45 # All data bytes on SDA are exactly 8 bits long (transmitted MSB-first).
46 # Each byte has to be followed by a 9th ACK/NACK bit. If that bit is low,
47 # that indicates an ACK, if it's high that indicates a NACK.
49 # After the first START condition, a master sends the device address of the
50 # slave it wants to talk to. Slave addresses are 7 bits long (MSB-first).
51 # After those 7 bits, a data direction bit is sent. If the bit is low that
52 # indicates a WRITE operation, if it's high that indicates a READ operation.
54 # Later an optional 10bit slave addressing scheme was added.
57 # http://www.nxp.com/acrobat/literature/9398/39340011.pdf (v2.1 spec)
58 # http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf (v3 spec)
59 # http://en.wikipedia.org/wiki/I2C
62 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
63 # TODO: Handle clock stretching.
64 # TODO: Handle combined messages / repeated START.
65 # TODO: Implement support for 7bit and 10bit slave addresses.
66 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
67 # TODO: Implement support for detecting various bus errors.
72 # The output consists of a (Python) list of I2C "packets", each of which
73 # has an (implicit) index number (its index in the list).
74 # Each packet consists of a Python dict with certain key/value pairs.
76 # TODO: Make this a list later instead of a dict?
79 # - 'S' (START condition)
80 # - 'Sr' (Repeated START)
81 # - 'AR' (Address, read)
82 # - 'AW' (Address, write)
84 # - 'DW' (Data, write)
85 # - 'P' (STOP condition)
86 # 'range': (tuple of 2 integers, the min/max samplenumber of this range)
88 # - min/max can also be identical.
89 # 'data': (actual data as integer ???) TODO: This can be very variable...
90 # 'ann': (string; additional annotations / comments)
92 # TODO: I2C address of slaves.
93 # TODO: Handle multiple different I2C devices on same bus
94 # -> we need to decode multiple protocols at the same time.
101 # [[id, channel, description], ...] # TODO
104 # {'id': 'SCL', 'ch': 5, 'desc': 'Serial clock line'}
105 # {'id': 'SDA', 'ch': 7, 'desc': 'Serial data line'}
109 # 'signals': [{'SCL': }]}
114 # values are verbose and short annotation, respectively
116 'START': ['START', 'S'],
117 'START_REPEAT': ['START REPEAT', 'Sr'],
118 'STOP': ['STOP', 'P'],
120 'NACK': ['NACK', 'N'],
121 'ADDRESS_READ': ['ADDRESS READ', 'AR'],
122 'ADDRESS_WRITE': ['ADDRESS WRITE','AW'],
123 'DATA_READ': ['DATA READ', 'DR'],
124 'DATA_WRITE': ['DATA WRITE', 'DW'],
126 # export protocol keys as symbols for i2c decoders up the stack
127 EXPORT = [ protocol.keys() ]
134 # annotation feed formats
136 ANN_SHIFTED_SHORT = 1
140 class Decoder(sigrokdecode.Decoder):
143 longname = 'Inter-Integrated Circuit (I2C) bus'
144 desc = 'I2C is a two-wire, multi-master, serial bus.'
146 author = 'Uwe Hermann'
147 email = 'uwe@hermann-uwe.de'
152 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
153 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
156 'address-space': ['Address space (in bits)', 7],
160 ["7-bit shifted hex",
161 "Read/Write bit shifted out from the 8-bit i2c slave address"],
163 ["7-bit shifted hex (short)",
164 "Read/Write bit shifted out from the 8-bit i2c slave address"],
166 ["Raw hex", "Unaltered raw data"]
169 def __init__(self, **kwargs):
170 self.output_protocol = None
171 self.output_annotation = None
176 self.startsample = -1
177 self.is_repeat_start = 0
178 self.state = FIND_START
182 def start(self, metadata):
183 self.output_protocol = self.add(sigrokdecode.SRD_OUTPUT_PROTOCOL, 'i2c')
184 self.output_annotation = self.add(sigrokdecode.SRD_OUTPUT_ANNOTATION, 'i2c')
189 def is_start_condition(self, scl, sda):
190 """START condition (S): SDA = falling, SCL = high"""
191 if (self.oldsda == 1 and sda == 0) and scl == 1:
195 def is_data_bit(self, scl, sda):
196 """Data sampling of receiver: SCL = rising"""
197 if self.oldscl == 0 and scl == 1:
201 def is_stop_condition(self, scl, sda):
202 """STOP condition (P): SDA = rising, SCL = high"""
203 if (self.oldsda == 0 and sda == 1) and scl == 1:
207 def found_start(self, scl, sda):
208 if self.is_repeat_start == 1:
212 self.put(self.output_protocol, [ cmd ])
213 self.put(self.output_annotation, [ ANN_SHIFTED, [protocol[cmd][0]] ])
214 self.put(self.output_annotation, [ ANN_SHIFTED_SHORT, [protocol[cmd][1]] ])
216 self.state = FIND_ADDRESS
217 self.bitcount = self.databyte = 0
218 self.is_repeat_start = 1
221 def found_address_or_data(self, scl, sda):
222 """Gather 8 bits of data plus the ACK/NACK bit."""
224 if self.startsample == -1:
225 # TODO: should be samplenum, as received from the feed
226 self.startsample = self.samplecnt
229 # Address and data are transmitted MSB-first.
233 # Return if we haven't collected all 8 + 1 bits, yet.
234 if self.bitcount != 9:
237 # send raw output annotation before we start shifting out
238 # read/write and ack/nack bits
239 self.put(self.output_annotation, [ANN_RAW, ["0x%.2x" % self.databyte]])
241 # We received 8 address/data bits and the ACK/NACK bit.
242 self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
244 if self.state == FIND_ADDRESS:
245 # The READ/WRITE bit is only in address bytes, not data bytes.
246 if self.databyte & 1:
250 d = self.databyte >> 1
251 elif self.state == FIND_DATA:
257 # last bit that came in was the ACK/NACK bit (1 = NACK)
264 if self.state == FIND_ADDRESS and self.wr == 1:
265 cmd = 'ADDRESS_WRITE'
266 elif self.state == FIND_ADDRESS and self.wr == 0:
268 elif self.state == FIND_DATA and self.wr == 1:
270 elif self.state == FIND_DATA and self.wr == 0:
272 self.put(self.output_protocol, [ [cmd, d], [ack_bit] ] )
273 self.put(self.output_annotation, [ANN_SHIFTED, [
274 "%s" % protocol[cmd][0],
276 "%s" % protocol[ack_bit][0]]
278 self.put(self.output_annotation, [ANN_SHIFTED_SHORT, [
279 "%s" % protocol[cmd][1],
281 "%s" % protocol[ack_bit][1]]
284 self.bitcount = self.databyte = 0
285 self.startsample = -1
287 if self.state == FIND_ADDRESS:
288 self.state = FIND_DATA
289 elif self.state == FIND_DATA:
290 # There could be multiple data bytes in a row.
291 # So, either find a STOP condition or another data byte next.
294 def found_stop(self, scl, sda):
295 self.put(self.output_protocol, [ 'STOP' ])
296 self.put(self.output_annotation, [ ANN_SHIFTED, [protocol['STOP'][0]] ])
297 self.put(self.output_annotation, [ ANN_SHIFTED_SHORT, [protocol['STOP'][1]] ])
299 self.state = FIND_START
300 self.is_repeat_start = 0
303 def put(self, output_id, data):
304 # inject sample range into the call up to sigrok
305 # TODO: 0-0 sample range for now
306 super(Decoder, self).put(0, 0, output_id, data)
308 def decode(self, timeoffset, duration, data):
309 for samplenum, (scl, sda) in data:
312 # First sample: Save SCL/SDA value.
313 if self.oldscl == None:
318 # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
321 if self.state == FIND_START:
322 if self.is_start_condition(scl, sda):
323 self.found_start(scl, sda)
324 elif self.state == FIND_ADDRESS:
325 if self.is_data_bit(scl, sda):
326 self.found_address_or_data(scl, sda)
327 elif self.state == FIND_DATA:
328 if self.is_data_bit(scl, sda):
329 self.found_address_or_data(scl, sda)
330 elif self.is_start_condition(scl, sda):
331 self.found_start(scl, sda)
332 elif self.is_stop_condition(scl, sda):
333 self.found_stop(scl, sda)
338 # Save current SDA/SCL values for the next round.