2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2010-2014 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # TODO: Look into arbitration, collision detection, clock synchronisation, etc.
22 # TODO: Implement support for 10bit slave addresses.
23 # TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
24 # TODO: Implement support for detecting various bus errors.
26 import sigrokdecode as srd
35 - 'START' (START condition)
36 - 'START REPEAT' (Repeated START condition)
37 - 'ADDRESS READ' (Slave address, read)
38 - 'ADDRESS WRITE' (Slave address, write)
39 - 'DATA READ' (Data, read)
40 - 'DATA WRITE' (Data, write)
41 - 'STOP' (STOP condition)
44 - 'BITS' (<pdata>: list of data/address bits and their ss/es numbers)
46 <pdata> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
47 command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
48 For example, a slave address field could be 0x51 (instead of 0xa2).
49 For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <pdata> is None.
52 # CMD: [annotation-type-index, long annotation, short annotation]
54 'START': [0, 'Start', 'S'],
55 'START REPEAT': [1, 'Start repeat', 'Sr'],
56 'STOP': [2, 'Stop', 'P'],
57 'ACK': [3, 'ACK', 'A'],
58 'NACK': [4, 'NACK', 'N'],
59 'BIT': [5, 'Bit', 'B'],
60 'ADDRESS READ': [6, 'Address read', 'AR'],
61 'ADDRESS WRITE': [7, 'Address write', 'AW'],
62 'DATA READ': [8, 'Data read', 'DR'],
63 'DATA WRITE': [9, 'Data write', 'DW'],
66 class Decoder(srd.Decoder):
70 longname = 'Inter-Integrated Circuit'
71 desc = 'Two-wire, multi-master, serial bus.'
76 {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
77 {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
80 {'id': 'address_format', 'desc': 'Displayed slave address format',
81 'default': 'shifted', 'values': ('shifted', 'unshifted')},
84 ('start', 'Start condition'),
85 ('repeat-start', 'Repeat start condition'),
86 ('stop', 'Stop condition'),
89 ('bit', 'Data/address bit'),
90 ('address-read', 'Address read'),
91 ('address-write', 'Address write'),
92 ('data-read', 'Data read'),
93 ('data-write', 'Data write'),
94 ('warnings', 'Human-readable warnings'),
97 ('bits', 'Bits', (5,)),
98 ('addr-data', 'Address/Data', (0, 1, 2, 3, 4, 6, 7, 8, 9)),
99 ('warnings', 'Warnings', (10,)),
102 ('address-read', 'Address read'),
103 ('address-write', 'Address write'),
104 ('data-read', 'Data read'),
105 ('data-write', 'Data write'),
108 def __init__(self, **kwargs):
109 self.samplerate = None
110 self.ss = self.es = self.byte_ss = -1
111 self.samplenum = None
115 self.is_repeat_start = 0
116 self.state = 'FIND START'
117 self.oldscl = self.oldsda = 1
118 self.oldpins = [1, 1]
119 self.pdu_start = None
123 def metadata(self, key, value):
124 if key == srd.SRD_CONF_SAMPLERATE:
125 self.samplerate = value
128 self.out_python = self.register(srd.OUTPUT_PYTHON)
129 self.out_ann = self.register(srd.OUTPUT_ANN)
130 self.out_binary = self.register(srd.OUTPUT_BINARY)
131 self.out_bitrate = self.register(srd.OUTPUT_META,
132 meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
134 def putx(self, data):
135 self.put(self.ss, self.es, self.out_ann, data)
137 def putp(self, data):
138 self.put(self.ss, self.es, self.out_python, data)
140 def putb(self, data):
141 self.put(self.ss, self.es, self.out_binary, data)
143 def is_start_condition(self, scl, sda):
144 # START condition (S): SDA = falling, SCL = high
145 if (self.oldsda == 1 and sda == 0) and scl == 1:
149 def is_data_bit(self, scl, sda):
150 # Data sampling of receiver: SCL = rising
151 if self.oldscl == 0 and scl == 1:
155 def is_stop_condition(self, scl, sda):
156 # STOP condition (P): SDA = rising, SCL = high
157 if (self.oldsda == 0 and sda == 1) and scl == 1:
161 def found_start(self, scl, sda):
162 self.ss, self.es = self.samplenum, self.samplenum
163 self.pdu_start = self.samplenum
165 cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
166 self.putp([cmd, None])
167 self.putx([proto[cmd][0], proto[cmd][1:]])
168 self.state = 'FIND ADDRESS'
169 self.bitcount = self.databyte = 0
170 self.is_repeat_start = 1
174 # Gather 8 bits of data plus the ACK/NACK bit.
175 def found_address_or_data(self, scl, sda):
176 # Address and data are transmitted MSB-first.
180 # Remember the start of the first data/address bit.
181 if self.bitcount == 0:
182 self.byte_ss = self.samplenum
184 # Store individual bits and their start/end samplenumbers.
185 # In the list, index 0 represents the LSB (I²C transmits MSB-first).
186 self.bits.insert(0, [sda, self.samplenum, self.samplenum])
187 if self.bitcount > 0:
188 self.bits[1][2] = self.samplenum
189 if self.bitcount == 7:
190 self.bitwidth = self.bits[1][2] - self.bits[2][2]
191 self.bits[0][2] += self.bitwidth
193 # Return if we haven't collected all 8 + 1 bits, yet.
194 if self.bitcount < 7:
199 if self.state == 'FIND ADDRESS':
200 # The READ/WRITE bit is only in address bytes, not data bytes.
201 self.wr = 0 if (self.databyte & 1) else 1
202 if self.options['address_format'] == 'shifted':
206 if self.state == 'FIND ADDRESS' and self.wr == 1:
207 cmd = 'ADDRESS WRITE'
209 elif self.state == 'FIND ADDRESS' and self.wr == 0:
212 elif self.state == 'FIND DATA' and self.wr == 1:
215 elif self.state == 'FIND DATA' and self.wr == 0:
219 self.ss, self.es = self.byte_ss, self.samplenum + self.bitwidth
221 self.putp(['BITS', self.bits])
224 self.putb((bin_class, bytes([d])))
226 for bit in self.bits:
227 self.put(bit[1], bit[2], self.out_ann, [5, ['%d' % bit[0]]])
229 if cmd.startswith('ADDRESS'):
230 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
231 w = ['Write', 'Wr', 'W'] if self.wr else ['Read', 'Rd', 'R']
232 self.putx([proto[cmd][0], w])
233 self.ss, self.es = self.byte_ss, self.samplenum
235 self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
236 '%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
238 # Done with this packet.
239 self.bitcount = self.databyte = 0
241 self.state = 'FIND ACK'
243 def get_ack(self, scl, sda):
244 self.ss, self.es = self.samplenum, self.samplenum + self.bitwidth
245 cmd = 'NACK' if (sda == 1) else 'ACK'
246 self.putp([cmd, None])
247 self.putx([proto[cmd][0], proto[cmd][1:]])
248 # There could be multiple data bytes in a row, so either find
249 # another data byte or a STOP condition next.
250 self.state = 'FIND DATA'
252 def found_stop(self, scl, sda):
254 elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
255 bitrate = int(1 / elapsed * self.pdu_bits)
256 self.put(self.byte_ss, self.samplenum, self.out_bitrate, bitrate)
259 self.ss, self.es = self.samplenum, self.samplenum
260 self.putp([cmd, None])
261 self.putx([proto[cmd][0], proto[cmd][1:]])
262 self.state = 'FIND START'
263 self.is_repeat_start = 0
267 def decode(self, ss, es, data):
268 if self.samplerate is None:
269 raise Exception("Cannot decode without samplerate.")
270 for (self.samplenum, pins) in data:
272 # Ignore identical samples early on (for performance reasons).
273 if self.oldpins == pins:
275 self.oldpins, (scl, sda) = pins, pins
280 if self.state == 'FIND START':
281 if self.is_start_condition(scl, sda):
282 self.found_start(scl, sda)
283 elif self.state == 'FIND ADDRESS':
284 if self.is_data_bit(scl, sda):
285 self.found_address_or_data(scl, sda)
286 elif self.state == 'FIND DATA':
287 if self.is_data_bit(scl, sda):
288 self.found_address_or_data(scl, sda)
289 elif self.is_start_condition(scl, sda):
290 self.found_start(scl, sda)
291 elif self.is_stop_condition(scl, sda):
292 self.found_stop(scl, sda)
293 elif self.state == 'FIND ACK':
294 if self.is_data_bit(scl, sda):
295 self.get_ack(scl, sda)
297 raise Exception('Invalid state: %s' % self.state)
299 # Save current SDA/SCL values for the next round.
300 self.oldscl, self.oldsda = scl, sda