2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2019 Jiahao Li <reg@ljh.me>
6 ## Permission is hereby granted, free of charge, to any person obtaining a copy
7 ## of this software and associated documentation files (the "Software"), to deal
8 ## in the Software without restriction, including without limitation the rights
9 ## to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 ## copies of the Software, and to permit persons to whom the Software is
11 ## furnished to do so, subject to the following conditions:
13 ## The above copyright notice and this permission notice shall be included in all
14 ## copies or substantial portions of the Software.
16 ## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 ## IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 ## FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19 ## AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 ## LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 ## OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 import sigrokdecode as srd
26 OPCODE_MASK = 0b11100000
27 REG_ADDR_MASK = 0b00011111
30 0b00000000: '_process_rcr',
31 0b00100000: '_process_rbm',
32 0b01000000: '_process_wcr',
33 0b01100000: '_process_wbm',
34 0b10000000: '_process_bfs',
35 0b10100000: '_process_bfc',
36 0b11100000: '_process_src',
39 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC, ANN_DATA,
40 ANN_REG_ADDR, ANN_WARNING) = range(10)
43 BIT_ECON1_BSEL0 = 0b00000001
44 BIT_ECON1_BSEL1 = 0b00000010
185 class Decoder(srd.Decoder):
189 longname = 'Microchip ENC28J60'
190 desc = 'Microchip ENC28J60 10Base-T Ethernet controller protocol.'
193 outputs = ['enc28j60']
194 tags = ['Embedded/industrial', 'Networking']
196 ('rcr', 'Read Control Register'),
197 ('rbm', 'Read Buffer Memory'),
198 ('wcr', 'Write Control Register'),
199 ('wbm', 'Write Buffer Memory'),
200 ('bfs', 'Bit Field Set'),
201 ('bfc', 'Bit Field Clear'),
202 ('src', 'System Reset Command'),
204 ('reg-addr', 'Register Address'),
205 ('warning', 'Warning'),
208 ('commands', 'Commands',
209 (ANN_RCR, ANN_RBM, ANN_WCR, ANN_WBM, ANN_BFS, ANN_BFC, ANN_SRC)),
210 ('fields', 'Fields', (ANN_DATA, ANN_REG_ADDR)),
211 ('warnings', 'Warnings', (ANN_WARNING,)),
221 self.command_start = None
222 self.command_end = None
228 self.ann = self.register(srd.OUTPUT_ANN)
230 def _process_command(self):
231 if len(self.mosi) == 0:
235 header = self.mosi[0]
236 opcode = header & OPCODE_MASK
238 if opcode not in OPCODE_HANDLERS:
239 self._put_command_warning("Unknown opcode.")
243 getattr(self, OPCODE_HANDLERS[opcode])()
247 def _get_register_name(self, reg_addr):
248 if (self.bsel0 is None) or (self.bsel1 is None):
249 # We don't know the bank we're in yet.
252 bank = (self.bsel1 << 1) + self.bsel0
253 return REGS[bank][reg_addr]
255 def _put_register_header(self):
256 reg_addr = self.mosi[0] & REG_ADDR_MASK
257 reg_name = self._get_register_name(reg_addr)
260 # We don't know the bank we're in yet.
261 self.put(self.command_start, self.ranges[1][0], self.ann, [
264 'Reg Bank ? Addr 0x{0:02X}'.format(reg_addr),
265 '?:{0:02X}'.format(reg_addr),
267 self.put(self.command_start, self.ranges[1][0], self.ann, [
270 'Warning: Register bank not known yet.',
274 self.put(self.command_start, self.ranges[1][0], self.ann, [
277 'Reg {0}'.format(reg_name),
278 '{0}'.format(reg_name),
281 if (reg_name == '-') or (reg_name == 'Reserved'):
282 self.put(self.command_start, self.ranges[1][0], self.ann, [
285 'Warning: Invalid register accessed.',
289 def _put_data_byte(self, data, byte_index, binary=False):
290 if byte_index == len(self.mosi) - 1:
291 end_sample = self.command_end
293 end_sample = self.ranges[byte_index + 1][0]
296 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
299 'Data 0b{0:08b}'.format(data),
300 '{0:08b}'.format(data),
303 self.put(self.ranges[byte_index][0], end_sample, self.ann, [
306 'Data 0x{0:02X}'.format(data),
307 '{0:02X}'.format(data),
310 def _put_command_warning(self, reason):
311 self.put(self.command_start, self.command_end, self.ann, [
314 'Warning: {0}'.format(reason),
318 def _process_rcr(self):
319 self.put(self.command_start, self.command_end,
320 self.ann, [ANN_RCR, ['Read Control Register', 'RCR']])
322 if (len(self.mosi) != 2) and (len(self.mosi) != 3):
323 self._put_command_warning('Invalid command length.')
326 self._put_register_header()
328 reg_name = self._get_register_name(self.mosi[0] & REG_ADDR_MASK)
330 # We can't tell if we're accessing MAC/MII registers or not
331 # Let's trust the user in this case.
334 if (reg_name[0] == 'M') and (len(self.mosi) != 3):
335 self._put_command_warning('Attempting to read a MAC/MII '
336 + 'register without using the dummy byte.')
339 if (reg_name[0] != 'M') and (len(self.mosi) != 2):
340 self._put_command_warning('Attempting to read a non-MAC/MII '
341 + 'register using the dummy byte.')
344 if len(self.mosi) == 2:
345 self._put_data_byte(self.miso[1], 1)
347 self.put(self.ranges[1][0], self.ranges[2][0], self.ann, [
353 self._put_data_byte(self.miso[2], 2)
355 def _process_rbm(self):
356 if self.mosi[0] != 0b00111010:
357 self._put_command_warning('Invalid header byte.')
360 self.put(self.command_start, self.command_end, self.ann, [
363 'Read Buffer Memory: Length {0}'.format(
368 for i in range(1, len(self.miso)):
369 self._put_data_byte(self.miso[i], i)
371 def _process_wcr(self):
372 self.put(self.command_start, self.command_end,
373 self.ann, [ANN_WCR, ['Write Control Register', 'WCR']])
375 if len(self.mosi) != 2:
376 self._put_command_warning('Invalid command length.')
379 self._put_register_header()
380 self._put_data_byte(self.mosi[1], 1)
382 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
383 self.bsel0 = (self.mosi[1] & BIT_ECON1_BSEL0) >> 0
384 self.bsel1 = (self.mosi[1] & BIT_ECON1_BSEL1) >> 1
386 def _process_wbm(self):
387 if self.mosi[0] != 0b01111010:
388 self._put_command_warning('Invalid header byte.')
391 self.put(self.command_start, self.command_end, self.ann, [
394 'Write Buffer Memory: Length {0}'.format(
399 for i in range(1, len(self.mosi)):
400 self._put_data_byte(self.mosi[i], i)
402 def _process_bfc(self):
403 self.put(self.command_start, self.command_end,
404 self.ann, [ANN_BFC, ['Bit Field Clear', 'BFC']])
406 if len(self.mosi) != 2:
407 self._put_command_warning('Invalid command length.')
410 self._put_register_header()
411 self._put_data_byte(self.mosi[1], 1, True)
413 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
414 if self.mosi[1] & BIT_ECON1_BSEL0:
416 if self.mosi[1] & BIT_ECON1_BSEL1:
419 def _process_bfs(self):
420 self.put(self.command_start, self.command_end,
421 self.ann, [ANN_BFS, ['Bit Field Set', 'BFS']])
423 if len(self.mosi) != 2:
424 self._put_command_warning('Invalid command length.')
427 self._put_register_header()
428 self._put_data_byte(self.mosi[1], 1, True)
430 if self.mosi[0] & REG_ADDR_MASK == REG_ADDR_ECON1:
431 if self.mosi[1] & BIT_ECON1_BSEL0:
433 if self.mosi[1] & BIT_ECON1_BSEL1:
436 def _process_src(self):
437 self.put(self.command_start, self.command_end,
438 self.ann, [ANN_SRC, ['System Reset Command', 'SRC']])
440 if len(self.mosi) != 1:
441 self._put_command_warning('Invalid command length.')
447 def decode(self, ss, es, data):
448 ptype, data1, data2 = data
450 if ptype == 'CS-CHANGE':
455 self.command_start = ss
461 self.command_end = es
462 self._process_command()
463 elif ptype == 'DATA':
464 mosi, miso = data1, data2
466 self.mosi.append(mosi)
467 self.miso.append(miso)
468 self.ranges.append((ss, es))