2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2016 fenugrec <fenugrec users.sourceforge.net>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
21 # - Annotations are very crude and could be improved.
22 # - Annotate every nibble? Would give insight on interrupted shifts.
23 # - Annotate invalid "command" nibbles while SYNC==1?
25 import sigrokdecode as srd
27 class Decoder(srd.Decoder):
31 longname = 'Advanced User Debugger'
32 desc = 'Renesas/Hitachi Advanced User Debugger (AUD) protocol.'
36 tags = ['Debug/trace']
38 {'id': 'audck', 'name': 'AUDCK', 'desc': 'AUD clock'},
39 {'id': 'naudsync', 'name': 'nAUDSYNC', 'desc': 'AUD sync'},
40 {'id': 'audata3', 'name': 'AUDATA3', 'desc': 'AUD data line 3'},
41 {'id': 'audata2', 'name': 'AUDATA2', 'desc': 'AUD data line 2'},
42 {'id': 'audata1', 'name': 'AUDATA1', 'desc': 'AUD data line 1'},
43 {'id': 'audata0', 'name': 'AUDATA0', 'desc': 'AUD data line 0'},
46 ('dest', 'Destination address'),
60 self.out_ann = self.register(srd.OUTPUT_ANN)
63 self.put(self.ss, self.samplenum, self.out_ann, data)
65 def handle_clk_edge(self, clk, sync, datapins):
69 nib |= datapins[3-i] << i
71 # sync == 1: annotate if finished; update cmd.
72 # TODO: Annotate idle level (nibble = 0x03 && SYNC=1).
74 if (self.ncnt == self.nmax) and (self.nmax != 0):
75 # Done shifting an address: annotate.
76 self.putx([0, ['0x%08X' % self.addr]])
77 self.lastaddr = self.addr
80 self.addr = self.lastaddr
81 self.ss = self.samplenum
94 # sync == 0, valid cmd: start or continue shifting in nibbles.
97 self.addr &= ~(0x0F << (self.ncnt * 4))
99 self.addr |= nib << (self.ncnt * 4)
104 pins = self.wait({0: 'r'})
108 self.handle_clk_edge(clk, sync, d)