2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2020 Analog Devices Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 3 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
21 from common.srdhelper import SrdIntEnum
30 READ, WRITE = range(2)
33 ENABLE = {1: ['Enable %s', 'En %s', '%s '], 0: ['Disable %s', 'Dis %s', '!%s '],}
34 SOURCE = {1: ['Involve %s', 'Inv %s', '%s'], 0: ['Not involve %s', 'Not inv %s', '!%s'],}
35 INTERRUPT = {1: ['INT2 %s', 'I2: %s '], 0: ['INT1 %s', 'I1:%s '],}
36 AC_DC = {1: ['%s ac', 'ac'], 0: ['%s dc', 'dc'],}
37 UNUSED = {1: ['N/A'], 0: ['N/A'],}
41 def __init__(self, name, type, values=None):
47 def set_value(self, value):
50 def get_bit_annotation(self):
51 if self.type == BitType.OTHER:
52 annotation = self.values[self.value].copy()
54 annotation = self.type[self.value].copy()
56 for index in range(len(annotation)):
57 if '%s' in annotation[index]:
58 annotation[index] = str(annotation[index] % self.name)
61 Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING')
63 St = SrdIntEnum.from_str('St', 'IDLE ADDRESS_BYTE DATA')
65 class Decoder(srd.Decoder):
69 longname = 'Analog Devices ADXL345'
70 desc = 'Analog Devices ADXL345 3-axis accelerometer.'
74 tags = ['IC', 'Sensor']
78 ('mb', 'Multiple bytes'),
79 ('reg-address', 'Register address'),
80 ('reg-data', 'Register data'),
81 ('warning', 'Warning'),
84 ('reg', 'Registers', (Ann.READ, Ann.WRITE, Ann.MB, Ann.REG_ADDRESS)),
85 ('data', 'Data', (Ann.REG_DATA, Ann.WARNING)),
92 self.mosi, self.miso = [], []
98 self.ss, self.es = -1, -1
99 self.samples_per_bit = 0
102 self.out_ann = self.register(srd.OUTPUT_ANN)
104 def putx(self, data):
105 self.put(self.ss, self.es, self.out_ann, data)
107 def putb(self, data, index):
108 start = self.ss + (self.samples_per_bit * index)
109 self.put(start, start + self.samples_per_bit, self.out_ann, data)
111 def putbs(self, data, start_index, stop_index):
112 start_index = self.reverse_bit_index(start_index, WORD_SIZE)
113 stop_index = self.reverse_bit_index(stop_index, WORD_SIZE)
114 start = self.ss + (self.samples_per_bit * start_index)
115 stop = start + (self.samples_per_bit * (stop_index - start_index + 1))
116 self.put(start, stop, self.out_ann, data)
118 def handle_reg_with_scaling_factor(self, data, factor, name, unit, error_msg):
119 if data == 0 and error_msg is not None:
120 self.putx([Ann.WARNING, error_msg])
122 result = (data * factor) / 1000
123 self.putx([Ann.REG_DATA, ['%s: %f %s' % (name, result, unit), '%f %s' % (result, unit)]])
125 def handle_reg_bit_msg(self, bit, index, en_msg, dis_msg):
126 self.putb([Ann.REG_DATA, [en_msg if bit else dis_msg]], index)
128 def interpret_bits(self, data, bits):
130 for offset in range(8):
131 bits_values.insert(0, (data & (1 << offset)) >> offset)
133 for index in range(len(bits)):
134 if bits[index] is None:
137 bit.set_value(bits_values[index])
138 self.putb([Ann.REG_DATA, bit.get_bit_annotation()], index)
140 return list(reversed(bits_values))
142 def reverse_bit_index(self, index, word_size):
143 return word_size - index - 1
145 def get_decimal_number(self, bits, start_index, stop_index):
147 interval = range(start_index, stop_index + 1, 1)
148 for index, offset in zip(interval, range(len(interval))):
150 number = number | (bit << offset)
153 def get_axis_value(self, data, axis):
157 self.put(self.start_index, self.es, self.out_ann,
158 [Ann.REG_DATA, ['%s: 0x%04X' % (axis, self.data), str(data)]])
161 self.putx([Ann.REG_DATA, [str(data)]])
163 def handle_reg_0x1d(self, data):
164 self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
165 error_messages['undesirable'])
167 def handle_reg_0x1e(self, data):
168 self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
170 def handle_reg_0x1f(self, data):
171 self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
173 def handle_reg_0x20(self, data):
174 self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
176 def handle_reg_0x21(self, data):
177 self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's',
178 error_messages['dis_single_double'])
180 def handle_reg_0x22(self, data):
181 self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
182 error_messages['dis_double'])
184 def handle_reg_0x23(self, data):
185 self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
186 error_messages['dis_double'])
188 def handle_reg_0x24(self, data):
189 self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
190 error_messages['undesirable'])
192 def handle_reg_0x25(self, data):
193 self.handle_reg_0x1d(data)
195 def handle_reg_0x26(self, data):
196 self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
197 error_messages['interrupt'])
199 def handle_reg_0x27(self, data):
200 bits = [Bit('ACT', BitType.AC_DC),
201 Bit('ACT_X', BitType.ENABLE),
202 Bit('ACT_Y', BitType.ENABLE),
203 Bit('ACT_Z', BitType.ENABLE),
204 Bit('INACT', BitType.AC_DC),
205 Bit('INACT_X', BitType.ENABLE),
206 Bit('INACT_Y', BitType.ENABLE),
207 Bit('INACT_Z', BitType.ENABLE)]
208 self.interpret_bits(data, bits)
210 def handle_reg_0x28(self, data):
211 self.handle_reg_0x1d(data)
213 def handle_reg_0x29(self, data):
214 self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
215 error_messages['undesirable'])
217 def handle_reg_0x2a(self, data):
218 bits = [Bit('', BitType.UNUSED),
219 Bit('', BitType.UNUSED),
220 Bit('', BitType.UNUSED),
221 Bit('', BitType.UNUSED),
222 Bit('', BitType.OTHER, {1: ['Suppressed', 'Suppr', 'S'],
223 0: ['Unsuppressed', 'Unsuppr', 'Uns'],}),
224 Bit('TAP_X', BitType.ENABLE),
225 Bit('TAP_Y', BitType.ENABLE),
226 Bit('TAP_Z', BitType.ENABLE)]
227 self.interpret_bits(data, bits)
229 def handle_reg_0x2b(self, data):
230 bits = [Bit('', BitType.UNUSED),
231 Bit('ACT_X', BitType.SOURCE),
232 Bit('ACT_Y', BitType.SOURCE),
233 Bit('ACT_Z', BitType.SOURCE),
234 Bit('', BitType.OTHER, {1: ['Asleep', 'Asl'],
235 0: ['Not asleep', 'Not asl', '!Asl'],}),
236 Bit('TAP_X', BitType.SOURCE),
237 Bit('TAP_Y', BitType.SOURCE),
238 Bit('TAP_Z', BitType.SOURCE)]
239 self.interpret_bits(data, bits)
241 def handle_reg_0x2c(self, data):
242 bits = [Bit('', BitType.UNUSED),
243 Bit('', BitType.UNUSED),
244 Bit('', BitType.UNUSED),
245 Bit('', BitType.OTHER, {1: ['Reduce power', 'Reduce pw', 'Red pw'], 0: ['Normal operation', 'Normal op', 'Norm op'],})]
246 bits_values = self.interpret_bits(data, bits)
248 start_index, stop_index = 0, 3
249 rate = self.get_decimal_number(bits_values, start_index, stop_index)
250 self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)
252 def handle_reg_0x2d(self, data):
253 bits = [Bit('', BitType.UNUSED),
254 Bit('', BitType.UNUSED),
255 Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
256 Bit('AUTO_SLEEP', BitType.ENABLE),
257 Bit('', BitType.OTHER, {1: ['Measurement mode', 'Measurement', 'Meas'], 0: ['Standby mode', 'Standby'], }),
258 Bit('', BitType.OTHER, {1: ['Sleep mode', 'Sleep', 'Slp'], 0: ['Normal mode', 'Normal', 'Nrm'],})]
259 bits_values = self.interpret_bits(data, bits)
261 start_index, stop_index = 0, 1
262 wakeup = self.get_decimal_number(bits_values, start_index, stop_index)
263 frequency = 2 ** (~wakeup & 0x03)
264 self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)
266 def handle_reg_0x2e(self, data):
267 bits = [Bit('DATA_READY', BitType.ENABLE),
268 Bit('SINGLE_TAP', BitType.ENABLE),
269 Bit('DOUBLE_TAP', BitType.ENABLE),
270 Bit('Activity', BitType.ENABLE),
271 Bit('Inactivity', BitType.ENABLE),
272 Bit('FREE_FALL', BitType.ENABLE),
273 Bit('Watermark', BitType.ENABLE),
274 Bit('Overrun', BitType.ENABLE)]
275 self.interpret_bits(data, bits)
277 def handle_reg_0x2f(self, data):
278 bits = [Bit('DATA_READY', BitType.INTERRUPT),
279 Bit('SINGLE_TAP', BitType.INTERRUPT),
280 Bit('DOUBLE_TAP', BitType.INTERRUPT),
281 Bit('Activity', BitType.INTERRUPT),
282 Bit('Inactivity', BitType.INTERRUPT),
283 Bit('FREE_FALL', BitType.INTERRUPT),
284 Bit('Watermark', BitType.INTERRUPT),
285 Bit('Overrun', BitType.INTERRUPT)]
286 self.interpret_bits(data, bits)
288 def handle_reg_0x30(self, data):
289 bits = [Bit('DATA_READY', BitType.SOURCE),
290 Bit('SINGLE_TAP', BitType.SOURCE),
291 Bit('DOUBLE_TAP', BitType.SOURCE),
292 Bit('Activity', BitType.SOURCE),
293 Bit('Inactivity', BitType.SOURCE),
294 Bit('FREE_FALL', BitType.SOURCE),
295 Bit('Watermark', BitType.SOURCE),
296 Bit('Overrun', BitType.SOURCE)]
297 self.interpret_bits(data, bits)
299 def handle_reg_0x31(self, data):
300 bits = [Bit('SELF_TEST', BitType.ENABLE),
301 Bit('', BitType.OTHER, {1: ['3-wire SPI', '3-SPI'], 0: ['4-wire SPI', '4-SPI'],}),
302 Bit('', BitType.OTHER, {1: ['INT ACT LOW', 'INT LOW'], 0: ['INT ACT HIGH', 'INT HIGH'],}),
303 Bit('', BitType.UNUSED),
304 Bit('', BitType.OTHER, {1: ['Full resolution', 'Full res'], 0: ['10-bit mode', '10-bit'],}),
305 Bit('', BitType.OTHER, {1: ['MSB mode', 'MSB'], 0: ['LSB mode', 'LSB'],})]
306 bits_values = self.interpret_bits(data, bits)
308 start_index, stop_index = 0, 1
309 range_g = self.get_decimal_number(bits_values, start_index, stop_index)
310 result = 2 ** (range_g + 1)
311 self.putbs([Ann.REG_DATA, ['+/-%d g' % result]], stop_index, start_index)
313 def handle_reg_0x32(self, data):
315 self.putx([Ann.REG_DATA, [str(data)]])
317 def handle_reg_0x33(self, data):
318 self.get_axis_value(data, 'X')
320 def handle_reg_0x34(self, data):
321 self.handle_reg_0x32(data)
323 def handle_reg_0x35(self, data):
324 self.get_axis_value(data, 'Y')
326 def handle_reg_0x36(self, data):
327 self.handle_reg_0x32(data)
329 def handle_reg_0x37(self, data):
330 self.get_axis_value(data, 'Z')
332 def handle_reg_0x38(self, data):
335 Bit('', BitType.OTHER, {1: ['Trig-INT2', 'INT2'], 0: ['Trig-INT1', 'INT1'], })]
336 bits_values = self.interpret_bits(data, bits)
338 start_index, stop_index = 6, 7
339 fifo = self.get_decimal_number(bits_values, start_index, stop_index)
340 self.putbs([Ann.REG_DATA, [fifo_modes[fifo]]], stop_index, start_index)
342 start_index, stop_index = 0, 4
343 samples = self.get_decimal_number(bits_values, start_index, stop_index)
344 self.putbs([Ann.REG_DATA, ['Samples: %d' % samples, '%d' % samples]], stop_index, start_index)
346 def handle_reg_0x39(self, data):
347 bits = [Bit('', BitType.OTHER, {1: ['Triggered', 'Trigg'], 0: ['Not triggered', 'Not trigg'],}),
348 Bit('', BitType.UNUSED)]
349 bits_values = self.interpret_bits(data, bits)
351 start_index, stop_index = 0, 5
352 entries = self.get_decimal_number(bits_values, start_index, stop_index)
353 self.putbs([Ann.REG_DATA, ['Entries: %d' % entries, '%d' % entries]], stop_index, start_index)
355 def get_bit(self, channel):
356 if (channel == Channel.MOSI and self.mosi is None) or \
357 (channel == Channel.MISO and self.miso is None):
358 raise Exception('No available data')
360 mosi_bit, miso_bit = 0, 0
361 if self.miso is not None:
362 if len(self.mosi) < 0:
363 raise Exception('No available data')
364 miso_bit = self.miso.pop(0)
365 if self.miso is not None:
366 if len(self.miso) < 0:
367 raise Exception('No available data')
368 mosi_bit = self.mosi.pop(0)
370 if channel == Channel.MOSI:
374 def decode(self, ss, es, data):
377 if ptype == 'CS-CHANGE':
378 cs_old, cs_new = data[1:]
379 if cs_old is not None and cs_old == 1 and cs_new == 0:
380 self.ss, self.es = ss, es
381 self.state = St.ADDRESS_BYTE
385 elif ptype == 'BITS':
386 if data[1] is not None:
387 self.mosi = list(reversed(data[1]))
388 if data[2] is not None:
389 self.miso = list(reversed(data[2]))
391 if self.mosi is None and self.miso is None:
394 if self.state == St.ADDRESS_BYTE:
396 op_bit = self.get_bit(Channel.MOSI)
397 self.put(op_bit[1], op_bit[2], self.out_ann,
398 [Ann.READ if op_bit[0] else Ann.WRITE, operations[op_bit[0]]])
399 self.operation = Operation.READ if op_bit[0] else Operation.WRITE
401 mb_bit = self.get_bit(Channel.MOSI)
402 self.put(mb_bit[1], mb_bit[2], self.out_ann, [Ann.MB, number_bytes[mb_bit[0]]])
404 # REGISTER 6-BIT ADDRESS
406 start_sample = self.mosi[0][1]
409 addr_bit = self.get_bit(Channel.MOSI)
410 self.address |= addr_bit[0]
413 self.put(start_sample, addr_bit[2], self.out_ann,
414 [Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X'
415 % self.address, '0x%02X' % self.address]])
419 elif self.state == St.DATA:
420 self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
422 self.mosi, self.miso = [], []
424 self.ss, self.es = self.reg[0][1], es
425 self.samples_per_bit = self.reg[0][2] - self.ss
427 if len(self.reg) < 8:
432 for offset in range(7, -1, -1):
433 reg_bit = self.reg.pop(0)
435 mask = reg_bit[0] << offset
438 if self.address < 0x00 or self.address > 0x39:
441 if self.address in [0x32, 0x34, 0x36]:
442 self.start_index = self.ss
444 if 0x1D > self.address >= 0x00:
445 self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, [str(self.address)]])
446 self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
448 self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
449 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.address)
450 handle_reg(reg_value)