2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2017 Joel Holdsworth <joel@airwebreathe.org.uk>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 3 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
21 from common.srdhelper import bitpack_lsb
23 def disabled_enabled(v):
24 return ['Disabled', 'Enabled'][v]
27 return '{:+d}dBm'.format([-4, -1, 2, 5][v])
29 # Notes on the implementation:
30 # - Bit fields' width in registers determines the range of indices in
31 # table/tuple lookups. Keep the implementation as robust as possible
32 # during future maintenance. Avoid Python runtime errors when adjusting
35 # reg: name offset width parser
37 ('FRAC', 3, 12, None),
38 ('INT', 15, 16, lambda v: 'Not Allowed' if v < 32 else v)
42 ('Phase', 15, 12, None),
43 ('Prescalar', 27, 1, lambda v: ['4/5', '8/9'][v]),
44 ('Phase Adjust', 28, 1, lambda v: ['Off', 'On'][v]),
47 ('Counter Reset', 3, 1, disabled_enabled),
48 ('Charge Pump Three-State', 4, 1, disabled_enabled),
49 ('Power-Down', 5, 1, disabled_enabled),
50 ('PD Polarity', 6, 1, lambda v: ['Negative', 'Positive'][v]),
51 ('LDP', 7, 1, lambda v: ['10ns', '6ns'][v]),
52 ('LDF', 8, 1, lambda v: ['FRAC-N', 'INT-N'][v]),
53 ('Charge Pump Current Setting', 9, 4, lambda v: '{curr:0.2f}mA @ 5.1kΩ'.format(
55 0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50,
56 2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00,
58 ('Double Buffer', 13, 1, disabled_enabled),
59 ('R Counter', 14, 10, None),
60 ('RDIV2', 24, 1, disabled_enabled),
61 ('Reference Doubler', 25, 1, disabled_enabled),
62 ('MUXOUT', 26, 3, lambda v: '{text}'.format(
64 'Three-State Output', 'DVdd', 'DGND',
65 'R Counter Output', 'N Divider Output',
66 'Analog Lock Detect', 'Digital Lock Detect',
69 ('Low Noise and Low Spur Modes', 29, 2, lambda v: '{text}'.format(
71 'Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode'
75 ('Clock Divider', 3, 12, None),
76 ('Clock Divider Mode', 15, 2, lambda v: '{text}'.format(
78 'Clock Divider Off', 'Fast Lock Enable', 'Resync Enable', 'Reserved'
80 ('CSR Enable', 18, 1, disabled_enabled),
81 ('Charge Cancellation', 21, 1, disabled_enabled),
82 ('ABP', 22, 1, lambda v: ['6ns (FRAC-N)', '3ns (INT-N)'][v]),
83 ('Band Select Clock Mode', 23, 1, lambda v: ['Low', 'High'][v])
86 ('Output Power', 3, 2, output_power),
87 ('Output Enable', 5, 1, disabled_enabled),
88 ('AUX Output Power', 6, 2, output_power),
89 ('AUX Output Select', 8, 1, lambda v: ['Divided Output', 'Fundamental'][v]),
90 ('AUX Output Enable', 9, 1, disabled_enabled),
91 ('MTLD', 10, 1, disabled_enabled),
92 ('VCO Power-Down', 11, 1, lambda v:
93 'VCO Powered {updown}'.format(updown = 'Down' if v else 'Up')),
94 ('Band Select Clock Divider', 12, 8, None),
95 ('RF Divider Select', 20, 3, lambda v: '÷{:d}'.format(2 ** v)),
96 ('Feedback Select', 23, 1, lambda v: ['Divided', 'Fundamental'][v]),
99 ('LD Pin Mode', 22, 2, lambda v: '{text}'.format(
101 'Low', 'Digital Lock Detect', 'Low', 'High',
109 class Decoder(srd.Decoder):
113 longname = 'Analog Devices ADF4350/1'
114 desc = 'Wideband synthesizer with integrated VCO.'
118 tags = ['Clock/timing', 'IC', 'Wireless/RF']
120 # Sent from the host to the chip.
121 ('write', 'Register write'),
122 ('warning', "Warnings"),
125 ('writes', 'Register writes', (ANN_REG,)),
126 ('warnings', 'Warnings', (ANN_WARN,)),
136 self.out_ann = self.register(srd.OUTPUT_ANN)
138 def putg(self, ss, es, cls, data):
139 self.put(ss, es, self.out_ann, [ cls, data, ])
141 def decode_bits(self, offset, width):
142 '''Extract a bit field. Expects LSB input data.'''
143 bits = self.bits[offset:][:width]
144 ss, es = bits[-1][1], bits[0][2]
145 value = bitpack_lsb(bits, 0)
146 return ( value, ( ss, es, ))
148 def decode_field(self, name, offset, width, parser):
149 '''Interpret a bit field. Emits an annotation.'''
150 val, ( ss, es, ) = self.decode_bits(offset, width)
151 val = parser(val) if parser else '{}'.format(val)
152 text = ['{name}: {val}'.format(name = name, val = val)]
153 self.putg(ss, es, ANN_REG, text)
155 def decode_word(self, ss, es, bits):
156 '''Interpret a 32bit word after accumulation completes.'''
157 # SPI transfer content must be exactly one 32bit word.
158 count = len(self.bits)
161 'Frame error: Bit count: want 32, got {}'.format(count),
162 'Frame error: Bit count',
165 self.putg(ss, es, ANN_WARN, text)
167 # Holding bits in LSB order during interpretation simplifies
168 # bit field extraction. And annotation emitting routines expect
169 # this reverse order of bits' timestamps.
171 # Determine which register was accessed.
172 reg_addr, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
174 'Register: {addr}'.format(addr = reg_addr),
175 'Reg: {addr}'.format(addr = reg_addr),
176 '[{addr}]'.format(addr = reg_addr),
178 self.putg(reg_ss, reg_es, ANN_REG, text)
179 # Interpret the register's content (when parsers are available).
180 field_descs = regs.get(reg_addr, None)
183 for field_desc in field_descs:
184 self.decode_field(*field_desc)
186 def decode(self, ss, es, data):
189 if ptype == 'TRANSFER':
190 # Process accumulated bits after completion of a transfer.
191 self.decode_word(ss, es, self.bits)
195 _, mosi_bits, miso_bits = data
196 # Accumulate bits in MSB order as they are seen in SPI frames.
197 msb_bits = mosi_bits.copy()
199 self.bits.extend(msb_bits)