2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2017 Joel Holdsworth <joel@airwebreathe.org.uk>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 3 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
22 def disabled_enabled(v):
23 return ['Disabled', 'Enabled'][v]
26 return '%+ddBm' % [-4, -1, 2, 5][v]
29 # reg: name offset width parser
31 ('FRAC', 3, 12, None),
32 ('INT', 15, 16, lambda v: 'Not Allowed' if v < 32 else v)
36 ('Phase', 15, 12, None),
37 ('Prescalar', 27, 1, lambda v: ['4/5', '8/9'][v]),
38 ('Phase Adjust', 28, 1, lambda v: ['Off', 'On'][v]),
41 ('Counter Reset', 3, 1, disabled_enabled),
42 ('Charge Pump Three-State', 4, 1, disabled_enabled),
43 ('Power-Down', 5, 1, disabled_enabled),
44 ('PD Polarity', 6, 1, lambda v: ['Negative', 'Positive'][v]),
45 ('LDP', 7, 1, lambda v: ['10ns', '6ns'][v]),
46 ('LDF', 8, 1, lambda v: ['FRAC-N', 'INT-N'][v]),
47 ('Charge Pump Current Setting', 9, 4, lambda v: '%0.2fmA @ 5.1kΩ' %
48 [0.31, 0.63, 0.94, 1.25, 1.56, 1.88, 2.19, 2.50,
49 2.81, 3.13, 3.44, 3.75, 4.06, 4.38, 4.69, 5.00][v]),
50 ('Double Buffer', 13, 1, disabled_enabled),
51 ('R Counter', 14, 10, None),
52 ('RDIV2', 24, 1, disabled_enabled),
53 ('Reference Doubler', 25, 1, disabled_enabled),
54 ('MUXOUT', 26, 3, lambda v:
55 ['Three-State Output', 'DVdd', 'DGND', 'R Counter Output', 'N Divider Output',
56 'Analog Lock Detect', 'Digital Lock Detect', 'Reserved'][v]),
57 ('Low Noise and Low Spur Modes', 29, 2, lambda v:
58 ['Low Noise Mode', 'Reserved', 'Reserved', 'Low Spur Mode'][v])
61 ('Clock Divider', 3, 12, None),
62 ('Clock Divider Mode', 15, 2, lambda v:
63 ['Clock Divider Off', 'Fast Lock Enable', 'Resync Enable', 'Reserved'][v]),
64 ('CSR Enable', 18, 1, disabled_enabled),
65 ('Charge Cancellation', 21, 1, disabled_enabled),
66 ('ABP', 22, 1, lambda v: ['6ns (FRAC-N)', '3ns (INT-N)'][v]),
67 ('Band Select Clock Mode', 23, 1, lambda v: ['Low', 'High'][v])
70 ('Output Power', 3, 2, output_power),
71 ('Output Enable', 5, 1, disabled_enabled),
72 ('AUX Output Power', 6, 2, output_power),
73 ('AUX Output Select', 8, 1, lambda v: ['Divided Output', 'Fundamental'][v]),
74 ('AUX Output Enable', 9, 1, disabled_enabled),
75 ('MTLD', 10, 1, disabled_enabled),
76 ('VCO Power-Down', 11, 1, lambda v:
77 'VCO Powered ' + ('Down' if v == 1 else 'Up')),
78 ('Band Select Clock Divider', 12, 8, None),
79 ('RF Divider Select', 20, 3, lambda v: '÷' + str(2**v)),
80 ('Feedback Select', 23, 1, lambda v: ['Divided', 'Fundamental'][v]),
83 ('LD Pin Mode', 22, 2, lambda v:
84 ['Low', 'Digital Lock Detect', 'Low', 'High'][v])
90 class Decoder(srd.Decoder):
94 longname = 'Analog Devices ADF4350/1'
95 desc = 'Wideband synthesizer with integrated VCO.'
99 tags = ['Clock/timing', 'IC', 'Wireless/RF']
101 # Sent from the host to the chip.
102 ('write', 'Register write'),
105 ('writes', 'Register writes', (ANN_REG,)),
115 self.out_ann = self.register(srd.OUTPUT_ANN)
117 def decode_bits(self, offset, width):
118 return (sum([(1 << i) if self.bits[offset + i][0] else 0 for i in range(width)]),
119 (self.bits[offset + width - 1][1], self.bits[offset][2]))
121 def decode_field(self, name, offset, width, parser):
122 val, pos = self.decode_bits(offset, width)
123 self.put(pos[0], pos[1], self.out_ann, [ANN_REG,
124 ['%s: %s' % (name, parser(val) if parser else str(val))]])
127 def decode(self, ss, es, data):
129 ptype, data1, data2 = data
131 if ptype == 'CS-CHANGE':
133 if len(self.bits) == 32:
134 reg_value, reg_pos = self.decode_bits(0, 3)
135 self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
136 ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
137 '[%d]' % reg_value]])
138 if reg_value < len(regs):
139 field_descs = regs[reg_value]
140 for field_desc in field_descs:
141 field = self.decode_field(*field_desc)
144 self.bits = data1 + self.bits