2 * This file is part of the libsigrok project.
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
27 #include <glib/gstdio.h>
30 #include "libsigrok.h"
31 #include "libsigrok-internal.h"
32 #include "asix-sigma.h"
34 #define USB_VENDOR 0xa600
35 #define USB_PRODUCT 0xa000
36 #define USB_DESCRIPTION "ASIX SIGMA"
37 #define USB_VENDOR_NAME "ASIX"
38 #define USB_MODEL_NAME "SIGMA"
39 #define USB_MODEL_VERSION ""
40 #define TRIGGER_TYPE "rf10"
43 SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
44 static struct sr_dev_driver *di = &asix_sigma_driver_info;
45 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
47 static const uint64_t samplerates[] = {
61 * Probe numbers seem to go from 1-16, according to this image:
62 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
63 * (the cable has two additional GND pins, and a TI and TO pin)
65 static const char *probe_names[NUM_PROBES + 1] = {
66 "1", "2", "3", "4", "5", "6", "7", "8",
67 "9", "10", "11", "12", "13", "14", "15", "16",
71 static const int32_t hwcaps[] = {
72 SR_CONF_LOGIC_ANALYZER,
74 SR_CONF_CAPTURE_RATIO,
78 /* Force the FPGA to reboot. */
79 static uint8_t suicide[] = {
80 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
83 /* Prepare to upload firmware (FPGA specific). */
84 static uint8_t init[] = {
85 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
88 /* Initialize the logic analyzer mode. */
89 static uint8_t logic_mode_start[] = {
90 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
91 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
94 static const char *firmware_files[] = {
95 "asix-sigma-50.fw", /* 50 MHz, supports 8 bit fractions */
96 "asix-sigma-100.fw", /* 100 MHz */
97 "asix-sigma-200.fw", /* 200 MHz */
98 "asix-sigma-50sync.fw", /* Synchronous clock from pin */
99 "asix-sigma-phasor.fw", /* Frequency counter */
102 static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
108 sr_err("ftdi_read_data failed: %s",
109 ftdi_get_error_string(&devc->ftdic));
115 static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
121 sr_err("ftdi_write_data failed: %s",
122 ftdi_get_error_string(&devc->ftdic));
123 } else if ((size_t) ret != size) {
124 sr_err("ftdi_write_data did not complete write.");
130 static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
131 struct dev_context *devc)
134 uint8_t buf[len + 2];
137 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
138 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
140 for (i = 0; i < len; ++i) {
141 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
142 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
145 return sigma_write(buf, idx, devc);
148 static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
150 return sigma_write_register(reg, &value, 1, devc);
153 static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
154 struct dev_context *devc)
158 buf[0] = REG_ADDR_LOW | (reg & 0xf);
159 buf[1] = REG_ADDR_HIGH | (reg >> 4);
160 buf[2] = REG_READ_ADDR;
162 sigma_write(buf, sizeof(buf), devc);
164 return sigma_read(data, len, devc);
167 static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
171 if (1 != sigma_read_register(reg, &value, 1, devc)) {
172 sr_err("sigma_get_register: 1 byte expected");
179 static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
180 struct dev_context *devc)
183 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
185 REG_READ_ADDR | NEXT_REG,
186 REG_READ_ADDR | NEXT_REG,
187 REG_READ_ADDR | NEXT_REG,
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
194 sigma_write(buf, sizeof(buf), devc);
196 sigma_read(result, sizeof(result), devc);
198 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
199 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
201 /* Not really sure why this must be done, but according to spec. */
202 if ((--*stoppos & 0x1ff) == 0x1ff)
205 if ((*--triggerpos & 0x1ff) == 0x1ff)
211 static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
212 uint8_t *data, struct dev_context *devc)
218 /* Send the startchunk. Index start with 1. */
219 buf[0] = startchunk >> 8;
220 buf[1] = startchunk & 0xff;
221 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
224 buf[idx++] = REG_DRAM_BLOCK;
225 buf[idx++] = REG_DRAM_WAIT_ACK;
227 for (i = 0; i < numchunks; ++i) {
228 /* Alternate bit to copy from DRAM to cache. */
229 if (i != (numchunks - 1))
230 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
232 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
234 if (i != (numchunks - 1))
235 buf[idx++] = REG_DRAM_WAIT_ACK;
238 sigma_write(buf, idx, devc);
240 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
243 /* Upload trigger look-up tables to Sigma. */
244 static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
250 /* Transpose the table and send to Sigma. */
251 for (i = 0; i < 16; ++i) {
256 if (lut->m2d[0] & bit)
258 if (lut->m2d[1] & bit)
260 if (lut->m2d[2] & bit)
262 if (lut->m2d[3] & bit)
272 if (lut->m0d[0] & bit)
274 if (lut->m0d[1] & bit)
276 if (lut->m0d[2] & bit)
278 if (lut->m0d[3] & bit)
281 if (lut->m1d[0] & bit)
283 if (lut->m1d[1] & bit)
285 if (lut->m1d[2] & bit)
287 if (lut->m1d[3] & bit)
290 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
295 /* Send the parameters */
296 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
297 sizeof(lut->params), devc);
302 /* Generate the bitbang stream for programming the FPGA. */
303 static int bin2bitbang(const char *filename,
304 unsigned char **buf, size_t *buf_size)
307 unsigned long file_size;
308 unsigned long offset = 0;
311 unsigned long fwsize = 0;
312 const int buffer_size = 65536;
315 uint32_t imm = 0x3f6df2ab;
317 f = g_fopen(filename, "rb");
319 sr_err("g_fopen(\"%s\", \"rb\")", filename);
323 if (-1 == fseek(f, 0, SEEK_END)) {
324 sr_err("fseek on %s failed", filename);
329 file_size = ftell(f);
331 fseek(f, 0, SEEK_SET);
333 if (!(firmware = g_try_malloc(buffer_size))) {
334 sr_err("%s: firmware malloc failed", __func__);
336 return SR_ERR_MALLOC;
339 while ((c = getc(f)) != EOF) {
340 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
341 firmware[fwsize++] = c ^ imm;
345 if(fwsize != file_size) {
346 sr_err("%s: Error reading firmware", filename);
352 *buf_size = fwsize * 2 * 8;
354 *buf = p = (unsigned char *)g_try_malloc(*buf_size);
356 sr_err("%s: buf/p malloc failed", __func__);
358 return SR_ERR_MALLOC;
361 for (i = 0; i < fwsize; ++i) {
362 for (bit = 7; bit >= 0; --bit) {
363 v = firmware[i] & 1 << bit ? 0x40 : 0x00;
364 p[offset++] = v | 0x01;
371 if (offset != *buf_size) {
373 sr_err("Error reading firmware %s "
374 "offset=%ld, file_size=%ld, buf_size=%zd.",
375 filename, offset, file_size, *buf_size);
383 static int clear_instances(void)
386 struct sr_dev_inst *sdi;
387 struct drv_context *drvc;
388 struct dev_context *devc;
392 /* Properly close all devices. */
393 for (l = drvc->instances; l; l = l->next) {
394 if (!(sdi = l->data)) {
395 /* Log error, but continue cleaning up the rest. */
396 sr_err("%s: sdi was NULL, continuing", __func__);
401 ftdi_deinit(&devc->ftdic);
403 sr_dev_inst_free(sdi);
405 g_slist_free(drvc->instances);
406 drvc->instances = NULL;
411 static int hw_init(struct sr_context *sr_ctx)
413 return std_hw_init(sr_ctx, di, LOG_PREFIX);
416 static GSList *hw_scan(GSList *options)
418 struct sr_dev_inst *sdi;
419 struct sr_probe *probe;
420 struct drv_context *drvc;
421 struct dev_context *devc;
423 struct ftdi_device_list *devlist;
434 if (!(devc = g_try_malloc(sizeof(struct dev_context)))) {
435 sr_err("%s: devc malloc failed", __func__);
439 ftdi_init(&devc->ftdic);
441 /* Look for SIGMAs. */
443 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
444 USB_VENDOR, USB_PRODUCT)) <= 0) {
446 sr_err("ftdi_usb_find_all(): %d", ret);
450 /* Make sure it's a version 1 or 2 SIGMA. */
451 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
452 serial_txt, sizeof(serial_txt));
453 sscanf(serial_txt, "%x", &serial);
455 if (serial < 0xa6010000 || serial > 0xa602ffff) {
456 sr_err("Only SIGMA and SIGMA2 are supported "
457 "in this version of libsigrok.");
461 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
463 devc->cur_samplerate = 0;
465 devc->limit_msec = 0;
466 devc->cur_firmware = -1;
467 devc->num_probes = 0;
468 devc->samples_per_event = 0;
469 devc->capture_ratio = 50;
470 devc->use_triggers = 0;
472 /* Register SIGMA device. */
473 if (!(sdi = sr_dev_inst_new(0, SR_ST_INITIALIZING, USB_VENDOR_NAME,
474 USB_MODEL_NAME, USB_MODEL_VERSION))) {
475 sr_err("%s: sdi was NULL", __func__);
480 for (i = 0; probe_names[i]; i++) {
481 if (!(probe = sr_probe_new(i, SR_PROBE_LOGIC, TRUE,
484 sdi->probes = g_slist_append(sdi->probes, probe);
487 devices = g_slist_append(devices, sdi);
488 drvc->instances = g_slist_append(drvc->instances, sdi);
491 /* We will open the device again when we need it. */
492 ftdi_list_free(&devlist);
497 ftdi_deinit(&devc->ftdic);
502 static GSList *hw_dev_list(void)
504 return ((struct drv_context *)(di->priv))->instances;
507 static int upload_firmware(int firmware_idx, struct dev_context *devc)
513 unsigned char result[32];
514 char firmware_path[128];
516 /* Make sure it's an ASIX SIGMA. */
517 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
518 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
519 sr_err("ftdi_usb_open failed: %s",
520 ftdi_get_error_string(&devc->ftdic));
524 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG)) < 0) {
525 sr_err("ftdi_set_bitmode failed: %s",
526 ftdi_get_error_string(&devc->ftdic));
530 /* Four times the speed of sigmalogan - Works well. */
531 if ((ret = ftdi_set_baudrate(&devc->ftdic, 750000)) < 0) {
532 sr_err("ftdi_set_baudrate failed: %s",
533 ftdi_get_error_string(&devc->ftdic));
537 /* Force the FPGA to reboot. */
538 sigma_write(suicide, sizeof(suicide), devc);
539 sigma_write(suicide, sizeof(suicide), devc);
540 sigma_write(suicide, sizeof(suicide), devc);
541 sigma_write(suicide, sizeof(suicide), devc);
543 /* Prepare to upload firmware (FPGA specific). */
544 sigma_write(init, sizeof(init), devc);
546 ftdi_usb_purge_buffers(&devc->ftdic);
548 /* Wait until the FPGA asserts INIT_B. */
550 ret = sigma_read(result, 1, devc);
551 if (result[0] & 0x20)
555 /* Prepare firmware. */
556 snprintf(firmware_path, sizeof(firmware_path), "%s/%s", FIRMWARE_DIR,
557 firmware_files[firmware_idx]);
559 if ((ret = bin2bitbang(firmware_path, &buf, &buf_size)) != SR_OK) {
560 sr_err("An error occured while reading the firmware: %s",
565 /* Upload firmare. */
566 sr_info("Uploading firmware file '%s'.", firmware_files[firmware_idx]);
567 sigma_write(buf, buf_size, devc);
571 if ((ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET)) < 0) {
572 sr_err("ftdi_set_bitmode failed: %s",
573 ftdi_get_error_string(&devc->ftdic));
577 ftdi_usb_purge_buffers(&devc->ftdic);
579 /* Discard garbage. */
580 while (1 == sigma_read(&pins, 1, devc))
583 /* Initialize the logic analyzer mode. */
584 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
586 /* Expect a 3 byte reply. */
587 ret = sigma_read(result, 3, devc);
589 result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
590 sr_err("Configuration failed. Invalid reply received.");
594 devc->cur_firmware = firmware_idx;
596 sr_info("Firmware uploaded.");
601 static int hw_dev_open(struct sr_dev_inst *sdi)
603 struct dev_context *devc;
608 /* Make sure it's an ASIX SIGMA. */
609 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
610 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
612 sr_err("ftdi_usb_open failed: %s",
613 ftdi_get_error_string(&devc->ftdic));
618 sdi->status = SR_ST_ACTIVE;
623 static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
625 struct dev_context *devc;
632 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
633 if (samplerates[i] == samplerate)
636 if (samplerates[i] == 0)
637 return SR_ERR_SAMPLERATE;
639 if (samplerate <= SR_MHZ(50)) {
640 ret = upload_firmware(0, devc);
641 devc->num_probes = 16;
643 if (samplerate == SR_MHZ(100)) {
644 ret = upload_firmware(1, devc);
645 devc->num_probes = 8;
647 else if (samplerate == SR_MHZ(200)) {
648 ret = upload_firmware(2, devc);
649 devc->num_probes = 4;
652 devc->cur_samplerate = samplerate;
653 devc->period_ps = 1000000000000ULL / samplerate;
654 devc->samples_per_event = 16 / devc->num_probes;
655 devc->state.state = SIGMA_IDLE;
661 * In 100 and 200 MHz mode, only a single pin rising/falling can be
662 * set as trigger. In other modes, two rising/falling triggers can be set,
663 * in addition to value/mask trigger for any number of probes.
665 * The Sigma supports complex triggers using boolean expressions, but this
666 * has not been implemented yet.
668 static int configure_probes(const struct sr_dev_inst *sdi)
670 struct dev_context *devc = sdi->priv;
671 const struct sr_probe *probe;
676 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
678 for (l = sdi->probes; l; l = l->next) {
679 probe = (struct sr_probe *)l->data;
680 probebit = 1 << (probe->index);
682 if (!probe->enabled || !probe->trigger)
685 if (devc->cur_samplerate >= SR_MHZ(100)) {
686 /* Fast trigger support. */
688 sr_err("Only a single pin trigger in 100 and "
689 "200MHz mode is supported.");
692 if (probe->trigger[0] == 'f')
693 devc->trigger.fallingmask |= probebit;
694 else if (probe->trigger[0] == 'r')
695 devc->trigger.risingmask |= probebit;
697 sr_err("Only rising/falling trigger in 100 "
698 "and 200MHz mode is supported.");
704 /* Simple trigger support (event). */
705 if (probe->trigger[0] == '1') {
706 devc->trigger.simplevalue |= probebit;
707 devc->trigger.simplemask |= probebit;
709 else if (probe->trigger[0] == '0') {
710 devc->trigger.simplevalue &= ~probebit;
711 devc->trigger.simplemask |= probebit;
713 else if (probe->trigger[0] == 'f') {
714 devc->trigger.fallingmask |= probebit;
717 else if (probe->trigger[0] == 'r') {
718 devc->trigger.risingmask |= probebit;
723 * Actually, Sigma supports 2 rising/falling triggers,
724 * but they are ORed and the current trigger syntax
725 * does not permit ORed triggers.
727 if (trigger_set > 1) {
728 sr_err("Only 1 rising/falling trigger "
735 devc->use_triggers = 1;
741 static int hw_dev_close(struct sr_dev_inst *sdi)
743 struct dev_context *devc;
748 if (sdi->status == SR_ST_ACTIVE)
749 ftdi_usb_close(&devc->ftdic);
751 sdi->status = SR_ST_INACTIVE;
756 static int hw_cleanup(void)
766 static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi)
768 struct dev_context *devc;
771 case SR_CONF_SAMPLERATE:
774 *data = g_variant_new_uint64(devc->cur_samplerate);
785 static int config_set(int id, GVariant *data, const struct sr_dev_inst *sdi)
787 struct dev_context *devc;
790 if (sdi->status != SR_ST_ACTIVE)
791 return SR_ERR_DEV_CLOSED;
795 if (id == SR_CONF_SAMPLERATE) {
796 ret = set_samplerate(sdi, g_variant_get_uint64(data));
797 } else if (id == SR_CONF_LIMIT_MSEC) {
798 devc->limit_msec = g_variant_get_uint64(data);
799 if (devc->limit_msec > 0)
803 } else if (id == SR_CONF_CAPTURE_RATIO) {
804 devc->capture_ratio = g_variant_get_uint64(data);
805 if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
816 static int config_list(int key, GVariant **data, const struct sr_dev_inst *sdi)
824 case SR_CONF_DEVICE_OPTIONS:
825 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
826 hwcaps, ARRAY_SIZE(hwcaps), sizeof(int32_t));
828 case SR_CONF_SAMPLERATE:
829 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
830 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
831 ARRAY_SIZE(samplerates), sizeof(uint64_t));
832 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
833 *data = g_variant_builder_end(&gvb);
835 case SR_CONF_TRIGGER_TYPE:
836 *data = g_variant_new_string(TRIGGER_TYPE);
845 /* Software trigger to determine exact trigger position. */
846 static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
847 struct sigma_trigger *t)
851 for (i = 0; i < 8; ++i) {
853 last_sample = samples[i-1];
855 /* Simple triggers. */
856 if ((samples[i] & t->simplemask) != t->simplevalue)
860 if ((last_sample & t->risingmask) != 0 || (samples[i] &
861 t->risingmask) != t->risingmask)
865 if ((last_sample & t->fallingmask) != t->fallingmask ||
866 (samples[i] & t->fallingmask) != 0)
872 /* If we did not match, return original trigger pos. */
877 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
878 * Each event is 20ns apart, and can contain multiple samples.
880 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
881 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
882 * For 50 MHz and below, events contain one sample for each channel,
883 * spread 20 ns apart.
885 static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
886 uint16_t *lastsample, int triggerpos,
887 uint16_t limit_chunk, void *cb_data)
889 struct sr_dev_inst *sdi = cb_data;
890 struct dev_context *devc = sdi->priv;
892 uint16_t samples[65536 * devc->samples_per_event];
893 struct sr_datafeed_packet packet;
894 struct sr_datafeed_logic logic;
895 int i, j, k, l, numpad, tosend;
896 size_t n = 0, sent = 0;
897 int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
902 /* Check if trigger is in this chunk. */
903 if (triggerpos != -1) {
904 if (devc->cur_samplerate <= SR_MHZ(50))
905 triggerpos -= EVENTS_PER_CLUSTER - 1;
910 /* Find in which cluster the trigger occured. */
911 triggerts = triggerpos / 7;
915 for (i = 0; i < 64; ++i) {
916 ts = *(uint16_t *) &buf[i * 16];
917 tsdiff = ts - *lastts;
920 /* Decode partial chunk. */
921 if (limit_chunk && ts > limit_chunk)
924 /* Pad last sample up to current point. */
925 numpad = tsdiff * devc->samples_per_event - clustersize;
927 for (j = 0; j < numpad; ++j)
928 samples[j] = *lastsample;
933 /* Send samples between previous and this timestamp to sigrok. */
936 tosend = MIN(2048, n - sent);
938 packet.type = SR_DF_LOGIC;
939 packet.payload = &logic;
940 logic.length = tosend * sizeof(uint16_t);
942 logic.data = samples + sent;
943 sr_session_send(devc->cb_data, &packet);
949 event = (uint16_t *) &buf[i * 16 + 2];
952 /* For each event in cluster. */
953 for (j = 0; j < 7; ++j) {
955 /* For each sample in event. */
956 for (k = 0; k < devc->samples_per_event; ++k) {
959 /* For each probe. */
960 for (l = 0; l < devc->num_probes; ++l)
961 cur_sample |= (!!(event[j] & (1 << (l *
962 devc->samples_per_event + k)))) << l;
964 samples[n++] = cur_sample;
968 /* Send data up to trigger point (if triggered). */
970 if (i == triggerts) {
972 * Trigger is not always accurate to sample because of
973 * pipeline delay. However, it always triggers before
974 * the actual event. We therefore look at the next
975 * samples to pinpoint the exact position of the trigger.
977 tosend = get_trigger_offset(samples, *lastsample,
981 packet.type = SR_DF_LOGIC;
982 packet.payload = &logic;
983 logic.length = tosend * sizeof(uint16_t);
985 logic.data = samples;
986 sr_session_send(devc->cb_data, &packet);
991 /* Only send trigger if explicitly enabled. */
992 if (devc->use_triggers) {
993 packet.type = SR_DF_TRIGGER;
994 sr_session_send(devc->cb_data, &packet);
998 /* Send rest of the chunk to sigrok. */
1002 packet.type = SR_DF_LOGIC;
1003 packet.payload = &logic;
1004 logic.length = tosend * sizeof(uint16_t);
1006 logic.data = samples + sent;
1007 sr_session_send(devc->cb_data, &packet);
1010 *lastsample = samples[n - 1];
1016 static int receive_data(int fd, int revents, void *cb_data)
1018 struct sr_dev_inst *sdi = cb_data;
1019 struct dev_context *devc = sdi->priv;
1020 struct sr_datafeed_packet packet;
1021 const int chunks_per_read = 32;
1022 unsigned char buf[chunks_per_read * CHUNK_SIZE];
1023 int bufsz, numchunks, i, newchunks;
1024 uint64_t running_msec;
1030 /* Get the current position. */
1031 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1033 numchunks = (devc->state.stoppos + 511) / 512;
1035 if (devc->state.state == SIGMA_IDLE)
1038 if (devc->state.state == SIGMA_CAPTURE) {
1039 /* Check if the timer has expired, or memory is full. */
1040 gettimeofday(&tv, 0);
1041 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1042 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1044 if (running_msec < devc->limit_msec && numchunks < 32767)
1045 return TRUE; /* While capturing... */
1047 hw_dev_acquisition_stop(sdi, sdi);
1051 if (devc->state.state == SIGMA_DOWNLOAD) {
1052 if (devc->state.chunks_downloaded >= numchunks) {
1053 /* End of samples. */
1054 packet.type = SR_DF_END;
1055 sr_session_send(devc->cb_data, &packet);
1057 devc->state.state = SIGMA_IDLE;
1062 newchunks = MIN(chunks_per_read,
1063 numchunks - devc->state.chunks_downloaded);
1065 sr_info("Downloading sample data: %.0f %%.",
1066 100.0 * devc->state.chunks_downloaded / numchunks);
1068 bufsz = sigma_read_dram(devc->state.chunks_downloaded,
1069 newchunks, buf, devc);
1070 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1073 /* Find first ts. */
1074 if (devc->state.chunks_downloaded == 0) {
1075 devc->state.lastts = *(uint16_t *) buf - 1;
1076 devc->state.lastsample = 0;
1079 /* Decode chunks and send them to sigrok. */
1080 for (i = 0; i < newchunks; ++i) {
1081 int limit_chunk = 0;
1083 /* The last chunk may potentially be only in part. */
1084 if (devc->state.chunks_downloaded == numchunks - 1) {
1085 /* Find the last valid timestamp */
1086 limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
1089 if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
1090 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1091 &devc->state.lastts,
1092 &devc->state.lastsample,
1093 devc->state.triggerpos & 0x1ff,
1096 decode_chunk_ts(buf + (i * CHUNK_SIZE),
1097 &devc->state.lastts,
1098 &devc->state.lastsample,
1099 -1, limit_chunk, sdi);
1101 ++devc->state.chunks_downloaded;
1108 /* Build a LUT entry used by the trigger functions. */
1109 static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1113 /* For each quad probe. */
1114 for (i = 0; i < 4; ++i) {
1117 /* For each bit in LUT. */
1118 for (j = 0; j < 16; ++j)
1120 /* For each probe in quad. */
1121 for (k = 0; k < 4; ++k) {
1122 bit = 1 << (i * 4 + k);
1124 /* Set bit in entry */
1126 ((!(value & bit)) !=
1128 entry[i] &= ~(1 << j);
1133 /* Add a logical function to LUT mask. */
1134 static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1135 int index, int neg, uint16_t *mask)
1138 int x[2][2], tmp, a, b, aset, bset, rset;
1140 memset(x, 0, 4 * sizeof(int));
1142 /* Trigger detect condition. */
1172 case OP_NOTRISEFALL:
1178 /* Transpose if neg is set. */
1180 for (i = 0; i < 2; ++i) {
1181 for (j = 0; j < 2; ++j) {
1183 x[i][j] = x[1-i][1-j];
1189 /* Update mask with function. */
1190 for (i = 0; i < 16; ++i) {
1191 a = (i >> (2 * index + 0)) & 1;
1192 b = (i >> (2 * index + 1)) & 1;
1194 aset = (*mask >> i) & 1;
1197 if (func == FUNC_AND || func == FUNC_NAND)
1199 else if (func == FUNC_OR || func == FUNC_NOR)
1201 else if (func == FUNC_XOR || func == FUNC_NXOR)
1204 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1215 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1216 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1217 * set at any time, but a full mask and value can be set (0/1).
1219 static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1222 uint16_t masks[2] = { 0, 0 };
1224 memset(lut, 0, sizeof(struct triggerlut));
1226 /* Contant for simple triggers. */
1229 /* Value/mask trigger support. */
1230 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1233 /* Rise/fall trigger support. */
1234 for (i = 0, j = 0; i < 16; ++i) {
1235 if (devc->trigger.risingmask & (1 << i) ||
1236 devc->trigger.fallingmask & (1 << i))
1237 masks[j++] = 1 << i;
1240 build_lut_entry(masks[0], masks[0], lut->m0d);
1241 build_lut_entry(masks[1], masks[1], lut->m1d);
1243 /* Add glue logic */
1244 if (masks[0] || masks[1]) {
1245 /* Transition trigger. */
1246 if (masks[0] & devc->trigger.risingmask)
1247 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1248 if (masks[0] & devc->trigger.fallingmask)
1249 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1250 if (masks[1] & devc->trigger.risingmask)
1251 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1252 if (masks[1] & devc->trigger.fallingmask)
1253 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1255 /* Only value/mask trigger. */
1259 /* Triggertype: event. */
1260 lut->params.selres = 3;
1265 static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
1268 struct dev_context *devc;
1269 struct clockselect_50 clockselect;
1270 int frac, triggerpin, ret;
1271 uint8_t triggerselect = 0;
1272 struct triggerinout triggerinout_conf;
1273 struct triggerlut lut;
1275 if (sdi->status != SR_ST_ACTIVE)
1276 return SR_ERR_DEV_CLOSED;
1280 if (configure_probes(sdi) != SR_OK) {
1281 sr_err("Failed to configure probes.");
1285 /* If the samplerate has not been set, default to 200 kHz. */
1286 if (devc->cur_firmware == -1) {
1287 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1291 /* Enter trigger programming mode. */
1292 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1294 /* 100 and 200 MHz mode. */
1295 if (devc->cur_samplerate >= SR_MHZ(100)) {
1296 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1298 /* Find which pin to trigger on from mask. */
1299 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1300 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1304 /* Set trigger pin and light LED on trigger. */
1305 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1307 /* Default rising edge. */
1308 if (devc->trigger.fallingmask)
1309 triggerselect |= 1 << 3;
1311 /* All other modes. */
1312 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1313 build_basic_trigger(&lut, devc);
1315 sigma_write_trigger_lut(&lut, devc);
1317 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1320 /* Setup trigger in and out pins to default values. */
1321 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1322 triggerinout_conf.trgout_bytrigger = 1;
1323 triggerinout_conf.trgout_enable = 1;
1325 sigma_write_register(WRITE_TRIGGER_OPTION,
1326 (uint8_t *) &triggerinout_conf,
1327 sizeof(struct triggerinout), devc);
1329 /* Go back to normal mode. */
1330 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1332 /* Set clock select register. */
1333 if (devc->cur_samplerate == SR_MHZ(200))
1334 /* Enable 4 probes. */
1335 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1336 else if (devc->cur_samplerate == SR_MHZ(100))
1337 /* Enable 8 probes. */
1338 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1341 * 50 MHz mode (or fraction thereof). Any fraction down to
1342 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1344 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1346 clockselect.async = 0;
1347 clockselect.fraction = frac;
1348 clockselect.disabled_probes = 0;
1350 sigma_write_register(WRITE_CLOCK_SELECT,
1351 (uint8_t *) &clockselect,
1352 sizeof(clockselect), devc);
1355 /* Setup maximum post trigger time. */
1356 sigma_set_register(WRITE_POST_TRIGGER,
1357 (devc->capture_ratio * 255) / 100, devc);
1359 /* Start acqusition. */
1360 gettimeofday(&devc->start_tv, 0);
1361 sigma_set_register(WRITE_MODE, 0x0d, devc);
1363 devc->cb_data = cb_data;
1365 /* Send header packet to the session bus. */
1366 std_session_send_df_header(cb_data, LOG_PREFIX);
1368 /* Add capture source. */
1369 sr_source_add(0, G_IO_IN, 10, receive_data, (void *)sdi);
1371 devc->state.state = SIGMA_CAPTURE;
1376 static int hw_dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1378 struct dev_context *devc;
1383 sr_source_remove(0);
1385 if (!(devc = sdi->priv)) {
1386 sr_err("%s: sdi->priv was NULL", __func__);
1390 /* Stop acquisition. */
1391 sigma_set_register(WRITE_MODE, 0x11, devc);
1393 /* Set SDRAM Read Enable. */
1394 sigma_set_register(WRITE_MODE, 0x02, devc);
1396 /* Get the current position. */
1397 sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
1399 /* Check if trigger has fired. */
1400 modestatus = sigma_get_register(READ_MODE, devc);
1401 if (modestatus & 0x20)
1402 devc->state.triggerchunk = devc->state.triggerpos / 512;
1404 devc->state.triggerchunk = -1;
1406 devc->state.chunks_downloaded = 0;
1408 devc->state.state = SIGMA_DOWNLOAD;
1413 SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1414 .name = "asix-sigma",
1415 .longname = "ASIX SIGMA/SIGMA2",
1418 .cleanup = hw_cleanup,
1420 .dev_list = hw_dev_list,
1421 .dev_clear = clear_instances,
1422 .config_get = config_get,
1423 .config_set = config_set,
1424 .config_list = config_list,
1425 .dev_open = hw_dev_open,
1426 .dev_close = hw_dev_close,
1427 .dev_acquisition_start = hw_dev_acquisition_start,
1428 .dev_acquisition_stop = hw_dev_acquisition_stop,