2 * This file is part of the sigrok project.
4 * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
5 * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
8 * Redistribution and use in source and binary forms, with or
9 * without modification, are permitted provided that the following
12 * * Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
15 * * Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGE.
35 #include "libsigrok-internal.h"
38 HARD_DATA_CHECK_SUM = 0x00,
46 FREQUENCY_REG0 = 0x30,
54 TRIGGER_STATUS0 = 0x40,
64 TRIGGER_COUNT0 = 0x50,
67 TRIGGER_LEVEL0 = 0x55,
72 RAMSIZE_TRIGGERBAR_ADDRESS0 = 0x60,
73 RAMSIZE_TRIGGERBAR_ADDRESS1,
74 RAMSIZE_TRIGGERBAR_ADDRESS2,
83 ENABLE_DELAY_TIME0 = 0x7a,
86 ENABLE_INSERT_DATA0 = 0x80,
93 TRIGGER_ADDRESS0 = 0x90,
101 STOP_ADDRESS0 = 0x9b,
105 READ_RAM_STATUS = 0xa0,
108 static int g_trigger_status[9] = { 0 };
109 static int g_trigger_count = 1;
110 static int g_filter_status[8] = { 0 };
111 static int g_filter_enable = 0;
113 static int g_freq_value = 100;
114 static int g_freq_scale = FREQ_SCALE_MHZ;
115 static int g_memory_size = MEMORY_SIZE_512K;
116 static int g_ramsize_triggerbar_addr = 0x80000 >> 2;
117 static int g_triggerbar_addr = 0x3fe;
118 static int g_compression = COMPRESSION_NONE;
120 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
121 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
125 return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
128 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
130 int reg0 = 0, divisor = 0, reg2 = 0;
133 case FREQ_SCALE_MHZ: /* MHz */
134 if (freq >= 100 && freq <= 200) {
140 if (freq >= 50 && freq < 100) {
146 if (freq >= 10 && freq < 50) {
159 if (freq >= 2 && freq < 10) {
175 case FREQ_SCALE_HZ: /* Hz */
176 if (freq >= 500 && freq < 1000) {
182 if (freq >= 300 && freq < 500) {
183 reg0 = freq * 0.005 * 8;
188 if (freq >= 100 && freq < 300) {
189 reg0 = freq * 0.005 * 16;
198 case FREQ_SCALE_KHZ: /* kHz */
199 if (freq >= 500 && freq < 1000) {
205 if (freq >= 100 && freq < 500) {
211 if (freq >= 50 && freq < 100) {
217 if (freq >= 10 && freq < 50) {
229 if (freq >= 2 && freq < 10) {
246 sr_dbg("zp: Setting samplerate regs (freq=%d, scale=%d): "
247 "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
248 freq, scale, divisor, reg0, 0x02, reg2);
250 if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
251 return -1; /* Divisor maybe? */
253 if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
254 return -1; /* 10 / 0.2 */
256 if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
257 return -1; /* Always 2 */
259 if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
265 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
266 unsigned int address)
268 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
269 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
270 gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
273 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
274 unsigned int address)
276 gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
277 gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
278 gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
281 static void __analyzer_set_compression(libusb_device_handle *devh,
284 gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
285 gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
288 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
291 gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
292 gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
295 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
297 gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
298 gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
299 gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
300 gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
303 static void analyzer_set_filter(libusb_device_handle *devh)
306 gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
307 for (i = 0; i < 8; i++)
308 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
311 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
313 analyzer_write_status(devh, 3, STATUS_FLAG_NONE); // reset device
314 analyzer_write_status(devh, 3, STATUS_FLAG_RESET); // reset device
317 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
319 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
320 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
321 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
324 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
328 status = gl_reg_read(devh, DEV_STATUS);
329 if ((status & set) && ((status & unset) == 0))
334 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
338 analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
340 for (i = 0; i < 8; i++)
341 (void)gl_reg_read(devh, READ_RAM_STATUS);
344 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
347 return gl_read_bulk(devh, buffer, size);
350 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
352 analyzer_write_status(devh, 3, STATUS_FLAG_20);
353 analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
356 SR_PRIV void analyzer_start(libusb_device_handle *devh)
358 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
359 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
360 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
361 analyzer_write_status(devh, 1, STATUS_FLAG_GO);
364 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
368 /* Write_Start_Status */
369 analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
370 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
372 /* Start_Config_Outside_Device ? */
373 analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
374 analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
376 /* SetData_To_Frequence_Reg */
377 __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
379 /* SetMemory_Length */
380 gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
382 /* Sele_Inside_Outside_Clock */
383 gl_reg_write(devh, CLOCK_SOURCE, 0x03);
385 /* Set_Trigger_Status */
386 for (i = 0; i < 9; i++)
387 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
389 __analyzer_set_trigger_count(devh, g_trigger_count);
391 /* Set_Trigger_Level */
392 gl_reg_write(devh, TRIGGER_LEVEL0, 0x31);
393 gl_reg_write(devh, TRIGGER_LEVEL1, 0x31);
394 gl_reg_write(devh, TRIGGER_LEVEL2, 0x31);
395 gl_reg_write(devh, TRIGGER_LEVEL3, 0x31);
397 /* Size of actual memory >> 2 */
398 __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
399 __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
401 /* Set_Dont_Care_TriggerBar */
402 gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
405 analyzer_set_filter(devh);
407 /* Set_Enable_Delay_Time */
408 gl_reg_write(devh, 0x7a, 0x00);
409 gl_reg_write(devh, 0x7b, 0x00);
410 analyzer_write_enable_insert_data(devh);
411 __analyzer_set_compression(devh, g_compression);
414 SR_PRIV void analyzer_add_trigger(int channel, int type)
418 if ((channel & 0xf) >= 8)
421 if (type == TRIGGER_HIGH || type == TRIGGER_LOW) {
422 if (channel & CHANNEL_A)
424 else if (channel & CHANNEL_B)
426 else if (channel & CHANNEL_C)
428 else if (channel & CHANNEL_D)
432 if ((channel & 0xf) >= 4) {
436 g_trigger_status[i] |=
437 1 << ((2 * channel) + (type == TRIGGER_LOW ? 1 : 0));
439 if (type == TRIGGER_POSEDGE)
440 g_trigger_status[8] = 0x40;
441 else if (type == TRIGGER_NEGEDGE)
442 g_trigger_status[8] = 0x80;
444 g_trigger_status[8] = 0xc0;
446 /* FIXME: Just guessed the index; need to verify. */
447 if (channel & CHANNEL_B)
448 g_trigger_status[8] += 8;
449 else if (channel & CHANNEL_C)
450 g_trigger_status[8] += 16;
451 else if (channel & CHANNEL_D)
452 g_trigger_status[8] += 24;
453 g_trigger_status[8] += channel % 8;
457 SR_PRIV void analyzer_add_filter(int channel, int type)
461 if (type != FILTER_HIGH && type != FILTER_LOW)
463 if ((channel & 0xf) >= 8)
466 if (channel & CHANNEL_A)
468 else if (channel & CHANNEL_B)
470 else if (channel & CHANNEL_C)
472 else if (channel & CHANNEL_D)
477 if ((channel & 0xf) >= 4) {
482 g_filter_status[i] |=
483 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
488 SR_PRIV void analyzer_set_trigger_count(int count)
490 g_trigger_count = count;
493 SR_PRIV void analyzer_set_freq(int freq, int scale)
496 g_freq_scale = scale;
499 SR_PRIV void analyzer_set_memory_size(unsigned int size)
501 g_memory_size = size;
504 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
506 g_ramsize_triggerbar_addr = address;
509 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
511 g_triggerbar_addr = address;
514 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
516 return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
519 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
521 return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
522 STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
525 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
527 return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
528 NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
531 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
533 return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
534 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
537 SR_PRIV void analyzer_set_compression(unsigned int type)
539 g_compression = type;
542 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
544 analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
547 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
549 analyzer_wait(devh, STATUS_READY | 8, STATUS_BUSY);
552 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
553 void *output, unsigned int output_len)
555 unsigned char *in = input;
556 unsigned char *out = output;
557 unsigned int A, B, C, count;
558 unsigned int written = 0;
560 while (input_len > 0) {
566 if (count > output_len)
575 *out++ = 0; /* Channel D */