[libsigrok.git] / src / hardware / sysclk-lwla / protocol.h

/*
 * This file is part of the libsigrok project.
 *
 * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H

#define LOG_PREFIX "sysclk-lwla"

#include <stdint.h>
#include <libusb.h>
#include <glib.h>
#include <libsigrok/libsigrok.h>
#include <libsigrok-internal.h>

/* Maximum configurable sample count limit.
 * Due to compression, there is no meaningful hardware limit the driver
 * could report. So this value is less than 2^64-1 for no reason other
 * than to safeguard against integer overflows.
 */
#define MAX_LIMIT_SAMPLES	(UINT64_C(1000) * 1000 * 1000 * 1000)

/* Maximum configurable acquisition time limit.
 * Due to compression, there is no hardware limit that would be meaningful
 * in practice. However, the LWLA1016 reports the elapsed time as a 32-bit
 * value, so keep this below 2^32.
 */
#define MAX_LIMIT_MSEC		(1000 * 1000 * 1000)

struct acquisition_state;

/* USB vendor and product IDs. */
enum {
	USB_VID_SYSCLK   = 0x2961,
	USB_PID_LWLA1016 = 0x6688,
	USB_PID_LWLA1034 = 0x6689,
};

/* USB device characteristics. */
enum {
	USB_CONFIG	= 1,
	USB_INTERFACE	= 0,
	USB_TIMEOUT_MS	= 1000,
};

/** USB device end points. */
enum usb_endpoint {
	EP_COMMAND = 2,
	EP_CONFIG  = 4,
	EP_REPLY   = 6 | LIBUSB_ENDPOINT_IN
};

/** LWLA1034 clock sources. */
enum clock_source {
	CLOCK_INTERNAL = 0,
	CLOCK_EXT_CLK,
};

/** LWLA1034 trigger sources. */
enum trigger_source {
	TRIGGER_CHANNELS = 0,
	TRIGGER_EXT_TRG,
};

/** Edge choices for the LWLA1034 external clock and trigger inputs. */
enum signal_edge {
	EDGE_POSITIVE = 0,
	EDGE_NEGATIVE,
};

/* Common indicator for no or unknown FPGA config. */
enum {
	FPGA_NOCONF = -1,
};

/** Acquisition protocol states. */
enum protocol_state {
	/* idle states */
	STATE_IDLE = 0,
	STATE_STATUS_WAIT,
	/* device command states */
	STATE_START_CAPTURE,
	STATE_STOP_CAPTURE,
	STATE_READ_PREPARE,
	STATE_READ_FINISH,
	/* command followed by response */
	STATE_EXPECT_RESPONSE = 1 << 3,
	STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE,
	STATE_LENGTH_REQUEST,
	STATE_READ_REQUEST,
};

struct dev_context {
	uint64_t samplerate;	/* requested samplerate */
	uint64_t limit_msec;	/* requested capture duration in ms */
	uint64_t limit_samples;	/* requested capture length in samples */

	uint64_t channel_mask;		/* bit mask of enabled channels */
	uint64_t trigger_mask;		/* trigger enable mask */
	uint64_t trigger_edge_mask;	/* trigger type mask */
	uint64_t trigger_values;	/* trigger level/slope bits */

	const struct model_info *model;		/* device model descriptor */
	struct acquisition_state *acquisition;	/* running capture state */
	int active_fpga_config;			/* FPGA configuration index */
	gboolean short_transfer_quirk;		/* 64 bytes response limit */

	enum protocol_state state;	/* async protocol state */
	gboolean cancel_requested;	/* stop after current transfer */
	gboolean transfer_error;	/* error during device communication */

	gboolean cfg_rle;			/* RLE compression setting */
	enum clock_source cfg_clock_source;	/* clock source setting */
	enum signal_edge cfg_clock_edge;	/* ext clock edge setting */
	enum trigger_source cfg_trigger_source;	/* trigger source setting */
	enum signal_edge cfg_trigger_slope;	/* ext trigger slope setting */
};

/** LWLA model descriptor. */
struct model_info {
	char name[12];
	int num_channels;

	unsigned int num_devopts;
	uint32_t devopts[8];

	unsigned int num_samplerates;
	uint64_t samplerates[20];

	int (*apply_fpga_config)(const struct sr_dev_inst *sdi);
	int (*device_init_check)(const struct sr_dev_inst *sdi);
	int (*setup_acquisition)(const struct sr_dev_inst *sdi);

	int (*prepare_request)(const struct sr_dev_inst *sdi);
	int (*handle_response)(const struct sr_dev_inst *sdi);
};

extern SR_PRIV const struct model_info lwla1016_info;
extern SR_PRIV const struct model_info lwla1034_info;

SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);

#endif
Commit	Line	Data
	1	/*
	2	* This file is part of the libsigrok project.
	3	*
	4	* Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com>
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation, either version 3 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	21	#define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H
	22
	23	#define LOG_PREFIX "sysclk-lwla"
	24
	25	#include <stdint.h>
	26	#include <libusb.h>
	27	#include <glib.h>
	28	#include <libsigrok/libsigrok.h>
	29	#include <libsigrok-internal.h>
	30
	31	/* Maximum configurable sample count limit.
	32	* Due to compression, there is no meaningful hardware limit the driver
	33	* could report. So this value is less than 2^64-1 for no reason other
	34	* than to safeguard against integer overflows.
	35	*/
	36	#define MAX_LIMIT_SAMPLES (UINT64_C(1000) * 1000 * 1000 * 1000)
	37
	38	/* Maximum configurable acquisition time limit.
	39	* Due to compression, there is no hardware limit that would be meaningful
	40	* in practice. However, the LWLA1016 reports the elapsed time as a 32-bit
	41	* value, so keep this below 2^32.
	42	*/
	43	#define MAX_LIMIT_MSEC (1000 * 1000 * 1000)
	44
	45	struct acquisition_state;
	46
	47	/* USB vendor and product IDs. */
	48	enum {
	49	USB_VID_SYSCLK = 0x2961,
	50	USB_PID_LWLA1016 = 0x6688,
	51	USB_PID_LWLA1034 = 0x6689,
	52	};
	53
	54	/* USB device characteristics. */
	55	enum {
	56	USB_CONFIG = 1,
	57	USB_INTERFACE = 0,
	58	USB_TIMEOUT_MS = 1000,
	59	};
	60
	61	/** USB device end points. */
	62	enum usb_endpoint {
	63	EP_COMMAND = 2,
	64	EP_CONFIG = 4,
	65	EP_REPLY = 6 \| LIBUSB_ENDPOINT_IN
	66	};
	67
	68	/** LWLA1034 clock sources. */
	69	enum clock_source {
	70	CLOCK_INTERNAL = 0,
	71	CLOCK_EXT_CLK,
	72	};
	73
	74	/** LWLA1034 trigger sources. */
	75	enum trigger_source {
	76	TRIGGER_CHANNELS = 0,
	77	TRIGGER_EXT_TRG,
	78	};
	79
	80	/** Edge choices for the LWLA1034 external clock and trigger inputs. */
	81	enum signal_edge {
	82	EDGE_POSITIVE = 0,
	83	EDGE_NEGATIVE,
	84	};
	85
	86	/* Common indicator for no or unknown FPGA config. */
	87	enum {
	88	FPGA_NOCONF = -1,
	89	};
	90
	91	/** Acquisition protocol states. */
	92	enum protocol_state {
	93	/* idle states */
	94	STATE_IDLE = 0,
	95	STATE_STATUS_WAIT,
	96	/* device command states */
	97	STATE_START_CAPTURE,
	98	STATE_STOP_CAPTURE,
	99	STATE_READ_PREPARE,
	100	STATE_READ_FINISH,
	101	/* command followed by response */
	102	STATE_EXPECT_RESPONSE = 1 << 3,
	103	STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE,
	104	STATE_LENGTH_REQUEST,
	105	STATE_READ_REQUEST,
	106	};
	107
	108	struct dev_context {
	109	uint64_t samplerate; /* requested samplerate */
	110	uint64_t limit_msec; /* requested capture duration in ms */
	111	uint64_t limit_samples; /* requested capture length in samples */
	112
	113	uint64_t channel_mask; /* bit mask of enabled channels */
	114	uint64_t trigger_mask; /* trigger enable mask */
	115	uint64_t trigger_edge_mask; /* trigger type mask */
	116	uint64_t trigger_values; /* trigger level/slope bits */
	117
	118	const struct model_info model; / device model descriptor */
	119	struct acquisition_state acquisition; / running capture state */
	120	int active_fpga_config; /* FPGA configuration index */
	121	gboolean short_transfer_quirk; /* 64 bytes response limit */
	122
	123	enum protocol_state state; /* async protocol state */
	124	gboolean cancel_requested; /* stop after current transfer */
	125	gboolean transfer_error; /* error during device communication */
	126
	127	gboolean cfg_rle; /* RLE compression setting */
	128	enum clock_source cfg_clock_source; /* clock source setting */
	129	enum signal_edge cfg_clock_edge; /* ext clock edge setting */
	130	enum trigger_source cfg_trigger_source; /* trigger source setting */
	131	enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */
	132	};
	133
	134	/** LWLA model descriptor. */
	135	struct model_info {
	136	char name[12];
	137	int num_channels;
	138
	139	unsigned int num_devopts;
	140	uint32_t devopts[8];
	141
	142	unsigned int num_samplerates;
	143	uint64_t samplerates[20];
	144
	145	int (apply_fpga_config)(const struct sr_dev_inst sdi);
	146	int (device_init_check)(const struct sr_dev_inst sdi);
	147	int (setup_acquisition)(const struct sr_dev_inst sdi);
	148
	149	int (prepare_request)(const struct sr_dev_inst sdi);
	150	int (handle_response)(const struct sr_dev_inst sdi);
	151	};
	152
	153	extern SR_PRIV const struct model_info lwla1016_info;
	154	extern SR_PRIV const struct model_info lwla1034_info;
	155
	156	SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi);
	157
	158	#endif