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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2014 Daniel Elstner <daniel.kitta@gmail.com> | |
5 | * | |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 3 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #ifndef LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H | |
21 | #define LIBSIGROK_HARDWARE_SYSCLK_LWLA_PROTOCOL_H | |
22 | ||
23 | #define LOG_PREFIX "sysclk-lwla" | |
24 | ||
25 | #include <stdint.h> | |
26 | #include <glib.h> | |
27 | #include <libsigrok/libsigrok.h> | |
28 | #include <libsigrok-internal.h> | |
29 | ||
30 | #define VENDOR_NAME "SysClk" | |
31 | ||
32 | /* Maximum configurable sample count limit. | |
33 | * Due to compression, there is no meaningful hardware limit the driver | |
34 | * could report. So this value is less than 2^64-1 for no reason other | |
35 | * than to safeguard against integer overflows. | |
36 | */ | |
37 | #define MAX_LIMIT_SAMPLES (UINT64_C(1000) * 1000 * 1000 * 1000) | |
38 | ||
39 | /* Maximum configurable acquisition time limit. | |
40 | * Due to compression, there is no hardware limit that would be meaningful | |
41 | * in practice. However, the LWLA1016 reports the elapsed time as a 32-bit | |
42 | * value, so keep this below 2^32. | |
43 | */ | |
44 | #define MAX_LIMIT_MSEC (1000 * 1000 * 1000) | |
45 | ||
46 | struct acquisition_state; | |
47 | ||
48 | /* USB vendor and product IDs. | |
49 | */ | |
50 | enum { | |
51 | USB_VID_SYSCLK = 0x2961, | |
52 | USB_PID_LWLA1016 = 0x6688, | |
53 | USB_PID_LWLA1034 = 0x6689, | |
54 | }; | |
55 | ||
56 | /* USB device characteristics. | |
57 | */ | |
58 | enum { | |
59 | USB_CONFIG = 1, | |
60 | USB_INTERFACE = 0, | |
61 | USB_TIMEOUT_MS = 3000, | |
62 | }; | |
63 | ||
64 | /** LWLA1034 clock sources. | |
65 | */ | |
66 | enum clock_source { | |
67 | CLOCK_INTERNAL = 0, | |
68 | CLOCK_EXT_CLK, | |
69 | }; | |
70 | ||
71 | /** LWLA1034 trigger sources. | |
72 | */ | |
73 | enum trigger_source { | |
74 | TRIGGER_CHANNELS = 0, | |
75 | TRIGGER_EXT_TRG, | |
76 | }; | |
77 | ||
78 | /** Edge choices for the LWLA1034 external clock and trigger inputs. | |
79 | */ | |
80 | enum signal_edge { | |
81 | EDGE_POSITIVE = 0, | |
82 | EDGE_NEGATIVE, | |
83 | }; | |
84 | ||
85 | /* Common indicator for no or unknown FPGA config. */ | |
86 | enum { | |
87 | FPGA_NOCONF = -1, | |
88 | }; | |
89 | ||
90 | /** Acquisition protocol states. | |
91 | */ | |
92 | enum protocol_state { | |
93 | /* idle states */ | |
94 | STATE_IDLE = 0, | |
95 | STATE_STATUS_WAIT, | |
96 | /* device command states */ | |
97 | STATE_START_CAPTURE, | |
98 | STATE_STOP_CAPTURE, | |
99 | STATE_READ_PREPARE, | |
100 | STATE_READ_FINISH, | |
101 | /* command followed by response */ | |
102 | STATE_EXPECT_RESPONSE = 1 << 3, | |
103 | STATE_STATUS_REQUEST = STATE_EXPECT_RESPONSE, | |
104 | STATE_LENGTH_REQUEST, | |
105 | STATE_READ_REQUEST, | |
106 | }; | |
107 | ||
108 | /** Private, per-device-instance driver context. | |
109 | */ | |
110 | struct dev_context { | |
111 | uint64_t samplerate; /* requested samplerate */ | |
112 | ||
113 | uint64_t limit_msec; /* requested capture duration in ms */ | |
114 | uint64_t limit_samples; /* requested capture length in samples */ | |
115 | ||
116 | uint64_t channel_mask; /* bit mask of enabled channels */ | |
117 | ||
118 | uint64_t trigger_mask; /* trigger enable mask */ | |
119 | uint64_t trigger_edge_mask; /* trigger type mask */ | |
120 | uint64_t trigger_values; /* trigger level/slope bits */ | |
121 | ||
122 | const struct model_info *model; /* device model descriptor */ | |
123 | struct acquisition_state *acquisition; /* running capture state */ | |
124 | int active_fpga_config; /* FPGA configuration index */ | |
125 | ||
126 | enum protocol_state state; /* async protocol state */ | |
127 | gboolean cancel_requested; /* stop after current transfer */ | |
128 | gboolean transfer_error; /* error during device communication */ | |
129 | ||
130 | gboolean cfg_rle; /* RLE compression setting */ | |
131 | enum clock_source cfg_clock_source; /* clock source setting */ | |
132 | enum signal_edge cfg_clock_edge; /* ext clock edge setting */ | |
133 | enum trigger_source cfg_trigger_source; /* trigger source setting */ | |
134 | enum signal_edge cfg_trigger_slope; /* ext trigger slope setting */ | |
135 | ||
136 | }; | |
137 | ||
138 | /** LWLA model descriptor. | |
139 | */ | |
140 | struct model_info { | |
141 | char name[12]; | |
142 | int num_channels; | |
143 | ||
144 | unsigned int num_devopts; | |
145 | uint32_t devopts[8]; | |
146 | ||
147 | unsigned int num_samplerates; | |
148 | uint64_t samplerates[20]; | |
149 | ||
150 | int (*apply_fpga_config)(const struct sr_dev_inst *sdi); | |
151 | int (*device_init_check)(const struct sr_dev_inst *sdi); | |
152 | int (*setup_acquisition)(const struct sr_dev_inst *sdi); | |
153 | ||
154 | int (*prepare_request)(const struct sr_dev_inst *sdi); | |
155 | int (*handle_response)(const struct sr_dev_inst *sdi); | |
156 | }; | |
157 | ||
158 | SR_PRIV const struct model_info lwla1016_info; | |
159 | SR_PRIV const struct model_info lwla1034_info; | |
160 | ||
161 | SR_PRIV int lwla_start_acquisition(const struct sr_dev_inst *sdi); | |
162 | ||
163 | #endif |