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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
6 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include "protocol.h" | |
23 | ||
24 | #include <stdint.h> | |
25 | #include <string.h> | |
26 | #include <glib.h> | |
27 | #include <glib/gstdio.h> | |
28 | #include <stdio.h> | |
29 | #include <errno.h> | |
30 | #include <math.h> | |
31 | #include "libsigrok.h" | |
32 | #include "libsigrok-internal.h" | |
33 | ||
34 | #define FPGA_FIRMWARE_18 FIRMWARE_DIR"/saleae-logic16-fpga-18.bitstream" | |
35 | #define FPGA_FIRMWARE_33 FIRMWARE_DIR"/saleae-logic16-fpga-33.bitstream" | |
36 | ||
37 | #define MAX_SAMPLE_RATE SR_MHZ(100) | |
38 | #define MAX_4CH_SAMPLE_RATE SR_MHZ(50) | |
39 | #define MAX_7CH_SAMPLE_RATE SR_MHZ(40) | |
40 | #define MAX_8CH_SAMPLE_RATE SR_MHZ(32) | |
41 | #define MAX_10CH_SAMPLE_RATE SR_MHZ(25) | |
42 | #define MAX_13CH_SAMPLE_RATE SR_MHZ(16) | |
43 | ||
44 | #define BASE_CLOCK_0_FREQ SR_MHZ(100) | |
45 | #define BASE_CLOCK_1_FREQ SR_MHZ(160) | |
46 | ||
47 | #define COMMAND_START_ACQUISITION 1 | |
48 | #define COMMAND_ABORT_ACQUISITION_ASYNC 2 | |
49 | #define COMMAND_WRITE_EEPROM 6 | |
50 | #define COMMAND_READ_EEPROM 7 | |
51 | #define COMMAND_WRITE_LED_TABLE 0x7a | |
52 | #define COMMAND_SET_LED_MODE 0x7b | |
53 | #define COMMAND_RETURN_TO_BOOTLOADER 0x7c | |
54 | #define COMMAND_ABORT_ACQUISITION_SYNC 0x7d | |
55 | #define COMMAND_FPGA_UPLOAD_INIT 0x7e | |
56 | #define COMMAND_FPGA_UPLOAD_SEND_DATA 0x7f | |
57 | #define COMMAND_FPGA_WRITE_REGISTER 0x80 | |
58 | #define COMMAND_FPGA_READ_REGISTER 0x81 | |
59 | #define COMMAND_GET_REVID 0x82 | |
60 | ||
61 | #define WRITE_EEPROM_COOKIE1 0x42 | |
62 | #define WRITE_EEPROM_COOKIE2 0x55 | |
63 | #define READ_EEPROM_COOKIE1 0x33 | |
64 | #define READ_EEPROM_COOKIE2 0x81 | |
65 | #define ABORT_ACQUISITION_SYNC_PATTERN 0x55 | |
66 | ||
67 | #define MAX_EMPTY_TRANSFERS 64 | |
68 | ||
69 | static void encrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
70 | { | |
71 | uint8_t state1 = 0x9b, state2 = 0x54; | |
72 | uint8_t t, v; | |
73 | int i; | |
74 | ||
75 | for (i = 0; i < cnt; i++) { | |
76 | v = src[i]; | |
77 | t = (((v ^ state2 ^ 0x2b) - 0x05) ^ 0x35) - 0x39; | |
78 | t = (((t ^ state1 ^ 0x5a) - 0xb0) ^ 0x38) - 0x45; | |
79 | dest[i] = state2 = t; | |
80 | state1 = v; | |
81 | } | |
82 | } | |
83 | ||
84 | static void decrypt(uint8_t *dest, const uint8_t *src, uint8_t cnt) | |
85 | { | |
86 | uint8_t state1 = 0x9b, state2 = 0x54; | |
87 | uint8_t t, v; | |
88 | int i; | |
89 | ||
90 | for (i = 0; i < cnt; i++) { | |
91 | v = src[i]; | |
92 | t = (((v + 0x45) ^ 0x38) + 0xb0) ^ 0x5a ^ state1; | |
93 | t = (((t + 0x39) ^ 0x35) + 0x05) ^ 0x2b ^ state2; | |
94 | dest[i] = state1 = t; | |
95 | state2 = v; | |
96 | } | |
97 | } | |
98 | ||
99 | static int do_ep1_command(const struct sr_dev_inst *sdi, | |
100 | const uint8_t *command, uint8_t cmd_len, | |
101 | uint8_t *reply, uint8_t reply_len) | |
102 | { | |
103 | uint8_t buf[64]; | |
104 | struct sr_usb_dev_inst *usb; | |
105 | int ret, xfer; | |
106 | ||
107 | usb = sdi->conn; | |
108 | ||
109 | if (cmd_len < 1 || cmd_len > 64 || reply_len > 64 || | |
110 | command == NULL || (reply_len > 0 && reply == NULL)) | |
111 | return SR_ERR_ARG; | |
112 | ||
113 | encrypt(buf, command, cmd_len); | |
114 | ||
115 | ret = libusb_bulk_transfer(usb->devhdl, 1, buf, cmd_len, &xfer, 1000); | |
116 | if (ret != 0) { | |
117 | sr_dbg("Failed to send EP1 command 0x%02x: %s.", | |
118 | command[0], libusb_error_name(ret)); | |
119 | return SR_ERR; | |
120 | } | |
121 | if (xfer != cmd_len) { | |
122 | sr_dbg("Failed to send EP1 command 0x%02x: incorrect length " | |
123 | "%d != %d.", xfer, cmd_len); | |
124 | return SR_ERR; | |
125 | } | |
126 | ||
127 | if (reply_len == 0) | |
128 | return SR_OK; | |
129 | ||
130 | ret = libusb_bulk_transfer(usb->devhdl, 0x80 | 1, buf, reply_len, | |
131 | &xfer, 1000); | |
132 | if (ret != 0) { | |
133 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: %s.", | |
134 | command[0], libusb_error_name(ret)); | |
135 | return SR_ERR; | |
136 | } | |
137 | if (xfer != reply_len) { | |
138 | sr_dbg("Failed to receive reply to EP1 command 0x%02x: " | |
139 | "incorrect length %d != %d.", xfer, reply_len); | |
140 | return SR_ERR; | |
141 | } | |
142 | ||
143 | decrypt(reply, buf, reply_len); | |
144 | ||
145 | return SR_OK; | |
146 | } | |
147 | ||
148 | static int read_eeprom(const struct sr_dev_inst *sdi, | |
149 | uint8_t address, uint8_t length, uint8_t *buf) | |
150 | { | |
151 | uint8_t command[5] = { | |
152 | COMMAND_READ_EEPROM, | |
153 | READ_EEPROM_COOKIE1, | |
154 | READ_EEPROM_COOKIE2, | |
155 | address, | |
156 | length, | |
157 | }; | |
158 | ||
159 | return do_ep1_command(sdi, command, 5, buf, length); | |
160 | } | |
161 | ||
162 | static int upload_led_table(const struct sr_dev_inst *sdi, | |
163 | const uint8_t *table, uint8_t offset, uint8_t cnt) | |
164 | { | |
165 | uint8_t chunk, command[64]; | |
166 | int ret; | |
167 | ||
168 | if (cnt < 1 || cnt + offset > 64 || table == NULL) | |
169 | return SR_ERR_ARG; | |
170 | ||
171 | while (cnt > 0) { | |
172 | chunk = (cnt > 32 ? 32 : cnt); | |
173 | ||
174 | command[0] = COMMAND_WRITE_LED_TABLE; | |
175 | command[1] = offset; | |
176 | command[2] = chunk; | |
177 | memcpy(command + 3, table, chunk); | |
178 | ||
179 | ret = do_ep1_command(sdi, command, 3 + chunk, NULL, 0); | |
180 | if (ret != SR_OK) | |
181 | return ret; | |
182 | ||
183 | table += chunk; | |
184 | offset += chunk; | |
185 | cnt -= chunk; | |
186 | } | |
187 | ||
188 | return SR_OK; | |
189 | } | |
190 | ||
191 | static int set_led_mode(const struct sr_dev_inst *sdi, | |
192 | uint8_t animate, uint16_t t2reload, uint8_t div, | |
193 | uint8_t repeat) | |
194 | { | |
195 | uint8_t command[6] = { | |
196 | COMMAND_SET_LED_MODE, | |
197 | animate, | |
198 | t2reload & 0xff, | |
199 | t2reload >> 8, | |
200 | div, | |
201 | repeat, | |
202 | }; | |
203 | ||
204 | return do_ep1_command(sdi, command, 6, NULL, 0); | |
205 | } | |
206 | ||
207 | static int read_fpga_register(const struct sr_dev_inst *sdi, | |
208 | uint8_t address, uint8_t *value) | |
209 | { | |
210 | uint8_t command[3] = { | |
211 | COMMAND_FPGA_READ_REGISTER, | |
212 | 1, | |
213 | address, | |
214 | }; | |
215 | ||
216 | return do_ep1_command(sdi, command, 3, value, 1); | |
217 | } | |
218 | ||
219 | static int write_fpga_registers(const struct sr_dev_inst *sdi, | |
220 | uint8_t (*regs)[2], uint8_t cnt) | |
221 | { | |
222 | uint8_t command[64]; | |
223 | int i; | |
224 | ||
225 | if (cnt < 1 || cnt > 31) | |
226 | return SR_ERR_ARG; | |
227 | ||
228 | command[0] = COMMAND_FPGA_WRITE_REGISTER; | |
229 | command[1] = cnt; | |
230 | for (i = 0; i < cnt; i++) { | |
231 | command[2 + 2 * i] = regs[i][0]; | |
232 | command[3 + 2 * i] = regs[i][1]; | |
233 | } | |
234 | ||
235 | return do_ep1_command(sdi, command, 2 * (cnt + 1), NULL, 0); | |
236 | } | |
237 | ||
238 | static int write_fpga_register(const struct sr_dev_inst *sdi, | |
239 | uint8_t address, uint8_t value) | |
240 | { | |
241 | uint8_t regs[2] = { address, value }; | |
242 | ||
243 | return write_fpga_registers(sdi, ®s, 1); | |
244 | } | |
245 | ||
246 | static uint8_t map_eeprom_data(uint8_t v) | |
247 | { | |
248 | return (((v ^ 0x80) + 0x44) ^ 0xd5) + 0x69; | |
249 | } | |
250 | ||
251 | static int prime_fpga(const struct sr_dev_inst *sdi) | |
252 | { | |
253 | uint8_t eeprom_data[16]; | |
254 | uint8_t old_reg_10, version; | |
255 | uint8_t regs[8][2] = { | |
256 | {10, 0x00}, | |
257 | {10, 0x40}, | |
258 | {12, 0}, | |
259 | {10, 0xc0}, | |
260 | {10, 0x40}, | |
261 | {6, 0}, | |
262 | {7, 1}, | |
263 | {7, 0} | |
264 | }; | |
265 | int i, ret; | |
266 | ||
267 | if ((ret = read_eeprom(sdi, 16, 16, eeprom_data)) != SR_OK) | |
268 | return ret; | |
269 | ||
270 | if ((ret = read_fpga_register(sdi, 10, &old_reg_10)) != SR_OK) | |
271 | return ret; | |
272 | ||
273 | regs[0][1] = (old_reg_10 &= 0x7f); | |
274 | regs[1][1] |= old_reg_10; | |
275 | regs[3][1] |= old_reg_10; | |
276 | regs[4][1] |= old_reg_10; | |
277 | ||
278 | for (i = 0; i < 16; i++) { | |
279 | regs[2][1] = eeprom_data[i]; | |
280 | regs[5][1] = map_eeprom_data(eeprom_data[i]); | |
281 | if (i) | |
282 | ret = write_fpga_registers(sdi, ®s[2], 6); | |
283 | else | |
284 | ret = write_fpga_registers(sdi, ®s[0], 8); | |
285 | if (ret != SR_OK) | |
286 | return ret; | |
287 | } | |
288 | ||
289 | if ((ret = write_fpga_register(sdi, 10, old_reg_10)) != SR_OK) | |
290 | return ret; | |
291 | ||
292 | if ((ret = read_fpga_register(sdi, 0, &version)) != SR_OK) | |
293 | return ret; | |
294 | ||
295 | if (version != 0x10 && version != 0x40 && version != 0x41) { | |
296 | sr_err("Unsupported FPGA version: 0x%02x.", version); | |
297 | return SR_ERR; | |
298 | } | |
299 | ||
300 | return SR_OK; | |
301 | } | |
302 | ||
303 | static void make_heartbeat(uint8_t *table, int len) | |
304 | { | |
305 | int i, j; | |
306 | ||
307 | memset(table, 0, len); | |
308 | len >>= 3; | |
309 | for (i = 0; i < 2; i++) | |
310 | for (j = 0; j < len; j++) | |
311 | *table++ = sin(j * M_PI / len) * 255; | |
312 | } | |
313 | ||
314 | static int configure_led(const struct sr_dev_inst *sdi) | |
315 | { | |
316 | uint8_t table[64]; | |
317 | int ret; | |
318 | ||
319 | make_heartbeat(table, 64); | |
320 | if ((ret = upload_led_table(sdi, table, 0, 64)) != SR_OK) | |
321 | return ret; | |
322 | ||
323 | return set_led_mode(sdi, 1, 6250, 0, 1); | |
324 | } | |
325 | ||
326 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
327 | enum voltage_range vrange) | |
328 | { | |
329 | struct dev_context *devc; | |
330 | int offset, chunksize, ret; | |
331 | const char *filename; | |
332 | uint8_t len, buf[256 * 62], command[64]; | |
333 | FILE *fw; | |
334 | ||
335 | devc = sdi->priv; | |
336 | ||
337 | if (devc->cur_voltage_range == vrange) | |
338 | return SR_OK; | |
339 | ||
340 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL) { | |
341 | switch (vrange) { | |
342 | case VOLTAGE_RANGE_18_33_V: | |
343 | filename = FPGA_FIRMWARE_18; | |
344 | break; | |
345 | case VOLTAGE_RANGE_5_V: | |
346 | filename = FPGA_FIRMWARE_33; | |
347 | break; | |
348 | default: | |
349 | sr_err("Unsupported voltage range."); | |
350 | return SR_ERR; | |
351 | } | |
352 | ||
353 | sr_info("Uploading FPGA bitstream at %s.", filename); | |
354 | if ((fw = g_fopen(filename, "rb")) == NULL) { | |
355 | sr_err("Unable to open bitstream file %s for reading: %s.", | |
356 | filename, strerror(errno)); | |
357 | return SR_ERR; | |
358 | } | |
359 | ||
360 | buf[0] = COMMAND_FPGA_UPLOAD_INIT; | |
361 | if ((ret = do_ep1_command(sdi, buf, 1, NULL, 0)) != SR_OK) { | |
362 | fclose(fw); | |
363 | return ret; | |
364 | } | |
365 | ||
366 | while (1) { | |
367 | chunksize = fread(buf, 1, sizeof(buf), fw); | |
368 | if (chunksize == 0) | |
369 | break; | |
370 | ||
371 | for (offset = 0; offset < chunksize; offset += 62) { | |
372 | len = (offset + 62 > chunksize ? | |
373 | chunksize - offset : 62); | |
374 | command[0] = COMMAND_FPGA_UPLOAD_SEND_DATA; | |
375 | command[1] = len; | |
376 | memcpy(command + 2, buf + offset, len); | |
377 | ret = do_ep1_command(sdi, command, len + 2, NULL, 0); | |
378 | if (ret != SR_OK) { | |
379 | fclose(fw); | |
380 | return ret; | |
381 | } | |
382 | } | |
383 | ||
384 | sr_info("Uploaded %d bytes.", chunksize); | |
385 | } | |
386 | fclose(fw); | |
387 | sr_info("FPGA bitstream upload done."); | |
388 | } | |
389 | ||
390 | if ((ret = prime_fpga(sdi)) != SR_OK) | |
391 | return ret; | |
392 | ||
393 | if ((ret = configure_led(sdi)) != SR_OK) | |
394 | return ret; | |
395 | ||
396 | devc->cur_voltage_range = vrange; | |
397 | return SR_OK; | |
398 | } | |
399 | ||
400 | static int abort_acquisition_sync(const struct sr_dev_inst *sdi) | |
401 | { | |
402 | static const uint8_t command[2] = { | |
403 | COMMAND_ABORT_ACQUISITION_SYNC, | |
404 | ABORT_ACQUISITION_SYNC_PATTERN, | |
405 | }; | |
406 | uint8_t reply, expected_reply; | |
407 | int ret; | |
408 | ||
409 | if ((ret = do_ep1_command(sdi, command, 2, &reply, 1)) != SR_OK) | |
410 | return ret; | |
411 | ||
412 | expected_reply = ~command[1]; | |
413 | if (reply != expected_reply) { | |
414 | sr_err("Invalid response for abort acquisition command: " | |
415 | "0x%02x != 0x%02x.", reply, expected_reply); | |
416 | return SR_ERR; | |
417 | } | |
418 | ||
419 | return SR_OK; | |
420 | } | |
421 | ||
422 | SR_PRIV int logic16_setup_acquisition(const struct sr_dev_inst *sdi, | |
423 | uint64_t samplerate, uint16_t channels) | |
424 | { | |
425 | uint8_t clock_select, reg1, reg10; | |
426 | uint64_t div; | |
427 | int i, ret, nchan = 0; | |
428 | struct dev_context *devc; | |
429 | ||
430 | devc = sdi->priv; | |
431 | ||
432 | if (samplerate == 0 || samplerate > MAX_SAMPLE_RATE) { | |
433 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
434 | return SR_ERR; | |
435 | } | |
436 | ||
437 | if (BASE_CLOCK_0_FREQ % samplerate == 0 && | |
438 | (div = BASE_CLOCK_0_FREQ / samplerate) <= 256) { | |
439 | clock_select = 0; | |
440 | } else if (BASE_CLOCK_1_FREQ % samplerate == 0 && | |
441 | (div = BASE_CLOCK_1_FREQ / samplerate) <= 256) { | |
442 | clock_select = 1; | |
443 | } else { | |
444 | sr_err("Unable to sample at %" PRIu64 "Hz.", samplerate); | |
445 | return SR_ERR; | |
446 | } | |
447 | ||
448 | for (i = 0; i < 16; i++) | |
449 | if (channels & (1U << i)) | |
450 | nchan++; | |
451 | ||
452 | if ((nchan >= 13 && samplerate > MAX_13CH_SAMPLE_RATE) || | |
453 | (nchan >= 10 && samplerate > MAX_10CH_SAMPLE_RATE) || | |
454 | (nchan >= 8 && samplerate > MAX_8CH_SAMPLE_RATE) || | |
455 | (nchan >= 7 && samplerate > MAX_7CH_SAMPLE_RATE) || | |
456 | (nchan >= 4 && samplerate > MAX_4CH_SAMPLE_RATE)) { | |
457 | sr_err("Unable to sample at %" PRIu64 "Hz " | |
458 | "with this many channels.", samplerate); | |
459 | return SR_ERR; | |
460 | } | |
461 | ||
462 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
463 | if (ret != SR_OK) | |
464 | return ret; | |
465 | ||
466 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
467 | return ret; | |
468 | ||
469 | /* Ignore FIFO overflow on previous capture */ | |
470 | reg1 &= ~0x20; | |
471 | ||
472 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x08) { | |
473 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x08. " | |
474 | "Proceeding anyway.", reg1); | |
475 | } | |
476 | ||
477 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
478 | return ret; | |
479 | ||
480 | if ((ret = write_fpga_register(sdi, 10, clock_select)) != SR_OK) | |
481 | return ret; | |
482 | ||
483 | if ((ret = write_fpga_register(sdi, 4, (uint8_t)(div - 1))) != SR_OK) | |
484 | return ret; | |
485 | ||
486 | if ((ret = write_fpga_register(sdi, 2, (uint8_t)(channels & 0xff))) != SR_OK) | |
487 | return ret; | |
488 | ||
489 | if ((ret = write_fpga_register(sdi, 3, (uint8_t)(channels >> 8))) != SR_OK) | |
490 | return ret; | |
491 | ||
492 | if ((ret = write_fpga_register(sdi, 1, 0x42)) != SR_OK) | |
493 | return ret; | |
494 | ||
495 | if ((ret = write_fpga_register(sdi, 1, 0x40)) != SR_OK) | |
496 | return ret; | |
497 | ||
498 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
499 | return ret; | |
500 | ||
501 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 != 0x48) { | |
502 | sr_dbg("Invalid state at acquisition setup register 1: 0x%02x != 0x48. " | |
503 | "Proceeding anyway.", reg1); | |
504 | } | |
505 | ||
506 | if ((ret = read_fpga_register(sdi, 10, ®10)) != SR_OK) | |
507 | return ret; | |
508 | ||
509 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg10 != clock_select) { | |
510 | sr_dbg("Invalid state at acquisition setup register 10: 0x%02x != 0x%02x. " | |
511 | "Proceeding anyway.", reg10, clock_select); | |
512 | } | |
513 | ||
514 | return SR_OK; | |
515 | } | |
516 | ||
517 | SR_PRIV int logic16_start_acquisition(const struct sr_dev_inst *sdi) | |
518 | { | |
519 | static const uint8_t command[1] = { | |
520 | COMMAND_START_ACQUISITION, | |
521 | }; | |
522 | int ret; | |
523 | ||
524 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
525 | return ret; | |
526 | ||
527 | return write_fpga_register(sdi, 1, 0x41); | |
528 | } | |
529 | ||
530 | SR_PRIV int logic16_abort_acquisition(const struct sr_dev_inst *sdi) | |
531 | { | |
532 | static const uint8_t command[1] = { | |
533 | COMMAND_ABORT_ACQUISITION_ASYNC, | |
534 | }; | |
535 | int ret; | |
536 | uint8_t reg1, reg8, reg9; | |
537 | struct dev_context *devc; | |
538 | ||
539 | devc = sdi->priv; | |
540 | ||
541 | if ((ret = do_ep1_command(sdi, command, 1, NULL, 0)) != SR_OK) | |
542 | return ret; | |
543 | ||
544 | if ((ret = write_fpga_register(sdi, 1, 0x00)) != SR_OK) | |
545 | return ret; | |
546 | ||
547 | if ((ret = read_fpga_register(sdi, 1, ®1)) != SR_OK) | |
548 | return ret; | |
549 | ||
550 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && (reg1 & ~0x20) != 0x08) { | |
551 | sr_dbg("Invalid state at acquisition stop: 0x%02x != 0x08.", reg1 & ~0x20); | |
552 | return SR_ERR; | |
553 | } | |
554 | ||
555 | if ((ret = read_fpga_register(sdi, 8, ®8)) != SR_OK) | |
556 | return ret; | |
557 | ||
558 | if ((ret = read_fpga_register(sdi, 9, ®9)) != SR_OK) | |
559 | return ret; | |
560 | ||
561 | if (devc->fpga_variant == FPGA_VARIANT_ORIGINAL && reg1 & 0x20) { | |
562 | sr_warn("FIFO overflow, capture data may be truncated."); | |
563 | return SR_ERR; | |
564 | } | |
565 | ||
566 | return SR_OK; | |
567 | } | |
568 | ||
569 | SR_PRIV int logic16_init_device(const struct sr_dev_inst *sdi) | |
570 | { | |
571 | uint8_t version; | |
572 | struct dev_context *devc; | |
573 | int ret; | |
574 | ||
575 | devc = sdi->priv; | |
576 | ||
577 | devc->cur_voltage_range = VOLTAGE_RANGE_UNKNOWN; | |
578 | ||
579 | if ((ret = abort_acquisition_sync(sdi)) != SR_OK) | |
580 | return ret; | |
581 | ||
582 | if ((ret = read_eeprom(sdi, 8, 8, devc->eeprom_data)) != SR_OK) | |
583 | return ret; | |
584 | ||
585 | /* mcupro Saleae16 has firmware pre-stored in FPGA. | |
586 | So, we can query it right away. */ | |
587 | if (read_fpga_register(sdi, 0, &version) == SR_OK && | |
588 | (version == 0x40 || version == 0x41)) { | |
589 | sr_info("mcupro Saleae16 detected."); | |
590 | devc->fpga_variant = FPGA_VARIANT_MCUPRO; | |
591 | } else { | |
592 | sr_info("Original Saleae Logic16 detected."); | |
593 | devc->fpga_variant = FPGA_VARIANT_ORIGINAL; | |
594 | } | |
595 | ||
596 | ret = upload_fpga_bitstream(sdi, devc->selected_voltage_range); | |
597 | if (ret != SR_OK) | |
598 | return ret; | |
599 | ||
600 | return SR_OK; | |
601 | } | |
602 | ||
603 | static void finish_acquisition(struct sr_dev_inst *sdi) | |
604 | { | |
605 | struct sr_datafeed_packet packet; | |
606 | struct dev_context *devc; | |
607 | ||
608 | devc = sdi->priv; | |
609 | ||
610 | /* Terminate session. */ | |
611 | packet.type = SR_DF_END; | |
612 | sr_session_send(devc->cb_data, &packet); | |
613 | ||
614 | /* Remove fds from polling. */ | |
615 | usb_source_remove(sdi->session, devc->ctx); | |
616 | ||
617 | devc->num_transfers = 0; | |
618 | g_free(devc->transfers); | |
619 | g_free(devc->convbuffer); | |
620 | if (devc->stl) { | |
621 | soft_trigger_logic_free(devc->stl); | |
622 | devc->stl = NULL; | |
623 | } | |
624 | } | |
625 | ||
626 | static void free_transfer(struct libusb_transfer *transfer) | |
627 | { | |
628 | struct sr_dev_inst *sdi; | |
629 | struct dev_context *devc; | |
630 | unsigned int i; | |
631 | ||
632 | sdi = transfer->user_data; | |
633 | devc = sdi->priv; | |
634 | ||
635 | g_free(transfer->buffer); | |
636 | transfer->buffer = NULL; | |
637 | libusb_free_transfer(transfer); | |
638 | ||
639 | for (i = 0; i < devc->num_transfers; i++) { | |
640 | if (devc->transfers[i] == transfer) { | |
641 | devc->transfers[i] = NULL; | |
642 | break; | |
643 | } | |
644 | } | |
645 | ||
646 | devc->submitted_transfers--; | |
647 | if (devc->submitted_transfers == 0) | |
648 | finish_acquisition(sdi); | |
649 | } | |
650 | ||
651 | static void resubmit_transfer(struct libusb_transfer *transfer) | |
652 | { | |
653 | int ret; | |
654 | ||
655 | if ((ret = libusb_submit_transfer(transfer)) == LIBUSB_SUCCESS) | |
656 | return; | |
657 | ||
658 | free_transfer(transfer); | |
659 | /* TODO: Stop session? */ | |
660 | ||
661 | sr_err("%s: %s", __func__, libusb_error_name(ret)); | |
662 | } | |
663 | ||
664 | static size_t convert_sample_data(struct dev_context *devc, | |
665 | uint8_t *dest, size_t destcnt, const uint8_t *src, size_t srccnt) | |
666 | { | |
667 | uint16_t *channel_data; | |
668 | int i, cur_channel; | |
669 | size_t ret = 0; | |
670 | uint16_t sample, channel_mask; | |
671 | ||
672 | srccnt /= 2; | |
673 | ||
674 | channel_data = devc->channel_data; | |
675 | cur_channel = devc->cur_channel; | |
676 | ||
677 | while (srccnt--) { | |
678 | sample = src[0] | (src[1] << 8); | |
679 | src += 2; | |
680 | ||
681 | channel_mask = devc->channel_masks[cur_channel]; | |
682 | ||
683 | for (i = 15; i >= 0; --i, sample >>= 1) | |
684 | if (sample & 1) | |
685 | channel_data[i] |= channel_mask; | |
686 | ||
687 | if (++cur_channel == devc->num_channels) { | |
688 | cur_channel = 0; | |
689 | if (destcnt < 16 * 2) { | |
690 | sr_err("Conversion buffer too small!"); | |
691 | break; | |
692 | } | |
693 | memcpy(dest, channel_data, 16 * 2); | |
694 | memset(channel_data, 0, 16 * 2); | |
695 | dest += 16 * 2; | |
696 | ret += 16; | |
697 | destcnt -= 16 * 2; | |
698 | } | |
699 | } | |
700 | ||
701 | devc->cur_channel = cur_channel; | |
702 | ||
703 | return ret; | |
704 | } | |
705 | ||
706 | SR_PRIV void logic16_receive_transfer(struct libusb_transfer *transfer) | |
707 | { | |
708 | gboolean packet_has_error = FALSE; | |
709 | struct sr_datafeed_packet packet; | |
710 | struct sr_datafeed_logic logic; | |
711 | struct sr_dev_inst *sdi; | |
712 | struct dev_context *devc; | |
713 | size_t new_samples, num_samples; | |
714 | int trigger_offset; | |
715 | int pre_trigger_samples; | |
716 | ||
717 | sdi = transfer->user_data; | |
718 | devc = sdi->priv; | |
719 | ||
720 | /* | |
721 | * If acquisition has already ended, just free any queued up | |
722 | * transfer that come in. | |
723 | */ | |
724 | if (devc->sent_samples < 0) { | |
725 | free_transfer(transfer); | |
726 | return; | |
727 | } | |
728 | ||
729 | sr_info("receive_transfer(): status %s received %d bytes.", | |
730 | libusb_error_name(transfer->status), transfer->actual_length); | |
731 | ||
732 | switch (transfer->status) { | |
733 | case LIBUSB_TRANSFER_NO_DEVICE: | |
734 | devc->sent_samples = -2; | |
735 | free_transfer(transfer); | |
736 | return; | |
737 | case LIBUSB_TRANSFER_COMPLETED: | |
738 | case LIBUSB_TRANSFER_TIMED_OUT: /* We may have received some data though. */ | |
739 | break; | |
740 | default: | |
741 | packet_has_error = TRUE; | |
742 | break; | |
743 | } | |
744 | ||
745 | if (transfer->actual_length & 1) { | |
746 | sr_err("Got an odd number of bytes from the device. " | |
747 | "This should not happen."); | |
748 | /* Bail out right away. */ | |
749 | packet_has_error = TRUE; | |
750 | devc->empty_transfer_count = MAX_EMPTY_TRANSFERS; | |
751 | } | |
752 | ||
753 | if (transfer->actual_length == 0 || packet_has_error) { | |
754 | devc->empty_transfer_count++; | |
755 | if (devc->empty_transfer_count > MAX_EMPTY_TRANSFERS) { | |
756 | /* | |
757 | * The FX2 gave up. End the acquisition, the frontend | |
758 | * will work out that the samplecount is short. | |
759 | */ | |
760 | devc->sent_samples = -2; | |
761 | free_transfer(transfer); | |
762 | } else { | |
763 | resubmit_transfer(transfer); | |
764 | } | |
765 | return; | |
766 | } else { | |
767 | devc->empty_transfer_count = 0; | |
768 | } | |
769 | ||
770 | new_samples = convert_sample_data(devc, devc->convbuffer, | |
771 | devc->convbuffer_size, transfer->buffer, transfer->actual_length); | |
772 | ||
773 | if (new_samples > 0) { | |
774 | if (devc->trigger_fired) { | |
775 | /* Send the incoming transfer to the session bus. */ | |
776 | packet.type = SR_DF_LOGIC; | |
777 | packet.payload = &logic; | |
778 | if (devc->limit_samples && | |
779 | new_samples > devc->limit_samples - devc->sent_samples) | |
780 | new_samples = devc->limit_samples - devc->sent_samples; | |
781 | logic.length = new_samples * 2; | |
782 | logic.unitsize = 2; | |
783 | logic.data = devc->convbuffer; | |
784 | sr_session_send(devc->cb_data, &packet); | |
785 | devc->sent_samples += new_samples; | |
786 | } else { | |
787 | trigger_offset = soft_trigger_logic_check(devc->stl, | |
788 | devc->convbuffer, new_samples * 2, &pre_trigger_samples); | |
789 | if (trigger_offset > -1) { | |
790 | devc->sent_samples += pre_trigger_samples; | |
791 | packet.type = SR_DF_LOGIC; | |
792 | packet.payload = &logic; | |
793 | num_samples = new_samples - trigger_offset; | |
794 | if (devc->limit_samples && | |
795 | num_samples > devc->limit_samples - devc->sent_samples) | |
796 | num_samples = devc->limit_samples - devc->sent_samples; | |
797 | logic.length = num_samples * 2; | |
798 | logic.unitsize = 2; | |
799 | logic.data = devc->convbuffer + trigger_offset * 2; | |
800 | sr_session_send(devc->cb_data, &packet); | |
801 | devc->sent_samples += num_samples; | |
802 | ||
803 | devc->trigger_fired = TRUE; | |
804 | } | |
805 | } | |
806 | ||
807 | if (devc->limit_samples && | |
808 | (uint64_t)devc->sent_samples >= devc->limit_samples) { | |
809 | devc->sent_samples = -2; | |
810 | free_transfer(transfer); | |
811 | return; | |
812 | } | |
813 | } | |
814 | ||
815 | resubmit_transfer(transfer); | |
816 | } |