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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2012 Martin Ling <martin-git@earth.li> | |
5 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
6 | * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #include <config.h> | |
23 | #include <stdlib.h> | |
24 | #include <stdarg.h> | |
25 | #include <unistd.h> | |
26 | #include <errno.h> | |
27 | #include <string.h> | |
28 | #include <math.h> | |
29 | #include <ctype.h> | |
30 | #include <time.h> | |
31 | #include <glib.h> | |
32 | #include <libsigrok/libsigrok.h> | |
33 | #include "libsigrok-internal.h" | |
34 | #include "scpi.h" | |
35 | #include "protocol.h" | |
36 | ||
37 | /* | |
38 | * This is a unified protocol driver for the DS1000 and DS2000 series. | |
39 | * | |
40 | * DS1000 support tested with a Rigol DS1102D. | |
41 | * | |
42 | * DS2000 support tested with a Rigol DS2072 using firmware version 01.01.00.02. | |
43 | * | |
44 | * The Rigol DS2000 series scopes try to adhere to the IEEE 488.2 (I think) | |
45 | * standard. If you want to read it - it costs real money... | |
46 | * | |
47 | * Every response from the scope has a linefeed appended because the | |
48 | * standard says so. In principle this could be ignored because sending the | |
49 | * next command clears the output queue of the scope. This driver tries to | |
50 | * avoid doing that because it may cause an error being generated inside the | |
51 | * scope and who knows what bugs the firmware has WRT this. | |
52 | * | |
53 | * Waveform data is transferred in a format called "arbitrary block program | |
54 | * data" specified in IEEE 488.2. See Agilents programming manuals for their | |
55 | * 2000/3000 series scopes for a nice description. | |
56 | * | |
57 | * Each data block from the scope has a header, e.g. "#900000001400". | |
58 | * The '#' marks the start of a block. | |
59 | * Next is one ASCII decimal digit between 1 and 9, this gives the number of | |
60 | * ASCII decimal digits following. | |
61 | * Last are the ASCII decimal digits giving the number of bytes (not | |
62 | * samples!) in the block. | |
63 | * | |
64 | * After this header as many data bytes as indicated follow. | |
65 | * | |
66 | * Each data block has a trailing linefeed too. | |
67 | */ | |
68 | ||
69 | static int parse_int(const char *str, int *ret) | |
70 | { | |
71 | char *e; | |
72 | long tmp; | |
73 | ||
74 | errno = 0; | |
75 | tmp = strtol(str, &e, 10); | |
76 | if (e == str || *e != '\0') { | |
77 | sr_dbg("Failed to parse integer: '%s'", str); | |
78 | return SR_ERR; | |
79 | } | |
80 | if (errno) { | |
81 | sr_dbg("Failed to parse integer: '%s', numerical overflow", str); | |
82 | return SR_ERR; | |
83 | } | |
84 | if (tmp > INT_MAX || tmp < INT_MIN) { | |
85 | sr_dbg("Failed to parse integer: '%s', value to large/small", str); | |
86 | return SR_ERR; | |
87 | } | |
88 | ||
89 | *ret = (int)tmp; | |
90 | return SR_OK; | |
91 | } | |
92 | ||
93 | /* Set the next event to wait for in rigol_ds_receive */ | |
94 | static void rigol_ds_set_wait_event(struct dev_context *devc, enum wait_events event) | |
95 | { | |
96 | if (event == WAIT_STOP) | |
97 | devc->wait_status = 2; | |
98 | else | |
99 | devc->wait_status = 1; | |
100 | devc->wait_event = event; | |
101 | } | |
102 | ||
103 | /* | |
104 | * Waiting for a event will return a timeout after 2 to 3 seconds in order | |
105 | * to not block the application. | |
106 | */ | |
107 | static int rigol_ds_event_wait(const struct sr_dev_inst *sdi, char status1, char status2) | |
108 | { | |
109 | char *buf; | |
110 | struct dev_context *devc; | |
111 | time_t start; | |
112 | ||
113 | if (!(devc = sdi->priv)) | |
114 | return SR_ERR; | |
115 | ||
116 | start = time(NULL); | |
117 | ||
118 | /* | |
119 | * Trigger status may return: | |
120 | * "TD" or "T'D" - triggered | |
121 | * "AUTO" - autotriggered | |
122 | * "RUN" - running | |
123 | * "WAIT" - waiting for trigger | |
124 | * "STOP" - stopped | |
125 | */ | |
126 | ||
127 | if (devc->wait_status == 1) { | |
128 | do { | |
129 | if (time(NULL) - start >= 3) { | |
130 | sr_dbg("Timeout waiting for trigger"); | |
131 | return SR_ERR_TIMEOUT; | |
132 | } | |
133 | ||
134 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) | |
135 | return SR_ERR; | |
136 | } while (buf[0] == status1 || buf[0] == status2); | |
137 | ||
138 | devc->wait_status = 2; | |
139 | } | |
140 | if (devc->wait_status == 2) { | |
141 | do { | |
142 | if (time(NULL) - start >= 3) { | |
143 | sr_dbg("Timeout waiting for trigger"); | |
144 | return SR_ERR_TIMEOUT; | |
145 | } | |
146 | ||
147 | if (sr_scpi_get_string(sdi->conn, ":TRIG:STAT?", &buf) != SR_OK) | |
148 | return SR_ERR; | |
149 | } while (buf[0] != status1 && buf[0] != status2); | |
150 | ||
151 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
152 | } | |
153 | ||
154 | return SR_OK; | |
155 | } | |
156 | ||
157 | /* | |
158 | * For live capture we need to wait for a new trigger event to ensure that | |
159 | * sample data is not returned twice. | |
160 | * | |
161 | * Unfortunately this will never really work because for sufficiently fast | |
162 | * timebases and trigger rates it just can't catch the status changes. | |
163 | * | |
164 | * What would be needed is a trigger event register with autoreset like the | |
165 | * Agilents have. The Rigols don't seem to have anything like this. | |
166 | * | |
167 | * The workaround is to only wait for the trigger when the timebase is slow | |
168 | * enough. Of course this means that for faster timebases sample data can be | |
169 | * returned multiple times, this effect is mitigated somewhat by sleeping | |
170 | * for about one sweep time in that case. | |
171 | */ | |
172 | static int rigol_ds_trigger_wait(const struct sr_dev_inst *sdi) | |
173 | { | |
174 | struct dev_context *devc; | |
175 | long s; | |
176 | ||
177 | if (!(devc = sdi->priv)) | |
178 | return SR_ERR; | |
179 | ||
180 | /* | |
181 | * If timebase < 50 msecs/DIV just sleep about one sweep time except | |
182 | * for really fast sweeps. | |
183 | */ | |
184 | if (devc->timebase < 0.0499) { | |
185 | if (devc->timebase > 0.99e-6) { | |
186 | /* | |
187 | * Timebase * num hor. divs * 85(%) * 1e6(usecs) / 100 | |
188 | * -> 85 percent of sweep time | |
189 | */ | |
190 | s = (devc->timebase * devc->model->series->num_horizontal_divs | |
191 | * 85e6) / 100L; | |
192 | sr_spew("Sleeping for %ld usecs instead of trigger-wait", s); | |
193 | g_usleep(s); | |
194 | } | |
195 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
196 | return SR_OK; | |
197 | } else { | |
198 | return rigol_ds_event_wait(sdi, 'T', 'A'); | |
199 | } | |
200 | } | |
201 | ||
202 | /* Wait for scope to got to "Stop" in single shot mode */ | |
203 | static int rigol_ds_stop_wait(const struct sr_dev_inst *sdi) | |
204 | { | |
205 | return rigol_ds_event_wait(sdi, 'S', 'S'); | |
206 | } | |
207 | ||
208 | /* Check that a single shot acquisition actually succeeded on the DS2000 */ | |
209 | static int rigol_ds_check_stop(const struct sr_dev_inst *sdi) | |
210 | { | |
211 | struct dev_context *devc; | |
212 | struct sr_channel *ch; | |
213 | int tmp; | |
214 | ||
215 | if (!(devc = sdi->priv)) | |
216 | return SR_ERR; | |
217 | ||
218 | ch = devc->channel_entry->data; | |
219 | ||
220 | if (devc->model->series->protocol != PROTOCOL_V3) | |
221 | return SR_OK; | |
222 | ||
223 | if (ch->type == SR_CHANNEL_LOGIC) { | |
224 | if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK) | |
225 | return SR_ERR; | |
226 | } else { | |
227 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
228 | ch->index + 1) != SR_OK) | |
229 | return SR_ERR; | |
230 | } | |
231 | /* Check that the number of samples will be accepted */ | |
232 | if (rigol_ds_config_set(sdi, ":WAV:POIN %d", | |
233 | ch->type == SR_CHANNEL_LOGIC ? | |
234 | devc->digital_frame_size : | |
235 | devc->analog_frame_size) != SR_OK) | |
236 | return SR_ERR; | |
237 | if (sr_scpi_get_int(sdi->conn, "*ESR?", &tmp) != SR_OK) | |
238 | return SR_ERR; | |
239 | /* | |
240 | * If we get an "Execution error" the scope went from "Single" to | |
241 | * "Stop" without actually triggering. There is no waveform | |
242 | * displayed and trying to download one will fail - the scope thinks | |
243 | * it has 1400 samples (like display memory) and the driver thinks | |
244 | * it has a different number of samples. | |
245 | * | |
246 | * In that case just try to capture something again. Might still | |
247 | * fail in interesting ways. | |
248 | * | |
249 | * Ain't firmware fun? | |
250 | */ | |
251 | if (tmp & 0x10) { | |
252 | sr_warn("Single shot acquisition failed, retrying..."); | |
253 | /* Sleep a bit, otherwise the single shot will often fail */ | |
254 | g_usleep(500 * 1000); | |
255 | rigol_ds_config_set(sdi, ":SING"); | |
256 | rigol_ds_set_wait_event(devc, WAIT_STOP); | |
257 | return SR_ERR; | |
258 | } | |
259 | ||
260 | return SR_OK; | |
261 | } | |
262 | ||
263 | /* Wait for enough data becoming available in scope output buffer */ | |
264 | static int rigol_ds_block_wait(const struct sr_dev_inst *sdi) | |
265 | { | |
266 | char *buf; | |
267 | struct dev_context *devc; | |
268 | time_t start; | |
269 | int len; | |
270 | ||
271 | if (!(devc = sdi->priv)) | |
272 | return SR_ERR; | |
273 | ||
274 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
275 | ||
276 | start = time(NULL); | |
277 | ||
278 | do { | |
279 | if (time(NULL) - start >= 3) { | |
280 | sr_dbg("Timeout waiting for data block"); | |
281 | return SR_ERR_TIMEOUT; | |
282 | } | |
283 | ||
284 | /* | |
285 | * The scope copies data really slowly from sample | |
286 | * memory to its output buffer, so try not to bother | |
287 | * it too much with SCPI requests but don't wait too | |
288 | * long for short sample frame sizes. | |
289 | */ | |
290 | g_usleep(devc->analog_frame_size < (15 * 1000) ? (100 * 1000) : (1000 * 1000)); | |
291 | ||
292 | /* "READ,nnnn" (still working) or "IDLE,nnnn" (finished) */ | |
293 | if (sr_scpi_get_string(sdi->conn, ":WAV:STAT?", &buf) != SR_OK) | |
294 | return SR_ERR; | |
295 | ||
296 | if (parse_int(buf + 5, &len) != SR_OK) | |
297 | return SR_ERR; | |
298 | } while (buf[0] == 'R' && len < (1000 * 1000)); | |
299 | } | |
300 | ||
301 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
302 | ||
303 | return SR_OK; | |
304 | } | |
305 | ||
306 | /* Send a configuration setting. */ | |
307 | SR_PRIV int rigol_ds_config_set(const struct sr_dev_inst *sdi, const char *format, ...) | |
308 | { | |
309 | struct dev_context *devc = sdi->priv; | |
310 | va_list args; | |
311 | int ret; | |
312 | ||
313 | va_start(args, format); | |
314 | ret = sr_scpi_send_variadic(sdi->conn, format, args); | |
315 | va_end(args); | |
316 | ||
317 | if (ret != SR_OK) | |
318 | return SR_ERR; | |
319 | ||
320 | if (devc->model->series->protocol == PROTOCOL_V2) { | |
321 | /* The DS1000 series needs this stupid delay, *OPC? doesn't work. */ | |
322 | sr_spew("delay %dms", 100); | |
323 | g_usleep(100 * 1000); | |
324 | return SR_OK; | |
325 | } else { | |
326 | return sr_scpi_get_opc(sdi->conn); | |
327 | } | |
328 | } | |
329 | ||
330 | /* Start capturing a new frameset */ | |
331 | SR_PRIV int rigol_ds_capture_start(const struct sr_dev_inst *sdi) | |
332 | { | |
333 | struct dev_context *devc; | |
334 | gchar *trig_mode; | |
335 | unsigned int num_channels, i, j; | |
336 | int buffer_samples; | |
337 | ||
338 | if (!(devc = sdi->priv)) | |
339 | return SR_ERR; | |
340 | ||
341 | if (devc->limit_frames == 0) | |
342 | sr_dbg("Starting data capture for frameset %" PRIu64, | |
343 | devc->num_frames + 1); | |
344 | else | |
345 | sr_dbg("Starting data capture for frameset %" PRIu64 " of %" | |
346 | PRIu64, devc->num_frames + 1, devc->limit_frames); | |
347 | ||
348 | switch (devc->model->series->protocol) { | |
349 | case PROTOCOL_V1: | |
350 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
351 | break; | |
352 | case PROTOCOL_V2: | |
353 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
354 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE NORMAL") != SR_OK) | |
355 | return SR_ERR; | |
356 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
357 | } else { | |
358 | if (rigol_ds_config_set(sdi, ":STOP") != SR_OK) | |
359 | return SR_ERR; | |
360 | if (rigol_ds_config_set(sdi, ":WAV:POIN:MODE RAW") != SR_OK) | |
361 | return SR_ERR; | |
362 | if (sr_scpi_get_string(sdi->conn, ":TRIG:MODE?", &trig_mode) != SR_OK) | |
363 | return SR_ERR; | |
364 | if (rigol_ds_config_set(sdi, ":TRIG:%s:SWE SING", trig_mode) != SR_OK) | |
365 | return SR_ERR; | |
366 | if (rigol_ds_config_set(sdi, ":RUN") != SR_OK) | |
367 | return SR_ERR; | |
368 | rigol_ds_set_wait_event(devc, WAIT_STOP); | |
369 | } | |
370 | break; | |
371 | case PROTOCOL_V3: | |
372 | case PROTOCOL_V4: | |
373 | if (rigol_ds_config_set(sdi, ":WAV:FORM BYTE") != SR_OK) | |
374 | return SR_ERR; | |
375 | if (devc->data_source == DATA_SOURCE_LIVE) { | |
376 | if (rigol_ds_config_set(sdi, ":WAV:MODE NORM") != SR_OK) | |
377 | return SR_ERR; | |
378 | devc->analog_frame_size = devc->model->series->live_samples; | |
379 | devc->digital_frame_size = devc->model->series->live_samples; | |
380 | rigol_ds_set_wait_event(devc, WAIT_TRIGGER); | |
381 | } else { | |
382 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
383 | if (rigol_ds_config_set(sdi, ":WAV:MODE RAW") != SR_OK) | |
384 | return SR_ERR; | |
385 | } else if (devc->model->series->protocol == PROTOCOL_V4) { | |
386 | num_channels = 0; | |
387 | ||
388 | /* Channels 3 and 4 are multiplexed with D0-7 and D8-15 */ | |
389 | for (i = 0; i < devc->model->analog_channels; i++) { | |
390 | if (devc->analog_channels[i]) { | |
391 | num_channels++; | |
392 | } else if (i >= 2 && devc->model->has_digital) { | |
393 | for (j = 0; j < 8; j++) { | |
394 | if (devc->digital_channels[8 * (i - 2) + j]) { | |
395 | num_channels++; | |
396 | break; | |
397 | } | |
398 | } | |
399 | } | |
400 | } | |
401 | ||
402 | buffer_samples = devc->model->series->buffer_samples; | |
403 | if (buffer_samples == 0) | |
404 | { | |
405 | /* The DS4000 series does not have a fixed memory depth, it | |
406 | * can be chosen from the menu and also varies with number | |
407 | * of active channels. Retrieve the actual number with the | |
408 | * ACQ:MDEP command. */ | |
409 | sr_scpi_get_int(sdi->conn, "ACQ:MDEP?", &buffer_samples); | |
410 | devc->analog_frame_size = devc->digital_frame_size = | |
411 | buffer_samples; | |
412 | } | |
413 | else | |
414 | { | |
415 | /* The DS1000Z series has a fixed memory depth which we | |
416 | * need to divide correctly according to the number of | |
417 | * active channels. */ | |
418 | devc->analog_frame_size = devc->digital_frame_size = | |
419 | num_channels == 1 ? | |
420 | buffer_samples : | |
421 | num_channels == 2 ? | |
422 | buffer_samples / 2 : | |
423 | buffer_samples / 4; | |
424 | } | |
425 | } | |
426 | ||
427 | if (rigol_ds_config_set(sdi, ":SING") != SR_OK) | |
428 | return SR_ERR; | |
429 | rigol_ds_set_wait_event(devc, WAIT_STOP); | |
430 | } | |
431 | break; | |
432 | } | |
433 | ||
434 | return SR_OK; | |
435 | } | |
436 | ||
437 | /* Start reading data from the current channel */ | |
438 | SR_PRIV int rigol_ds_channel_start(const struct sr_dev_inst *sdi) | |
439 | { | |
440 | struct dev_context *devc; | |
441 | struct sr_channel *ch; | |
442 | ||
443 | if (!(devc = sdi->priv)) | |
444 | return SR_ERR; | |
445 | ||
446 | ch = devc->channel_entry->data; | |
447 | ||
448 | sr_dbg("Starting reading data from channel %d", ch->index + 1); | |
449 | ||
450 | switch (devc->model->series->protocol) { | |
451 | case PROTOCOL_V1: | |
452 | case PROTOCOL_V2: | |
453 | if (ch->type == SR_CHANNEL_LOGIC) { | |
454 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? DIG") != SR_OK) | |
455 | return SR_ERR; | |
456 | } else { | |
457 | if (sr_scpi_send(sdi->conn, ":WAV:DATA? CHAN%d", | |
458 | ch->index + 1) != SR_OK) | |
459 | return SR_ERR; | |
460 | } | |
461 | rigol_ds_set_wait_event(devc, WAIT_NONE); | |
462 | break; | |
463 | case PROTOCOL_V3: | |
464 | if (ch->type == SR_CHANNEL_LOGIC) { | |
465 | if (rigol_ds_config_set(sdi, ":WAV:SOUR LA") != SR_OK) | |
466 | return SR_ERR; | |
467 | } else { | |
468 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
469 | ch->index + 1) != SR_OK) | |
470 | return SR_ERR; | |
471 | } | |
472 | if (devc->data_source != DATA_SOURCE_LIVE) { | |
473 | if (rigol_ds_config_set(sdi, ":WAV:RES") != SR_OK) | |
474 | return SR_ERR; | |
475 | if (rigol_ds_config_set(sdi, ":WAV:BEG") != SR_OK) | |
476 | return SR_ERR; | |
477 | } | |
478 | break; | |
479 | case PROTOCOL_V4: | |
480 | if (ch->type == SR_CHANNEL_ANALOG) { | |
481 | if (rigol_ds_config_set(sdi, ":WAV:SOUR CHAN%d", | |
482 | ch->index + 1) != SR_OK) | |
483 | return SR_ERR; | |
484 | } else { | |
485 | if (rigol_ds_config_set(sdi, ":WAV:SOUR D%d", | |
486 | ch->index) != SR_OK) | |
487 | return SR_ERR; | |
488 | } | |
489 | ||
490 | if (rigol_ds_config_set(sdi, | |
491 | devc->data_source == DATA_SOURCE_LIVE ? | |
492 | ":WAV:MODE NORM" :":WAV:MODE RAW") != SR_OK) | |
493 | return SR_ERR; | |
494 | break; | |
495 | } | |
496 | ||
497 | if (devc->model->series->protocol >= PROTOCOL_V3 && | |
498 | ch->type == SR_CHANNEL_ANALOG) { | |
499 | /* Vertical increment. */ | |
500 | if (sr_scpi_get_float(sdi->conn, ":WAV:YINC?", | |
501 | &devc->vert_inc[ch->index]) != SR_OK) | |
502 | return SR_ERR; | |
503 | /* Vertical origin. */ | |
504 | if (sr_scpi_get_float(sdi->conn, ":WAV:YOR?", | |
505 | &devc->vert_origin[ch->index]) != SR_OK) | |
506 | return SR_ERR; | |
507 | /* Vertical reference. */ | |
508 | if (sr_scpi_get_int(sdi->conn, ":WAV:YREF?", | |
509 | &devc->vert_reference[ch->index]) != SR_OK) | |
510 | return SR_ERR; | |
511 | } else if (ch->type == SR_CHANNEL_ANALOG) { | |
512 | devc->vert_inc[ch->index] = devc->vdiv[ch->index] / 25.6; | |
513 | } | |
514 | ||
515 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); | |
516 | ||
517 | devc->num_channel_bytes = 0; | |
518 | devc->num_header_bytes = 0; | |
519 | devc->num_block_bytes = 0; | |
520 | ||
521 | return SR_OK; | |
522 | } | |
523 | ||
524 | /* Read the header of a data block */ | |
525 | static int rigol_ds_read_header(struct sr_dev_inst *sdi) | |
526 | { | |
527 | struct sr_scpi_dev_inst *scpi = sdi->conn; | |
528 | struct dev_context *devc = sdi->priv; | |
529 | char *buf = (char *) devc->buffer; | |
530 | size_t header_length; | |
531 | int ret; | |
532 | ||
533 | /* Try to read the hashsign and length digit. */ | |
534 | if (devc->num_header_bytes < 2) { | |
535 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
536 | 2 - devc->num_header_bytes); | |
537 | if (ret < 0) { | |
538 | sr_err("Read error while reading data header."); | |
539 | return SR_ERR; | |
540 | } | |
541 | devc->num_header_bytes += ret; | |
542 | } | |
543 | ||
544 | if (devc->num_header_bytes < 2) | |
545 | return 0; | |
546 | ||
547 | if (buf[0] != '#' || !isdigit(buf[1]) || buf[1] == '0') { | |
548 | sr_err("Received invalid data block header '%c%c'.", buf[0], buf[1]); | |
549 | return SR_ERR; | |
550 | } | |
551 | ||
552 | header_length = 2 + buf[1] - '0'; | |
553 | ||
554 | /* Try to read the length. */ | |
555 | if (devc->num_header_bytes < header_length) { | |
556 | ret = sr_scpi_read_data(scpi, buf + devc->num_header_bytes, | |
557 | header_length - devc->num_header_bytes); | |
558 | if (ret < 0) { | |
559 | sr_err("Read error while reading data header."); | |
560 | return SR_ERR; | |
561 | } | |
562 | devc->num_header_bytes += ret; | |
563 | } | |
564 | ||
565 | if (devc->num_header_bytes < header_length) | |
566 | return 0; | |
567 | ||
568 | /* Read the data length. */ | |
569 | buf[header_length] = '\0'; | |
570 | ||
571 | if (parse_int(buf + 2, &ret) != SR_OK) { | |
572 | sr_err("Received invalid data block length '%s'.", buf + 2); | |
573 | return -1; | |
574 | } | |
575 | ||
576 | sr_dbg("Received data block header: '%s' -> block length %d", buf, ret); | |
577 | ||
578 | return ret; | |
579 | } | |
580 | ||
581 | SR_PRIV int rigol_ds_receive(int fd, int revents, void *cb_data) | |
582 | { | |
583 | struct sr_dev_inst *sdi; | |
584 | struct sr_scpi_dev_inst *scpi; | |
585 | struct dev_context *devc; | |
586 | struct sr_datafeed_packet packet; | |
587 | struct sr_datafeed_analog analog; | |
588 | struct sr_analog_encoding encoding; | |
589 | struct sr_analog_meaning meaning; | |
590 | struct sr_analog_spec spec; | |
591 | struct sr_datafeed_logic logic; | |
592 | double vdiv, offset, origin; | |
593 | int len, i, vref; | |
594 | struct sr_channel *ch; | |
595 | gsize expected_data_bytes; | |
596 | ||
597 | (void)fd; | |
598 | ||
599 | if (!(sdi = cb_data)) | |
600 | return TRUE; | |
601 | ||
602 | if (!(devc = sdi->priv)) | |
603 | return TRUE; | |
604 | ||
605 | scpi = sdi->conn; | |
606 | ||
607 | if (!(revents == G_IO_IN || revents == 0)) | |
608 | return TRUE; | |
609 | ||
610 | switch (devc->wait_event) { | |
611 | case WAIT_NONE: | |
612 | break; | |
613 | case WAIT_TRIGGER: | |
614 | if (rigol_ds_trigger_wait(sdi) != SR_OK) | |
615 | return TRUE; | |
616 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
617 | return TRUE; | |
618 | return TRUE; | |
619 | case WAIT_BLOCK: | |
620 | if (rigol_ds_block_wait(sdi) != SR_OK) | |
621 | return TRUE; | |
622 | break; | |
623 | case WAIT_STOP: | |
624 | if (rigol_ds_stop_wait(sdi) != SR_OK) | |
625 | return TRUE; | |
626 | if (rigol_ds_check_stop(sdi) != SR_OK) | |
627 | return TRUE; | |
628 | if (rigol_ds_channel_start(sdi) != SR_OK) | |
629 | return TRUE; | |
630 | return TRUE; | |
631 | default: | |
632 | sr_err("BUG: Unknown event target encountered"); | |
633 | break; | |
634 | } | |
635 | ||
636 | ch = devc->channel_entry->data; | |
637 | ||
638 | expected_data_bytes = ch->type == SR_CHANNEL_ANALOG ? | |
639 | devc->analog_frame_size : devc->digital_frame_size; | |
640 | ||
641 | if (devc->num_block_bytes == 0) { | |
642 | if (devc->model->series->protocol >= PROTOCOL_V4) { | |
643 | if (rigol_ds_config_set(sdi, ":WAV:START %d", | |
644 | devc->num_channel_bytes + 1) != SR_OK) | |
645 | return TRUE; | |
646 | if (rigol_ds_config_set(sdi, ":WAV:STOP %d", | |
647 | MIN(devc->num_channel_bytes + ACQ_BLOCK_SIZE, | |
648 | devc->analog_frame_size)) != SR_OK) | |
649 | return TRUE; | |
650 | } | |
651 | ||
652 | if (devc->model->series->protocol >= PROTOCOL_V3) | |
653 | if (sr_scpi_send(sdi->conn, ":WAV:DATA?") != SR_OK) | |
654 | return TRUE; | |
655 | ||
656 | if (sr_scpi_read_begin(scpi) != SR_OK) | |
657 | return TRUE; | |
658 | ||
659 | if (devc->format == FORMAT_IEEE488_2) { | |
660 | sr_dbg("New block header expected"); | |
661 | len = rigol_ds_read_header(sdi); | |
662 | if (len == 0) | |
663 | /* Still reading the header. */ | |
664 | return TRUE; | |
665 | if (len == -1) { | |
666 | sr_err("Error while reading block header, aborting capture."); | |
667 | packet.type = SR_DF_FRAME_END; | |
668 | sr_session_send(sdi, &packet); | |
669 | sr_dev_acquisition_stop(sdi); | |
670 | return TRUE; | |
671 | } | |
672 | /* At slow timebases in live capture the DS2072 | |
673 | * sometimes returns "short" data blocks, with | |
674 | * apparently no way to get the rest of the data. | |
675 | * Discard these, the complete data block will | |
676 | * appear eventually. | |
677 | */ | |
678 | if (devc->data_source == DATA_SOURCE_LIVE | |
679 | && (unsigned)len < expected_data_bytes) { | |
680 | sr_dbg("Discarding short data block"); | |
681 | sr_scpi_read_data(scpi, (char *)devc->buffer, len + 1); | |
682 | return TRUE; | |
683 | } | |
684 | devc->num_block_bytes = len; | |
685 | } else { | |
686 | devc->num_block_bytes = expected_data_bytes; | |
687 | } | |
688 | devc->num_block_read = 0; | |
689 | } | |
690 | ||
691 | len = devc->num_block_bytes - devc->num_block_read; | |
692 | if (len > ACQ_BUFFER_SIZE) | |
693 | len = ACQ_BUFFER_SIZE; | |
694 | sr_dbg("Requesting read of %d bytes", len); | |
695 | ||
696 | len = sr_scpi_read_data(scpi, (char *)devc->buffer, len); | |
697 | ||
698 | if (len == -1) { | |
699 | sr_err("Error while reading block data, aborting capture."); | |
700 | packet.type = SR_DF_FRAME_END; | |
701 | sr_session_send(sdi, &packet); | |
702 | sr_dev_acquisition_stop(sdi); | |
703 | return TRUE; | |
704 | } | |
705 | ||
706 | sr_dbg("Received %d bytes.", len); | |
707 | ||
708 | devc->num_block_read += len; | |
709 | ||
710 | if (ch->type == SR_CHANNEL_ANALOG) { | |
711 | vref = devc->vert_reference[ch->index]; | |
712 | vdiv = devc->vert_inc[ch->index]; | |
713 | origin = devc->vert_origin[ch->index]; | |
714 | offset = devc->vert_offset[ch->index]; | |
715 | if (devc->model->series->protocol >= PROTOCOL_V3) | |
716 | for (i = 0; i < len; i++) | |
717 | devc->data[i] = ((int)devc->buffer[i] - vref - origin) * vdiv; | |
718 | else | |
719 | for (i = 0; i < len; i++) | |
720 | devc->data[i] = (128 - devc->buffer[i]) * vdiv - offset; | |
721 | float vdivlog = log10f(vdiv); | |
722 | int digits = -(int)vdivlog + (vdivlog < 0.0); | |
723 | sr_analog_init(&analog, &encoding, &meaning, &spec, digits); | |
724 | analog.meaning->channels = g_slist_append(NULL, ch); | |
725 | analog.num_samples = len; | |
726 | analog.data = devc->data; | |
727 | analog.meaning->mq = SR_MQ_VOLTAGE; | |
728 | analog.meaning->unit = SR_UNIT_VOLT; | |
729 | analog.meaning->mqflags = 0; | |
730 | packet.type = SR_DF_ANALOG; | |
731 | packet.payload = &analog; | |
732 | sr_session_send(sdi, &packet); | |
733 | g_slist_free(analog.meaning->channels); | |
734 | } else { | |
735 | logic.length = len; | |
736 | // TODO: For the MSO1000Z series, we need a way to express that | |
737 | // this data is in fact just for a single channel, with the valid | |
738 | // data for that channel in the LSB of each byte. | |
739 | logic.unitsize = devc->model->series->protocol == PROTOCOL_V4 ? 1 : 2; | |
740 | logic.data = devc->buffer; | |
741 | packet.type = SR_DF_LOGIC; | |
742 | packet.payload = &logic; | |
743 | sr_session_send(sdi, &packet); | |
744 | } | |
745 | ||
746 | if (devc->num_block_read == devc->num_block_bytes) { | |
747 | sr_dbg("Block has been completed"); | |
748 | if (devc->model->series->protocol >= PROTOCOL_V3) { | |
749 | /* Discard the terminating linefeed */ | |
750 | sr_scpi_read_data(scpi, (char *)devc->buffer, 1); | |
751 | } | |
752 | if (devc->format == FORMAT_IEEE488_2) { | |
753 | /* Prepare for possible next block */ | |
754 | devc->num_header_bytes = 0; | |
755 | devc->num_block_bytes = 0; | |
756 | if (devc->data_source != DATA_SOURCE_LIVE) | |
757 | rigol_ds_set_wait_event(devc, WAIT_BLOCK); | |
758 | } | |
759 | /* End acquisition when data for all channels is acquired. */ | |
760 | if (!sr_scpi_read_complete(scpi) && !devc->channel_entry->next) { | |
761 | sr_err("Read should have been completed"); | |
762 | packet.type = SR_DF_FRAME_END; | |
763 | sr_session_send(sdi, &packet); | |
764 | sr_dev_acquisition_stop(sdi); | |
765 | return TRUE; | |
766 | } | |
767 | devc->num_block_read = 0; | |
768 | } else { | |
769 | sr_dbg("%" PRIu64 " of %" PRIu64 " block bytes read", | |
770 | devc->num_block_read, devc->num_block_bytes); | |
771 | } | |
772 | ||
773 | devc->num_channel_bytes += len; | |
774 | ||
775 | if (devc->num_channel_bytes < expected_data_bytes) | |
776 | /* Don't have the full data for this channel yet, re-run. */ | |
777 | return TRUE; | |
778 | ||
779 | /* End of data for this channel. */ | |
780 | if (devc->model->series->protocol == PROTOCOL_V3) { | |
781 | /* Signal end of data download to scope */ | |
782 | if (devc->data_source != DATA_SOURCE_LIVE) | |
783 | /* | |
784 | * This causes a query error, without it switching | |
785 | * to the next channel causes an error. Fun with | |
786 | * firmware... | |
787 | */ | |
788 | rigol_ds_config_set(sdi, ":WAV:END"); | |
789 | } | |
790 | ||
791 | if (devc->channel_entry->next) { | |
792 | /* We got the frame for this channel, now get the next channel. */ | |
793 | devc->channel_entry = devc->channel_entry->next; | |
794 | rigol_ds_channel_start(sdi); | |
795 | } else { | |
796 | /* Done with this frame. */ | |
797 | packet.type = SR_DF_FRAME_END; | |
798 | sr_session_send(sdi, &packet); | |
799 | ||
800 | if (++devc->num_frames == devc->limit_frames) { | |
801 | /* Last frame, stop capture. */ | |
802 | sr_dev_acquisition_stop(sdi); | |
803 | } else { | |
804 | /* Get the next frame, starting with the first channel. */ | |
805 | devc->channel_entry = devc->enabled_channels; | |
806 | ||
807 | rigol_ds_capture_start(sdi); | |
808 | ||
809 | /* Start of next frame. */ | |
810 | packet.type = SR_DF_FRAME_BEGIN; | |
811 | sr_session_send(sdi, &packet); | |
812 | } | |
813 | } | |
814 | ||
815 | return TRUE; | |
816 | } | |
817 | ||
818 | SR_PRIV int rigol_ds_get_dev_cfg(const struct sr_dev_inst *sdi) | |
819 | { | |
820 | struct dev_context *devc; | |
821 | struct sr_channel *ch; | |
822 | char *cmd; | |
823 | unsigned int i; | |
824 | int res; | |
825 | ||
826 | devc = sdi->priv; | |
827 | ||
828 | /* Analog channel state. */ | |
829 | for (i = 0; i < devc->model->analog_channels; i++) { | |
830 | cmd = g_strdup_printf(":CHAN%d:DISP?", i + 1); | |
831 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->analog_channels[i]); | |
832 | g_free(cmd); | |
833 | if (res != SR_OK) | |
834 | return SR_ERR; | |
835 | ch = g_slist_nth_data(sdi->channels, i); | |
836 | ch->enabled = devc->analog_channels[i]; | |
837 | } | |
838 | sr_dbg("Current analog channel state:"); | |
839 | for (i = 0; i < devc->model->analog_channels; i++) | |
840 | sr_dbg("CH%d %s", i + 1, devc->analog_channels[i] ? "on" : "off"); | |
841 | ||
842 | /* Digital channel state. */ | |
843 | if (devc->model->has_digital) { | |
844 | if (sr_scpi_get_bool(sdi->conn, | |
845 | devc->model->series->protocol >= PROTOCOL_V3 ? | |
846 | ":LA:STAT?" : ":LA:DISP?", | |
847 | &devc->la_enabled) != SR_OK) | |
848 | return SR_ERR; | |
849 | sr_dbg("Logic analyzer %s, current digital channel state:", | |
850 | devc->la_enabled ? "enabled" : "disabled"); | |
851 | for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) { | |
852 | cmd = g_strdup_printf( | |
853 | devc->model->series->protocol >= PROTOCOL_V3 ? | |
854 | ":LA:DIG%d:DISP?" : ":DIG%d:TURN?", i); | |
855 | res = sr_scpi_get_bool(sdi->conn, cmd, &devc->digital_channels[i]); | |
856 | g_free(cmd); | |
857 | if (res != SR_OK) | |
858 | return SR_ERR; | |
859 | ch = g_slist_nth_data(sdi->channels, i + devc->model->analog_channels); | |
860 | ch->enabled = devc->digital_channels[i]; | |
861 | sr_dbg("D%d: %s", i, devc->digital_channels[i] ? "on" : "off"); | |
862 | } | |
863 | } | |
864 | ||
865 | /* Timebase. */ | |
866 | if (sr_scpi_get_float(sdi->conn, ":TIM:SCAL?", &devc->timebase) != SR_OK) | |
867 | return SR_ERR; | |
868 | sr_dbg("Current timebase %g", devc->timebase); | |
869 | ||
870 | /* Probe attenuation. */ | |
871 | for (i = 0; i < devc->model->analog_channels; i++) { | |
872 | cmd = g_strdup_printf(":CHAN%d:PROB?", i + 1); | |
873 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->attenuation[i]); | |
874 | g_free(cmd); | |
875 | if (res != SR_OK) | |
876 | return SR_ERR; | |
877 | } | |
878 | sr_dbg("Current probe attenuation:"); | |
879 | for (i = 0; i < devc->model->analog_channels; i++) | |
880 | sr_dbg("CH%d %g", i + 1, devc->attenuation[i]); | |
881 | ||
882 | /* Vertical gain and offset. */ | |
883 | if (rigol_ds_get_dev_cfg_vertical(sdi) != SR_OK) | |
884 | return SR_ERR; | |
885 | ||
886 | /* Coupling. */ | |
887 | for (i = 0; i < devc->model->analog_channels; i++) { | |
888 | cmd = g_strdup_printf(":CHAN%d:COUP?", i + 1); | |
889 | res = sr_scpi_get_string(sdi->conn, cmd, &devc->coupling[i]); | |
890 | g_free(cmd); | |
891 | if (res != SR_OK) | |
892 | return SR_ERR; | |
893 | } | |
894 | sr_dbg("Current coupling:"); | |
895 | for (i = 0; i < devc->model->analog_channels; i++) | |
896 | sr_dbg("CH%d %s", i + 1, devc->coupling[i]); | |
897 | ||
898 | /* Trigger source. */ | |
899 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SOUR?", &devc->trigger_source) != SR_OK) | |
900 | return SR_ERR; | |
901 | sr_dbg("Current trigger source %s", devc->trigger_source); | |
902 | ||
903 | /* Horizontal trigger position. */ | |
904 | if (sr_scpi_get_float(sdi->conn, devc->model->cmds[CMD_GET_HORIZ_TRIGGERPOS].str, | |
905 | &devc->horiz_triggerpos) != SR_OK) | |
906 | return SR_ERR; | |
907 | sr_dbg("Current horizontal trigger position %g", devc->horiz_triggerpos); | |
908 | ||
909 | /* Trigger slope. */ | |
910 | if (sr_scpi_get_string(sdi->conn, ":TRIG:EDGE:SLOP?", &devc->trigger_slope) != SR_OK) | |
911 | return SR_ERR; | |
912 | sr_dbg("Current trigger slope %s", devc->trigger_slope); | |
913 | ||
914 | /* Trigger level. */ | |
915 | if (sr_scpi_get_float(sdi->conn, ":TRIG:EDGE:LEV?", &devc->trigger_level) != SR_OK) | |
916 | return SR_ERR; | |
917 | sr_dbg("Current trigger level %g", devc->trigger_level); | |
918 | ||
919 | return SR_OK; | |
920 | } | |
921 | ||
922 | SR_PRIV int rigol_ds_get_dev_cfg_vertical(const struct sr_dev_inst *sdi) | |
923 | { | |
924 | struct dev_context *devc; | |
925 | char *cmd; | |
926 | unsigned int i; | |
927 | int res; | |
928 | ||
929 | devc = sdi->priv; | |
930 | ||
931 | /* Vertical gain. */ | |
932 | for (i = 0; i < devc->model->analog_channels; i++) { | |
933 | cmd = g_strdup_printf(":CHAN%d:SCAL?", i + 1); | |
934 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vdiv[i]); | |
935 | g_free(cmd); | |
936 | if (res != SR_OK) | |
937 | return SR_ERR; | |
938 | } | |
939 | sr_dbg("Current vertical gain:"); | |
940 | for (i = 0; i < devc->model->analog_channels; i++) | |
941 | sr_dbg("CH%d %g", i + 1, devc->vdiv[i]); | |
942 | ||
943 | /* Vertical offset. */ | |
944 | for (i = 0; i < devc->model->analog_channels; i++) { | |
945 | cmd = g_strdup_printf(":CHAN%d:OFFS?", i + 1); | |
946 | res = sr_scpi_get_float(sdi->conn, cmd, &devc->vert_offset[i]); | |
947 | g_free(cmd); | |
948 | if (res != SR_OK) | |
949 | return SR_ERR; | |
950 | } | |
951 | sr_dbg("Current vertical offset:"); | |
952 | for (i = 0; i < devc->model->analog_channels; i++) | |
953 | sr_dbg("CH%d %g", i + 1, devc->vert_offset[i]); | |
954 | ||
955 | return SR_OK; | |
956 | } |