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[libsigrok.git] / src / hardware / rigol-ds / api.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include <config.h>
23#include <fcntl.h>
24#include <unistd.h>
25#include <stdlib.h>
26#include <string.h>
27#include <strings.h>
28#include <math.h>
29#include <glib.h>
30#include <libsigrok/libsigrok.h>
31#include "libsigrok-internal.h"
32#include "scpi.h"
33#include "protocol.h"
34
35static const uint32_t scanopts[] = {
36 SR_CONF_CONN,
37 SR_CONF_SERIALCOMM,
38};
39
40static const uint32_t drvopts[] = {
41 SR_CONF_OSCILLOSCOPE,
42};
43
44static const uint32_t devopts[] = {
45 SR_CONF_LIMIT_FRAMES | SR_CONF_GET | SR_CONF_SET,
46 SR_CONF_SAMPLERATE | SR_CONF_GET,
47 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
48 SR_CONF_NUM_HDIV | SR_CONF_GET,
49 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
50 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
51 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
52 SR_CONF_TRIGGER_LEVEL | SR_CONF_GET | SR_CONF_SET,
53 SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
54};
55
56static const uint32_t devopts_cg_analog[] = {
57 SR_CONF_NUM_VDIV | SR_CONF_GET,
58 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
59 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
60 SR_CONF_PROBE_FACTOR | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
61};
62
63static const uint64_t timebases[][2] = {
64 /* nanoseconds */
65 { 1, 1000000000 },
66 { 2, 1000000000 },
67 { 5, 1000000000 },
68 { 10, 1000000000 },
69 { 20, 1000000000 },
70 { 50, 1000000000 },
71 { 100, 1000000000 },
72 { 500, 1000000000 },
73 /* microseconds */
74 { 1, 1000000 },
75 { 2, 1000000 },
76 { 5, 1000000 },
77 { 10, 1000000 },
78 { 20, 1000000 },
79 { 50, 1000000 },
80 { 100, 1000000 },
81 { 200, 1000000 },
82 { 500, 1000000 },
83 /* milliseconds */
84 { 1, 1000 },
85 { 2, 1000 },
86 { 5, 1000 },
87 { 10, 1000 },
88 { 20, 1000 },
89 { 50, 1000 },
90 { 100, 1000 },
91 { 200, 1000 },
92 { 500, 1000 },
93 /* seconds */
94 { 1, 1 },
95 { 2, 1 },
96 { 5, 1 },
97 { 10, 1 },
98 { 20, 1 },
99 { 50, 1 },
100 { 100, 1 },
101 { 200, 1 },
102 { 500, 1 },
103 { 1000, 1 },
104};
105
106static const uint64_t vdivs[][2] = {
107 /* microvolts */
108 { 500, 1000000 },
109 /* millivolts */
110 { 1, 1000 },
111 { 2, 1000 },
112 { 5, 1000 },
113 { 10, 1000 },
114 { 20, 1000 },
115 { 50, 1000 },
116 { 100, 1000 },
117 { 200, 1000 },
118 { 500, 1000 },
119 /* volts */
120 { 1, 1 },
121 { 2, 1 },
122 { 5, 1 },
123 { 10, 1 },
124 { 20, 1 },
125 { 50, 1 },
126 { 100, 1 },
127};
128
129static const char *trigger_sources_2_chans[] = {
130 "CH1", "CH2",
131 "EXT", "AC Line",
132 "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7",
133 "D8", "D9", "D10", "D11", "D12", "D13", "D14", "D15",
134};
135
136static const char *trigger_sources_4_chans[] = {
137 "CH1", "CH2", "CH3", "CH4",
138 "EXT", "AC Line",
139 "D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7",
140 "D8", "D9", "D10", "D11", "D12", "D13", "D14", "D15",
141};
142
143static const char *trigger_slopes[] = {
144 "r", "f",
145};
146
147static const char *coupling[] = {
148 "AC", "DC", "GND",
149};
150
151static const uint64_t probe_factor[] = {
152 1, 2, 5, 10, 20, 50, 100, 200, 500, 1000,
153};
154
155/* Do not change the order of entries */
156static const char *data_sources[] = {
157 "Live",
158 "Memory",
159 "Segmented",
160};
161
162static const struct rigol_ds_command std_cmd[] = {
163 { CMD_GET_HORIZ_TRIGGERPOS, ":TIM:OFFS?" },
164 { CMD_SET_HORIZ_TRIGGERPOS, ":TIM:OFFS %s" },
165};
166
167static const struct rigol_ds_command mso7000a_cmd[] = {
168 { CMD_GET_HORIZ_TRIGGERPOS, ":TIM:POS?" },
169 { CMD_SET_HORIZ_TRIGGERPOS, ":TIM:POS %s" },
170};
171
172enum vendor {
173 RIGOL,
174 AGILENT,
175};
176
177enum series {
178 VS5000,
179 DS1000,
180 DS2000,
181 DS2000A,
182 DSO1000,
183 DSO1000B,
184 DS1000Z,
185 DS4000,
186 MSO5000,
187 MSO7000A,
188};
189
190/* short name, full name */
191static const struct rigol_ds_vendor supported_vendors[] = {
192 [RIGOL] = {"Rigol", "Rigol Technologies"},
193 [AGILENT] = {"Agilent", "Agilent Technologies"},
194};
195
196#define VENDOR(x) &supported_vendors[x]
197/* vendor, series/name, protocol, data format, max timebase, min vdiv,
198 * number of horizontal divs, live waveform samples, memory buffer samples */
199static const struct rigol_ds_series supported_series[] = {
200 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
201 {50, 1}, {2, 1000}, 14, 2048, 0},
202 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
203 {50, 1}, {2, 1000}, 12, 600, 1048576},
204 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
205 {500, 1}, {500, 1000000}, 14, 1400, 14000},
206 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
207 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
208 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
209 {50, 1}, {2, 1000}, 12, 600, 20480},
210 [DSO1000B] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
211 {50, 1}, {2, 1000}, 12, 600, 20480},
212 [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
213 {50, 1}, {1, 1000}, 12, 1200, 12000000},
214 [DS4000] = {VENDOR(RIGOL), "DS4000", PROTOCOL_V4, FORMAT_IEEE488_2,
215 {1000, 1}, {1, 1000}, 14, 1400, 0},
216 [MSO5000] = {VENDOR(RIGOL), "MSO5000", PROTOCOL_V5, FORMAT_IEEE488_2,
217 {1000, 1}, {500, 1000000}, 10, 1000, 0},
218 [MSO7000A] = {VENDOR(AGILENT), "MSO7000A", PROTOCOL_V4, FORMAT_IEEE488_2,
219 {50, 1}, {2, 1000}, 10, 1000, 8000000},
220};
221
222#define SERIES(x) &supported_series[x]
223/*
224 * Use a macro to select the correct list of trigger sources and its length
225 * based on the number of analog channels and presence of digital channels.
226 */
227#define CH_INFO(num, digital) \
228 num, digital, trigger_sources_##num##_chans, \
229 digital ? ARRAY_SIZE(trigger_sources_##num##_chans) : (num + 2)
230/* series, model, min timebase, analog channels, digital */
231static const struct rigol_ds_model supported_models[] = {
232 {SERIES(VS5000), "VS5022", {20, 1000000000}, CH_INFO(2, false), std_cmd},
233 {SERIES(VS5000), "VS5042", {10, 1000000000}, CH_INFO(2, false), std_cmd},
234 {SERIES(VS5000), "VS5062", {5, 1000000000}, CH_INFO(2, false), std_cmd},
235 {SERIES(VS5000), "VS5102", {2, 1000000000}, CH_INFO(2, false), std_cmd},
236 {SERIES(VS5000), "VS5202", {2, 1000000000}, CH_INFO(2, false), std_cmd},
237 {SERIES(VS5000), "VS5022D", {20, 1000000000}, CH_INFO(2, true), std_cmd},
238 {SERIES(VS5000), "VS5042D", {10, 1000000000}, CH_INFO(2, true), std_cmd},
239 {SERIES(VS5000), "VS5062D", {5, 1000000000}, CH_INFO(2, true), std_cmd},
240 {SERIES(VS5000), "VS5102D", {2, 1000000000}, CH_INFO(2, true), std_cmd},
241 {SERIES(VS5000), "VS5202D", {2, 1000000000}, CH_INFO(2, true), std_cmd},
242 {SERIES(DS1000), "DS1052E", {5, 1000000000}, CH_INFO(2, false), std_cmd},
243 {SERIES(DS1000), "DS1102E", {2, 1000000000}, CH_INFO(2, false), std_cmd},
244 {SERIES(DS1000), "DS1152E", {2, 1000000000}, CH_INFO(2, false), std_cmd},
245 {SERIES(DS1000), "DS1152E-EDU", {2, 1000000000}, CH_INFO(2, false), std_cmd},
246 {SERIES(DS1000), "DS1052D", {5, 1000000000}, CH_INFO(2, true), std_cmd},
247 {SERIES(DS1000), "DS1102D", {2, 1000000000}, CH_INFO(2, true), std_cmd},
248 {SERIES(DS1000), "DS1152D", {2, 1000000000}, CH_INFO(2, true), std_cmd},
249 {SERIES(DS2000), "DS2072", {5, 1000000000}, CH_INFO(2, false), std_cmd},
250 {SERIES(DS2000), "DS2102", {5, 1000000000}, CH_INFO(2, false), std_cmd},
251 {SERIES(DS2000), "DS2202", {2, 1000000000}, CH_INFO(2, false), std_cmd},
252 {SERIES(DS2000), "DS2302", {1, 1000000000}, CH_INFO(2, false), std_cmd},
253 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, CH_INFO(2, false), std_cmd},
254 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, CH_INFO(2, false), std_cmd},
255 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, CH_INFO(2, false), std_cmd},
256 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, CH_INFO(2, false), std_cmd},
257 {SERIES(DS2000A), "MSO2072A", {5, 1000000000}, CH_INFO(2, true), std_cmd},
258 {SERIES(DS2000A), "MSO2102A", {5, 1000000000}, CH_INFO(2, true), std_cmd},
259 {SERIES(DS2000A), "MSO2202A", {2, 1000000000}, CH_INFO(2, true), std_cmd},
260 {SERIES(DS2000A), "MSO2302A", {1, 1000000000}, CH_INFO(2, true), std_cmd},
261 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, CH_INFO(2, false), std_cmd},
262 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, CH_INFO(4, false), std_cmd},
263 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, CH_INFO(2, false), std_cmd},
264 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, CH_INFO(4, false), std_cmd},
265 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, CH_INFO(2, false), std_cmd},
266 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, CH_INFO(4, false), std_cmd},
267 {SERIES(DSO1000B), "DSO1052B", {2, 1000000000}, CH_INFO(2, false), std_cmd},
268 {SERIES(DSO1000B), "DSO1072B", {2, 1000000000}, CH_INFO(2, false), std_cmd},
269 {SERIES(DSO1000B), "DSO1102B", {2, 1000000000}, CH_INFO(2, false), std_cmd},
270 {SERIES(DSO1000B), "DSO1152B", {2, 1000000000}, CH_INFO(2, false), std_cmd},
271 {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, CH_INFO(4, false), std_cmd},
272 {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, CH_INFO(4, false), std_cmd},
273 {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, CH_INFO(4, false), std_cmd},
274 {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, CH_INFO(4, false), std_cmd},
275 {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, CH_INFO(4, false), std_cmd},
276 {SERIES(DS1000Z), "DS1074Z Plus", {5, 1000000000}, CH_INFO(4, false), std_cmd},
277 {SERIES(DS1000Z), "DS1104Z Plus", {5, 1000000000}, CH_INFO(4, false), std_cmd},
278 {SERIES(DS1000Z), "DS1102Z-E", {2, 1000000000}, CH_INFO(2, false), std_cmd},
279 {SERIES(DS1000Z), "DS1202Z-E", {2, 1000000000}, CH_INFO(2, false), std_cmd},
280 {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, CH_INFO(4, true), std_cmd},
281 {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, CH_INFO(4, true), std_cmd},
282 {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, CH_INFO(4, true), std_cmd},
283 {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, CH_INFO(4, true), std_cmd},
284 {SERIES(DS4000), "DS4024", {1, 1000000000}, CH_INFO(4, false), std_cmd},
285 {SERIES(MSO5000), "MSO5072", {1, 1000000000}, CH_INFO(2, true), std_cmd},
286 {SERIES(MSO5000), "MSO5074", {1, 1000000000}, CH_INFO(4, true), std_cmd},
287 {SERIES(MSO5000), "MSO5102", {1, 1000000000}, CH_INFO(2, true), std_cmd},
288 {SERIES(MSO5000), "MSO5104", {1, 1000000000}, CH_INFO(4, true), std_cmd},
289 {SERIES(MSO5000), "MSO5204", {1, 1000000000}, CH_INFO(4, true), std_cmd},
290 {SERIES(MSO5000), "MSO5354", {1, 1000000000}, CH_INFO(4, true), std_cmd},
291 /* TODO: Digital channels are not yet supported on MSO7000A. */
292 {SERIES(MSO7000A), "MSO7034A", {2, 1000000000}, CH_INFO(4, false), mso7000a_cmd},
293};
294
295static struct sr_dev_driver rigol_ds_driver_info;
296
297static int analog_frame_size(const struct sr_dev_inst *);
298
299static void clear_helper(struct dev_context *devc)
300{
301 unsigned int i;
302
303 g_free(devc->data);
304 g_free(devc->buffer);
305 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
306 g_free(devc->coupling[i]);
307 g_free(devc->trigger_source);
308 g_free(devc->trigger_slope);
309 g_free(devc->analog_groups);
310}
311
312static int dev_clear(const struct sr_dev_driver *di)
313{
314 return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper);
315}
316
317static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
318{
319 struct dev_context *devc;
320 struct sr_dev_inst *sdi;
321 struct sr_scpi_hw_info *hw_info;
322 struct sr_channel *ch;
323 long n[3];
324 unsigned int i;
325 const struct rigol_ds_model *model = NULL;
326 gchar *channel_name, **version;
327
328 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
329 sr_info("Couldn't get IDN response, retrying.");
330 sr_scpi_close(scpi);
331 sr_scpi_open(scpi);
332 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
333 sr_info("Couldn't get IDN response.");
334 return NULL;
335 }
336 }
337
338 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
339 if (!g_ascii_strcasecmp(hw_info->manufacturer,
340 supported_models[i].series->vendor->full_name) &&
341 !strcmp(hw_info->model, supported_models[i].name)) {
342 model = &supported_models[i];
343 break;
344 }
345 }
346
347 if (!model) {
348 sr_scpi_hw_info_free(hw_info);
349 return NULL;
350 }
351
352 sdi = g_malloc0(sizeof(struct sr_dev_inst));
353 sdi->vendor = g_strdup(model->series->vendor->name);
354 sdi->model = g_strdup(model->name);
355 sdi->version = g_strdup(hw_info->firmware_version);
356 sdi->conn = scpi;
357 sdi->driver = &rigol_ds_driver_info;
358 sdi->inst_type = SR_INST_SCPI;
359 sdi->serial_num = g_strdup(hw_info->serial_number);
360 devc = g_malloc0(sizeof(struct dev_context));
361 devc->limit_frames = 0;
362 devc->model = model;
363 devc->format = model->series->format;
364
365 /* DS1000 models with firmware before 0.2.4 used the old data format. */
366 if (model->series == SERIES(DS1000)) {
367 version = g_strsplit(hw_info->firmware_version, ".", 0);
368 do {
369 if (!version[0] || !version[1] || !version[2])
370 break;
371 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
372 break;
373 for (i = 0; i < 3; i++) {
374 if (sr_atol(version[i], &n[i]) != SR_OK)
375 break;
376 }
377 if (i != 3)
378 break;
379 scpi->firmware_version = n[0] * 100 + n[1] * 10 + n[2];
380 if (scpi->firmware_version < 24) {
381 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
382 devc->format = FORMAT_RAW;
383 }
384 break;
385 } while (0);
386 g_strfreev(version);
387 }
388
389 sr_scpi_hw_info_free(hw_info);
390
391 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
392 model->analog_channels);
393
394 for (i = 0; i < model->analog_channels; i++) {
395 channel_name = g_strdup_printf("CH%d", i + 1);
396 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
397
398 devc->analog_groups[i] = sr_channel_group_new(sdi,
399 channel_name, NULL);
400 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
401 }
402
403 if (devc->model->has_digital) {
404 devc->digital_group = sr_channel_group_new(sdi, "LA", NULL);
405 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
406 channel_name = g_strdup_printf("D%d", i);
407 ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
408 g_free(channel_name);
409 devc->digital_group->channels = g_slist_append(
410 devc->digital_group->channels, ch);
411 }
412 }
413
414 for (i = 0; i < ARRAY_SIZE(timebases); i++) {
415 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
416 devc->timebases = &timebases[i];
417 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
418 devc->num_timebases = &timebases[i] - devc->timebases + 1;
419 }
420
421 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
422 if (!memcmp(&devc->model->series->min_vdiv,
423 &vdivs[i], sizeof(uint64_t[2]))) {
424 devc->vdivs = &vdivs[i];
425 devc->num_vdivs = ARRAY_SIZE(vdivs) - i;
426 }
427 }
428
429 devc->buffer = g_malloc(ACQ_BUFFER_SIZE);
430 devc->data = g_malloc(ACQ_BUFFER_SIZE * sizeof(float));
431
432 devc->data_source = DATA_SOURCE_LIVE;
433
434 sdi->priv = devc;
435
436 return sdi;
437}
438
439static GSList *scan(struct sr_dev_driver *di, GSList *options)
440{
441 return sr_scpi_scan(di->context, options, probe_device);
442}
443
444static int dev_open(struct sr_dev_inst *sdi)
445{
446 int ret;
447 struct sr_scpi_dev_inst *scpi = sdi->conn;
448
449 if ((ret = sr_scpi_open(scpi)) < 0) {
450 sr_err("Failed to open SCPI device: %s.", sr_strerror(ret));
451 return SR_ERR;
452 }
453
454 if ((ret = rigol_ds_get_dev_cfg(sdi)) < 0) {
455 sr_err("Failed to get device config: %s.", sr_strerror(ret));
456 return SR_ERR;
457 }
458
459 return SR_OK;
460}
461
462static int dev_close(struct sr_dev_inst *sdi)
463{
464 struct sr_scpi_dev_inst *scpi;
465 struct dev_context *devc;
466
467 scpi = sdi->conn;
468 devc = sdi->priv;
469
470 if (!scpi)
471 return SR_ERR_BUG;
472
473 if (devc->model->series->protocol == PROTOCOL_V2)
474 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
475
476 return sr_scpi_close(scpi);
477}
478
479static int analog_frame_size(const struct sr_dev_inst *sdi)
480{
481 struct dev_context *devc = sdi->priv;
482 struct sr_channel *ch;
483 int analog_channels = 0;
484 GSList *l;
485
486 for (l = sdi->channels; l; l = l->next) {
487 ch = l->data;
488 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
489 analog_channels++;
490 }
491
492 if (analog_channels == 0)
493 return 0;
494
495 switch (devc->data_source) {
496 case DATA_SOURCE_LIVE:
497 return devc->model->series->live_samples;
498 case DATA_SOURCE_MEMORY:
499 case DATA_SOURCE_SEGMENTED:
500 return devc->model->series->buffer_samples / analog_channels;
501 default:
502 return 0;
503 }
504}
505
506static int digital_frame_size(const struct sr_dev_inst *sdi)
507{
508 struct dev_context *devc = sdi->priv;
509
510 switch (devc->data_source) {
511 case DATA_SOURCE_LIVE:
512 return devc->model->series->live_samples * 2;
513 case DATA_SOURCE_MEMORY:
514 case DATA_SOURCE_SEGMENTED:
515 return devc->model->series->buffer_samples * 2;
516 default:
517 return 0;
518 }
519}
520
521static int config_get(uint32_t key, GVariant **data,
522 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
523{
524 struct dev_context *devc;
525 struct sr_channel *ch;
526 const char *tmp_str;
527 int analog_channel = -1;
528 float smallest_diff = INFINITY;
529 int idx = -1;
530 unsigned i;
531
532 if (!sdi)
533 return SR_ERR_ARG;
534
535 devc = sdi->priv;
536
537 /* If a channel group is specified, it must be a valid one. */
538 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
539 sr_err("Invalid channel group specified.");
540 return SR_ERR;
541 }
542
543 if (cg) {
544 ch = g_slist_nth_data(cg->channels, 0);
545 if (!ch)
546 return SR_ERR;
547 if (ch->type == SR_CHANNEL_ANALOG) {
548 if (ch->name[2] < '1' || ch->name[2] > '4')
549 return SR_ERR;
550 analog_channel = ch->name[2] - '1';
551 }
552 }
553
554 switch (key) {
555 case SR_CONF_NUM_HDIV:
556 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
557 break;
558 case SR_CONF_NUM_VDIV:
559 *data = g_variant_new_int32(devc->num_vdivs);
560 break;
561 case SR_CONF_DATA_SOURCE:
562 if (devc->data_source == DATA_SOURCE_LIVE)
563 *data = g_variant_new_string("Live");
564 else if (devc->data_source == DATA_SOURCE_MEMORY)
565 *data = g_variant_new_string("Memory");
566 else
567 *data = g_variant_new_string("Segmented");
568 break;
569 case SR_CONF_LIMIT_FRAMES:
570 *data = g_variant_new_uint64(devc->limit_frames);
571 break;
572 case SR_CONF_SAMPLERATE:
573 *data = g_variant_new_uint64(devc->sample_rate);
574 break;
575 case SR_CONF_TRIGGER_SOURCE:
576 if (!strcmp(devc->trigger_source, "ACL"))
577 tmp_str = "AC Line";
578 else if (!strcmp(devc->trigger_source, "CHAN1"))
579 tmp_str = "CH1";
580 else if (!strcmp(devc->trigger_source, "CHAN2"))
581 tmp_str = "CH2";
582 else if (!strcmp(devc->trigger_source, "CHAN3"))
583 tmp_str = "CH3";
584 else if (!strcmp(devc->trigger_source, "CHAN4"))
585 tmp_str = "CH4";
586 else
587 tmp_str = devc->trigger_source;
588 *data = g_variant_new_string(tmp_str);
589 break;
590 case SR_CONF_TRIGGER_SLOPE:
591 if (!strncmp(devc->trigger_slope, "POS", 3)) {
592 tmp_str = "r";
593 } else if (!strncmp(devc->trigger_slope, "NEG", 3)) {
594 tmp_str = "f";
595 } else {
596 sr_dbg("Unknown trigger slope: '%s'.", devc->trigger_slope);
597 return SR_ERR_NA;
598 }
599 *data = g_variant_new_string(tmp_str);
600 break;
601 case SR_CONF_TRIGGER_LEVEL:
602 *data = g_variant_new_double(devc->trigger_level);
603 break;
604 case SR_CONF_TIMEBASE:
605 for (i = 0; i < devc->num_timebases; i++) {
606 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
607 float diff = fabs(devc->timebase - tb);
608 if (diff < smallest_diff) {
609 smallest_diff = diff;
610 idx = i;
611 }
612 }
613 if (idx < 0) {
614 sr_dbg("Negative timebase index: %d.", idx);
615 return SR_ERR_NA;
616 }
617 *data = g_variant_new("(tt)", devc->timebases[idx][0],
618 devc->timebases[idx][1]);
619 break;
620 case SR_CONF_VDIV:
621 if (analog_channel < 0) {
622 sr_dbg("Negative analog channel: %d.", analog_channel);
623 return SR_ERR_NA;
624 }
625 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
626 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
627 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
628 if (diff < smallest_diff) {
629 smallest_diff = diff;
630 idx = i;
631 }
632 }
633 if (idx < 0) {
634 sr_dbg("Negative vdiv index: %d.", idx);
635 return SR_ERR_NA;
636 }
637 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
638 break;
639 case SR_CONF_COUPLING:
640 if (analog_channel < 0) {
641 sr_dbg("Negative analog channel: %d.", analog_channel);
642 return SR_ERR_NA;
643 }
644 *data = g_variant_new_string(devc->coupling[analog_channel]);
645 break;
646 case SR_CONF_PROBE_FACTOR:
647 if (analog_channel < 0) {
648 sr_dbg("Negative analog channel: %d.", analog_channel);
649 return SR_ERR_NA;
650 }
651 *data = g_variant_new_uint64(devc->attenuation[analog_channel]);
652 break;
653 default:
654 return SR_ERR_NA;
655 }
656
657 return SR_OK;
658}
659
660static int config_set(uint32_t key, GVariant *data,
661 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
662{
663 struct dev_context *devc;
664 uint64_t p;
665 double t_dbl;
666 int ret, idx, i;
667 const char *tmp_str;
668 char buffer[16];
669
670 devc = sdi->priv;
671
672 /* If a channel group is specified, it must be a valid one. */
673 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
674 sr_err("Invalid channel group specified.");
675 return SR_ERR;
676 }
677
678 switch (key) {
679 case SR_CONF_LIMIT_FRAMES:
680 devc->limit_frames = g_variant_get_uint64(data);
681 break;
682 case SR_CONF_TRIGGER_SLOPE:
683 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(trigger_slopes))) < 0)
684 return SR_ERR_ARG;
685 g_free(devc->trigger_slope);
686 devc->trigger_slope = g_strdup((trigger_slopes[idx][0] == 'r') ? "POS" : "NEG");
687 return rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
688 case SR_CONF_HORIZ_TRIGGERPOS:
689 t_dbl = g_variant_get_double(data);
690 if (t_dbl < 0.0 || t_dbl > 1.0) {
691 sr_err("Invalid horiz. trigger position: %g.", t_dbl);
692 return SR_ERR;
693 }
694 devc->horiz_triggerpos = t_dbl;
695 /* We have the trigger offset as a percentage of the frame, but
696 * need to express this in seconds. */
697 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
698 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
699 return rigol_ds_config_set(sdi,
700 devc->model->cmds[CMD_SET_HORIZ_TRIGGERPOS].str, buffer);
701 case SR_CONF_TRIGGER_LEVEL:
702 t_dbl = g_variant_get_double(data);
703 g_ascii_formatd(buffer, sizeof(buffer), "%.3f", t_dbl);
704 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:LEV %s", buffer);
705 if (ret == SR_OK)
706 devc->trigger_level = t_dbl;
707 return ret;
708 case SR_CONF_TIMEBASE:
709 if ((idx = std_u64_tuple_idx(data, devc->timebases, devc->num_timebases)) < 0)
710 return SR_ERR_ARG;
711 devc->timebase = (float)devc->timebases[idx][0] / devc->timebases[idx][1];
712 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
713 devc->timebase);
714 return rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
715 case SR_CONF_TRIGGER_SOURCE:
716 if ((idx = std_str_idx(data, devc->model->trigger_sources, devc->model->num_trigger_sources)) < 0)
717 return SR_ERR_ARG;
718 g_free(devc->trigger_source);
719 devc->trigger_source = g_strdup(devc->model->trigger_sources[idx]);
720 if (!strcmp(devc->trigger_source, "AC Line"))
721 tmp_str = "ACL";
722 else if (!strcmp(devc->trigger_source, "CH1"))
723 tmp_str = "CHAN1";
724 else if (!strcmp(devc->trigger_source, "CH2"))
725 tmp_str = "CHAN2";
726 else if (!strcmp(devc->trigger_source, "CH3"))
727 tmp_str = "CHAN3";
728 else if (!strcmp(devc->trigger_source, "CH4"))
729 tmp_str = "CHAN4";
730 else
731 tmp_str = (char *)devc->trigger_source;
732 return rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
733 case SR_CONF_VDIV:
734 if (!cg)
735 return SR_ERR_CHANNEL_GROUP;
736 if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0)
737 return SR_ERR_ARG;
738 if ((idx = std_u64_tuple_idx(data, ARRAY_AND_SIZE(vdivs))) < 0)
739 return SR_ERR_ARG;
740 devc->vdiv[i] = (float)vdivs[idx][0] / vdivs[idx][1];
741 g_ascii_formatd(buffer, sizeof(buffer), "%.3f", devc->vdiv[i]);
742 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1, buffer);
743 case SR_CONF_COUPLING:
744 if (!cg)
745 return SR_ERR_CHANNEL_GROUP;
746 if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0)
747 return SR_ERR_ARG;
748 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(coupling))) < 0)
749 return SR_ERR_ARG;
750 g_free(devc->coupling[i]);
751 devc->coupling[i] = g_strdup(coupling[idx]);
752 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1, devc->coupling[i]);
753 case SR_CONF_PROBE_FACTOR:
754 if (!cg)
755 return SR_ERR_CHANNEL_GROUP;
756 if ((i = std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels)) < 0)
757 return SR_ERR_ARG;
758 if ((idx = std_u64_idx(data, ARRAY_AND_SIZE(probe_factor))) < 0)
759 return SR_ERR_ARG;
760 p = g_variant_get_uint64(data);
761 devc->attenuation[i] = probe_factor[idx];
762 ret = rigol_ds_config_set(sdi, ":CHAN%d:PROB %"PRIu64, i + 1, p);
763 if (ret == SR_OK)
764 rigol_ds_get_dev_cfg_vertical(sdi);
765 return ret;
766 case SR_CONF_DATA_SOURCE:
767 tmp_str = g_variant_get_string(data, NULL);
768 if (!strcmp(tmp_str, "Live"))
769 devc->data_source = DATA_SOURCE_LIVE;
770 else if (devc->model->series->protocol >= PROTOCOL_V2
771 && !strcmp(tmp_str, "Memory"))
772 devc->data_source = DATA_SOURCE_MEMORY;
773 else if (devc->model->series->protocol >= PROTOCOL_V3
774 && !strcmp(tmp_str, "Segmented"))
775 devc->data_source = DATA_SOURCE_SEGMENTED;
776 else {
777 sr_err("Unknown data source: '%s'.", tmp_str);
778 return SR_ERR;
779 }
780 break;
781 default:
782 return SR_ERR_NA;
783 }
784
785 return SR_OK;
786}
787
788static int config_list(uint32_t key, GVariant **data,
789 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
790{
791 struct dev_context *devc;
792
793 devc = (sdi) ? sdi->priv : NULL;
794
795 switch (key) {
796 case SR_CONF_SCAN_OPTIONS:
797 case SR_CONF_DEVICE_OPTIONS:
798 if (!cg)
799 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
800 if (!devc)
801 return SR_ERR_ARG;
802 if (cg == devc->digital_group) {
803 *data = std_gvar_array_u32(NULL, 0);
804 return SR_OK;
805 } else {
806 if (std_cg_idx(cg, devc->analog_groups, devc->model->analog_channels) < 0)
807 return SR_ERR_ARG;
808 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg_analog));
809 return SR_OK;
810 }
811 break;
812 case SR_CONF_COUPLING:
813 if (!cg)
814 return SR_ERR_CHANNEL_GROUP;
815 *data = g_variant_new_strv(ARRAY_AND_SIZE(coupling));
816 break;
817 case SR_CONF_PROBE_FACTOR:
818 if (!cg)
819 return SR_ERR_CHANNEL_GROUP;
820 *data = std_gvar_array_u64(ARRAY_AND_SIZE(probe_factor));
821 break;
822 case SR_CONF_VDIV:
823 if (!devc)
824 /* Can't know this until we have the exact model. */
825 return SR_ERR_ARG;
826 if (!cg)
827 return SR_ERR_CHANNEL_GROUP;
828 *data = std_gvar_tuple_array(devc->vdivs, devc->num_vdivs);
829 break;
830 case SR_CONF_TIMEBASE:
831 if (!devc)
832 /* Can't know this until we have the exact model. */
833 return SR_ERR_ARG;
834 if (devc->num_timebases <= 0)
835 return SR_ERR_NA;
836 *data = std_gvar_tuple_array(devc->timebases, devc->num_timebases);
837 break;
838 case SR_CONF_TRIGGER_SOURCE:
839 if (!devc)
840 /* Can't know this until we have the exact model. */
841 return SR_ERR_ARG;
842 *data = g_variant_new_strv(devc->model->trigger_sources, devc->model->num_trigger_sources);
843 break;
844 case SR_CONF_TRIGGER_SLOPE:
845 *data = g_variant_new_strv(ARRAY_AND_SIZE(trigger_slopes));
846 break;
847 case SR_CONF_DATA_SOURCE:
848 if (!devc)
849 /* Can't know this until we have the exact model. */
850 return SR_ERR_ARG;
851 switch (devc->model->series->protocol) {
852 case PROTOCOL_V1:
853 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
854 break;
855 case PROTOCOL_V2:
856 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
857 break;
858 default:
859 *data = g_variant_new_strv(ARRAY_AND_SIZE(data_sources));
860 break;
861 }
862 break;
863 default:
864 return SR_ERR_NA;
865 }
866
867 return SR_OK;
868}
869
870static int dev_acquisition_start(const struct sr_dev_inst *sdi)
871{
872 struct sr_scpi_dev_inst *scpi;
873 struct dev_context *devc;
874 struct sr_channel *ch;
875 gboolean some_digital;
876 GSList *l;
877 char *cmd;
878 int protocol;
879 int ret;
880
881 scpi = sdi->conn;
882 devc = sdi->priv;
883 protocol = devc->model->series->protocol;
884
885 devc->num_frames = 0;
886 devc->num_frames_segmented = 0;
887
888 some_digital = FALSE;
889 for (l = sdi->channels; l; l = l->next) {
890 ch = l->data;
891 sr_dbg("handling channel %s", ch->name);
892 if (ch->type == SR_CHANNEL_ANALOG) {
893 if (ch->enabled)
894 devc->enabled_channels = g_slist_append(
895 devc->enabled_channels, ch);
896 if (ch->enabled != devc->analog_channels[ch->index]) {
897 /* Enabled channel is currently disabled, or vice versa. */
898 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
899 ch->enabled ? "ON" : "OFF") != SR_OK)
900 return SR_ERR;
901 devc->analog_channels[ch->index] = ch->enabled;
902 }
903 } else if (ch->type == SR_CHANNEL_LOGIC) {
904 /* Only one list entry for older protocols. All channels are
905 * retrieved together when this entry is processed. */
906 if (ch->enabled && (
907 protocol > PROTOCOL_V3 ||
908 !some_digital))
909 devc->enabled_channels = g_slist_append(
910 devc->enabled_channels, ch);
911 if (ch->enabled) {
912 some_digital = TRUE;
913 /* Turn on LA module if currently off. */
914 if (!devc->la_enabled) {
915 if (rigol_ds_config_set(sdi, protocol >= PROTOCOL_V3 ?
916 ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
917 return SR_ERR;
918 devc->la_enabled = TRUE;
919 }
920 }
921 if (ch->enabled != devc->digital_channels[ch->index]) {
922 /* Enabled channel is currently disabled, or vice versa. */
923 if (protocol >= PROTOCOL_V5)
924 cmd = ":LA:DISP D%d,%s";
925 else if (protocol >= PROTOCOL_V3)
926 cmd = ":LA:DIG%d:DISP %s";
927 else
928 cmd = ":DIG%d:TURN %s";
929
930 if (rigol_ds_config_set(sdi, cmd, ch->index,
931 ch->enabled ? "ON" : "OFF") != SR_OK)
932 return SR_ERR;
933 devc->digital_channels[ch->index] = ch->enabled;
934 }
935 }
936 }
937
938 if (!devc->enabled_channels)
939 return SR_ERR;
940
941 /* Turn off LA module if on and no digital channels selected. */
942 if (devc->la_enabled && !some_digital)
943 if (rigol_ds_config_set(sdi,
944 devc->model->series->protocol >= PROTOCOL_V3 ?
945 ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
946 return SR_ERR;
947
948 /* Set memory mode. */
949 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
950 switch (protocol) {
951 case PROTOCOL_V1:
952 case PROTOCOL_V2:
953 /* V1 and V2 do not have segmented data */
954 sr_err("Data source 'Segmented' not supported on this model");
955 break;
956 case PROTOCOL_V3:
957 case PROTOCOL_V4:
958 {
959 int frames = 0;
960 if (sr_scpi_get_int(sdi->conn,
961 protocol == PROTOCOL_V4 ? "FUNC:WREP:FEND?" :
962 "FUNC:WREP:FMAX?", &frames) != SR_OK)
963 return SR_ERR;
964 if (frames <= 0) {
965 sr_err("No segmented data available");
966 return SR_ERR;
967 }
968 devc->num_frames_segmented = frames;
969 break;
970 }
971 case PROTOCOL_V5:
972 /* The frame limit has to be read on the fly, just set up
973 * reading of the first frame */
974 if (rigol_ds_config_set(sdi, "REC:CURR 1") != SR_OK)
975 return SR_ERR;
976 break;
977 default:
978 sr_err("Data source 'Segmented' not yet supported");
979 return SR_ERR;
980 }
981 }
982
983 devc->analog_frame_size = analog_frame_size(sdi);
984 devc->digital_frame_size = digital_frame_size(sdi);
985
986 switch (devc->model->series->protocol) {
987 case PROTOCOL_V2:
988 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
989 return SR_ERR;
990 break;
991 case PROTOCOL_V3:
992 /* Apparently for the DS2000 the memory
993 * depth can only be set in Running state -
994 * this matches the behaviour of the UI. */
995 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
996 return SR_ERR;
997 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
998 devc->analog_frame_size) != SR_OK)
999 return SR_ERR;
1000 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
1001 return SR_ERR;
1002 break;
1003 default:
1004 break;
1005 }
1006
1007 if (devc->data_source == DATA_SOURCE_LIVE)
1008 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1009 return SR_ERR;
1010
1011 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
1012 rigol_ds_receive, (void *)sdi);
1013
1014 std_session_send_df_header(sdi);
1015
1016 devc->channel_entry = devc->enabled_channels;
1017
1018 if (devc->data_source == DATA_SOURCE_LIVE) {
1019 devc->sample_rate = analog_frame_size(sdi) /
1020 (devc->timebase * devc->model->series->num_horizontal_divs);
1021 } else {
1022 float xinc;
1023 if (devc->model->series->protocol < PROTOCOL_V3) {
1024 sr_err("Cannot get samplerate (below V3).");
1025 return SR_ERR;
1026 }
1027 ret = sr_scpi_get_float(sdi->conn, "WAV:XINC?", &xinc);
1028 if (ret != SR_OK) {
1029 sr_err("Cannot get samplerate (WAV:XINC? failed).");
1030 return SR_ERR;
1031 }
1032 if (!xinc) {
1033 sr_err("Cannot get samplerate (zero XINC value).");
1034 return SR_ERR;
1035 }
1036 devc->sample_rate = 1. / xinc;
1037 }
1038
1039 if (rigol_ds_capture_start(sdi) != SR_OK)
1040 return SR_ERR;
1041
1042 /* Start of first frame. */
1043 std_session_send_df_frame_begin(sdi);
1044
1045 return SR_OK;
1046}
1047
1048static int dev_acquisition_stop(struct sr_dev_inst *sdi)
1049{
1050 struct dev_context *devc;
1051 struct sr_scpi_dev_inst *scpi;
1052
1053 devc = sdi->priv;
1054
1055 std_session_send_df_end(sdi);
1056
1057 g_slist_free(devc->enabled_channels);
1058 devc->enabled_channels = NULL;
1059 scpi = sdi->conn;
1060 sr_scpi_source_remove(sdi->session, scpi);
1061
1062 return SR_OK;
1063}
1064
1065static struct sr_dev_driver rigol_ds_driver_info = {
1066 .name = "rigol-ds",
1067 .longname = "Rigol DS",
1068 .api_version = 1,
1069 .init = std_init,
1070 .cleanup = std_cleanup,
1071 .scan = scan,
1072 .dev_list = std_dev_list,
1073 .dev_clear = dev_clear,
1074 .config_get = config_get,
1075 .config_set = config_set,
1076 .config_list = config_list,
1077 .dev_open = dev_open,
1078 .dev_close = dev_close,
1079 .dev_acquisition_start = dev_acquisition_start,
1080 .dev_acquisition_stop = dev_acquisition_stop,
1081 .context = NULL,
1082};
1083SR_REGISTER_DEV_DRIVER(rigol_ds_driver_info);
Hardware access and backend lib