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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2022 Gerhard Sittig <gerhard.sittig@gmx.net> | |
5 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
6 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
7 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
8 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
9 | * | |
10 | * This program is free software: you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation, either version 3 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
22 | */ | |
23 | ||
24 | #include <config.h> | |
25 | ||
26 | #include <libsigrok/libsigrok.h> | |
27 | #include <string.h> | |
28 | ||
29 | #include "libsigrok-internal.h" | |
30 | #include "protocol.h" | |
31 | ||
32 | /* USB PID dependent MCU firmware. Model dependent FPGA bitstream. */ | |
33 | #define MCU_FWFILE_FMT "kingst-la-%04x.fw" | |
34 | #define FPGA_FWFILE_FMT "kingst-%s-fpga.bitstream" | |
35 | ||
36 | /* | |
37 | * List of known devices and their features. See @ref kingst_model | |
38 | * for the fields' type and meaning. Table is sorted by EEPROM magic. | |
39 | * More specific items need to go first (additional byte[2/6]). Not | |
40 | * all devices are covered by this driver implementation, but telling | |
41 | * users what was detected is considered useful. | |
42 | * | |
43 | * TODO Verify the identification of models that were not tested before. | |
44 | */ | |
45 | static const struct kingst_model models[] = { | |
46 | { 2, 1, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, }, | |
47 | { 2, 0, "LA2016", "la2016", SR_MHZ(200), 16, 1, 0, }, | |
48 | { 3, 1, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, }, | |
49 | { 3, 0, "LA1016", "la1016", SR_MHZ(100), 16, 1, 0, }, | |
50 | { 4, 0, "LA1010", "la1010a0", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
51 | { 5, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), }, | |
52 | { 6, 0, "LA5032", "la5032a0", SR_MHZ(500), 32, 4, SR_MHZ(800), }, | |
53 | { 7, 0, "LA1010", "la1010a1", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
54 | { 8, 0, "LA2016", "la2016a1", SR_MHZ(200), 16, 1, 0, }, | |
55 | { 9, 0, "LA1016", "la1016a1", SR_MHZ(100), 16, 1, 0, }, | |
56 | { 10, 0, "LA1010", "la1010a2", SR_MHZ(100), 16, 0, SR_MHZ(800), }, | |
57 | { 65, 0, "LA5016", "la5016a1", SR_MHZ(500), 16, 2, SR_MHZ(800), }, | |
58 | }; | |
59 | ||
60 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ | |
61 | #define CMD_FPGA_ENABLE 0x10 | |
62 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ | |
63 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
64 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
65 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
66 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
67 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
68 | ||
69 | /* | |
70 | * FPGA register addresses (base addresses when registers span multiple | |
71 | * bytes, in that case data is kept in little endian format). Passed to | |
72 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
73 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
74 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
75 | * | |
76 | * Unfortunately the FPGA registers change their meaning between the | |
77 | * read and write directions of access, or exclusively provide one of | |
78 | * these directions and not the other. This is an arbitrary vendor's | |
79 | * choice, there is nothing which the sigrok driver could do about it. | |
80 | * Values written to registers typically cannot get read back, neither | |
81 | * verified after writing a configuration, nor queried upon startup for | |
82 | * automatic detection of the current configuration. Neither appear to | |
83 | * be there echo registers for presence and communication checks, nor | |
84 | * version identifying registers, as far as we know. | |
85 | */ | |
86 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ | |
87 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
88 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
89 | #define REG_PIN_STATE 0x04 /* Read current pin state (real time display). */ | |
90 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
91 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
92 | #define REG_TRIGGER 0x20 /* Write level and edge trigger config. */ | |
93 | #define REG_UNKNOWN_30 0x30 | |
94 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ | |
95 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
96 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
97 | ||
98 | /* Bit patterns to write to REG_CAPT_MODE. */ | |
99 | #define CAPTMODE_TO_RAM 0x00 | |
100 | #define CAPTMODE_STREAM 0x01 | |
101 | ||
102 | /* Bit patterns to write to REG_RUN, setup run mode. */ | |
103 | #define RUNMODE_HALT 0x00 | |
104 | #define RUNMODE_RUN 0x03 | |
105 | ||
106 | /* Bit patterns when reading from REG_RUN, get run state. */ | |
107 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
108 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
109 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
110 | #define RUNSTATE_POST_BIT (1UL << 3) | |
111 | ||
112 | static int ctrl_in(const struct sr_dev_inst *sdi, | |
113 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
114 | void *data, uint16_t wLength) | |
115 | { | |
116 | struct sr_usb_dev_inst *usb; | |
117 | int ret; | |
118 | ||
119 | usb = sdi->conn; | |
120 | ||
121 | ret = libusb_control_transfer(usb->devhdl, | |
122 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
123 | bRequest, wValue, wIndex, data, wLength, | |
124 | DEFAULT_TIMEOUT_MS); | |
125 | if (ret != wLength) { | |
126 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", | |
127 | wLength, bRequest, wValue, wIndex, | |
128 | libusb_error_name(ret)); | |
129 | sr_err("Cannot read %d bytes from USB: %s.", | |
130 | wLength, libusb_error_name(ret)); | |
131 | return SR_ERR_IO; | |
132 | } | |
133 | ||
134 | return SR_OK; | |
135 | } | |
136 | ||
137 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
138 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, | |
139 | void *data, uint16_t wLength) | |
140 | { | |
141 | struct sr_usb_dev_inst *usb; | |
142 | int ret; | |
143 | ||
144 | usb = sdi->conn; | |
145 | ||
146 | ret = libusb_control_transfer(usb->devhdl, | |
147 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
148 | bRequest, wValue, wIndex, data, wLength, | |
149 | DEFAULT_TIMEOUT_MS); | |
150 | if (ret != wLength) { | |
151 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", | |
152 | wLength, bRequest, wValue, wIndex, | |
153 | libusb_error_name(ret)); | |
154 | sr_err("Cannot write %d bytes to USB: %s.", | |
155 | wLength, libusb_error_name(ret)); | |
156 | return SR_ERR_IO; | |
157 | } | |
158 | ||
159 | return SR_OK; | |
160 | } | |
161 | ||
162 | /* HACK Experiment to spot FPGA registers of interest. */ | |
163 | static void la2016_dump_fpga_registers(const struct sr_dev_inst *sdi, | |
164 | const char *caption, size_t reg_lower, size_t reg_upper) | |
165 | { | |
166 | static const size_t dump_chunk_len = 16; | |
167 | ||
168 | size_t rdlen; | |
169 | uint8_t rdbuf[0x80 - 0x00]; /* Span all FPGA registers. */ | |
170 | const uint8_t *rdptr; | |
171 | int ret; | |
172 | size_t dump_addr, indent, dump_len; | |
173 | GString *txt; | |
174 | ||
175 | if (sr_log_loglevel_get() < SR_LOG_SPEW) | |
176 | return; | |
177 | ||
178 | if (!reg_lower && !reg_upper) { | |
179 | reg_lower = 0; | |
180 | reg_upper = sizeof(rdbuf); | |
181 | } | |
182 | if (reg_upper - reg_lower > sizeof(rdbuf)) | |
183 | reg_upper = sizeof(rdbuf) - reg_lower; | |
184 | ||
185 | rdlen = reg_upper - reg_lower; | |
186 | ret = ctrl_in(sdi, CMD_FPGA_SPI, reg_lower, 0, rdbuf, rdlen); | |
187 | if (ret != SR_OK) { | |
188 | sr_err("Cannot get registers space."); | |
189 | return; | |
190 | } | |
191 | rdptr = rdbuf; | |
192 | ||
193 | sr_spew("FPGA registers dump: %s", caption ? : "for fun"); | |
194 | dump_addr = reg_lower; | |
195 | while (rdlen) { | |
196 | dump_len = rdlen; | |
197 | indent = dump_addr % dump_chunk_len; | |
198 | if (dump_len > dump_chunk_len) | |
199 | dump_len = dump_chunk_len; | |
200 | if (dump_len + indent > dump_chunk_len) | |
201 | dump_len = dump_chunk_len - indent; | |
202 | txt = sr_hexdump_new(rdptr, dump_len); | |
203 | sr_spew(" %04zx %*s%s", | |
204 | dump_addr, (int)(3 * indent), "", txt->str); | |
205 | sr_hexdump_free(txt); | |
206 | dump_addr += dump_len; | |
207 | rdptr += dump_len; | |
208 | rdlen -= dump_len; | |
209 | } | |
210 | } | |
211 | ||
212 | /* | |
213 | * Check the necessity for FPGA bitstream upload, because another upload | |
214 | * would take some 600ms which is undesirable after program startup. Try | |
215 | * to access some FPGA registers and check the values' plausibility. The | |
216 | * check should fail on the safe side, request another upload when in | |
217 | * doubt. A positive response (the request to continue operation with the | |
218 | * currently active bitstream) should be conservative. Accessing multiple | |
219 | * registers is considered cheap compared to the cost of bitstream upload. | |
220 | * | |
221 | * It helps though that both the vendor software and the sigrok driver | |
222 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
223 | * supported models. We don't expect to successfully communicate to the | |
224 | * device yet disagree on its protocol. Ideally we would access version | |
225 | * identifying registers for improved robustness, but are not aware of | |
226 | * any. A bitstream reload can always be forced by a power cycle. | |
227 | */ | |
228 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
229 | { | |
230 | uint8_t init_rsp; | |
231 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Larger of REG_RUN, REG_PWM_EN. */ | |
232 | int ret; | |
233 | uint16_t run_state; | |
234 | uint8_t pwm_en; | |
235 | size_t read_len; | |
236 | const uint8_t *rdptr; | |
237 | ||
238 | sr_dbg("Checking operation of the FPGA bitstream."); | |
239 | la2016_dump_fpga_registers(sdi, "bitstream check", 0, 0); | |
240 | ||
241 | init_rsp = ~0; | |
242 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); | |
243 | if (ret != SR_OK || init_rsp != 0) { | |
244 | sr_dbg("FPGA init query failed, or unexpected response."); | |
245 | return SR_ERR_IO; | |
246 | } | |
247 | ||
248 | read_len = sizeof(run_state); | |
249 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
250 | if (ret != SR_OK) { | |
251 | sr_dbg("FPGA register access failed (run state)."); | |
252 | return SR_ERR_IO; | |
253 | } | |
254 | rdptr = buff; | |
255 | run_state = read_u16le_inc(&rdptr); | |
256 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
257 | if (run_state && (run_state & 0x3) != 0x1) { | |
258 | sr_dbg("Unexpected FPGA register content (run state)."); | |
259 | return SR_ERR_DATA; | |
260 | } | |
261 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
262 | sr_dbg("Unexpected FPGA register content (run state)."); | |
263 | return SR_ERR_DATA; | |
264 | } | |
265 | ||
266 | read_len = sizeof(pwm_en); | |
267 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
268 | if (ret != SR_OK) { | |
269 | sr_dbg("FPGA register access failed (PWM enable)."); | |
270 | return SR_ERR_IO; | |
271 | } | |
272 | rdptr = buff; | |
273 | pwm_en = read_u8_inc(&rdptr); | |
274 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
275 | if ((pwm_en & 0x3) != 0x0) { | |
276 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
277 | return SR_ERR_DATA; | |
278 | } | |
279 | ||
280 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
281 | return SR_OK; | |
282 | } | |
283 | ||
284 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, | |
285 | const char *bitstream_fname) | |
286 | { | |
287 | struct drv_context *drvc; | |
288 | struct sr_usb_dev_inst *usb; | |
289 | struct sr_resource bitstream; | |
290 | uint32_t bitstream_size; | |
291 | uint8_t buffer[sizeof(uint32_t)]; | |
292 | uint8_t *wrptr; | |
293 | uint8_t block[4096]; | |
294 | int len, act_len; | |
295 | unsigned int pos; | |
296 | int ret; | |
297 | unsigned int zero_pad_to; | |
298 | ||
299 | drvc = sdi->driver->context; | |
300 | usb = sdi->conn; | |
301 | ||
302 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); | |
303 | ||
304 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, | |
305 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
306 | if (ret != SR_OK) { | |
307 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); | |
308 | return ret; | |
309 | } | |
310 | ||
311 | bitstream_size = (uint32_t)bitstream.size; | |
312 | wrptr = buffer; | |
313 | write_u32le_inc(&wrptr, bitstream_size); | |
314 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); | |
315 | if (ret != SR_OK) { | |
316 | sr_err("Cannot initiate FPGA bitstream upload."); | |
317 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
318 | return ret; | |
319 | } | |
320 | zero_pad_to = bitstream_size; | |
321 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
322 | zero_pad_to /= LA2016_EP2_PADDING; | |
323 | zero_pad_to *= LA2016_EP2_PADDING; | |
324 | ||
325 | pos = 0; | |
326 | while (1) { | |
327 | if (pos < bitstream.size) { | |
328 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, | |
329 | block, sizeof(block)); | |
330 | if (len < 0) { | |
331 | sr_err("Cannot read FPGA bitstream."); | |
332 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
333 | return SR_ERR_IO; | |
334 | } | |
335 | } else { | |
336 | /* Zero-pad until 'zero_pad_to'. */ | |
337 | len = zero_pad_to - pos; | |
338 | if ((unsigned)len > sizeof(block)) | |
339 | len = sizeof(block); | |
340 | memset(&block, 0, len); | |
341 | } | |
342 | if (len == 0) | |
343 | break; | |
344 | ||
345 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, | |
346 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); | |
347 | if (ret != 0) { | |
348 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", | |
349 | pos, (int)len, libusb_error_name(ret)); | |
350 | ret = SR_ERR_IO; | |
351 | break; | |
352 | } | |
353 | if (act_len != len) { | |
354 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", | |
355 | pos, (int)len, act_len); | |
356 | ret = SR_ERR_IO; | |
357 | break; | |
358 | } | |
359 | pos += len; | |
360 | } | |
361 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
362 | if (ret != SR_OK) | |
363 | return ret; | |
364 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", | |
365 | bitstream.size); | |
366 | ||
367 | return SR_OK; | |
368 | } | |
369 | ||
370 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
371 | { | |
372 | int ret; | |
373 | uint8_t resp; | |
374 | ||
375 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); | |
376 | if (ret != SR_OK) { | |
377 | sr_err("Cannot read response after FPGA bitstream upload."); | |
378 | return ret; | |
379 | } | |
380 | if (resp != 0) { | |
381 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", | |
382 | resp); | |
383 | return SR_ERR_DATA; | |
384 | } | |
385 | g_usleep(30 * 1000); | |
386 | ||
387 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); | |
388 | if (ret != SR_OK) { | |
389 | sr_err("Cannot enable FPGA after bitstream upload."); | |
390 | return ret; | |
391 | } | |
392 | g_usleep(40 * 1000); | |
393 | ||
394 | return SR_OK; | |
395 | } | |
396 | ||
397 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
398 | { | |
399 | int ret; | |
400 | uint16_t duty_R79, duty_R56; | |
401 | uint8_t buf[REG_PWM1 - REG_THRESHOLD]; /* Width of REG_THRESHOLD. */ | |
402 | uint8_t *wrptr; | |
403 | ||
404 | /* Clamp threshold setting to valid range for LA2016. */ | |
405 | if (voltage > LA2016_THR_VOLTAGE_MAX) { | |
406 | voltage = LA2016_THR_VOLTAGE_MAX; | |
407 | } else if (voltage < -LA2016_THR_VOLTAGE_MAX) { | |
408 | voltage = -LA2016_THR_VOLTAGE_MAX; | |
409 | } | |
410 | ||
411 | /* | |
412 | * Two PWM output channels feed one DAC which generates a bias | |
413 | * voltage, which offsets the input probe's voltage level, and | |
414 | * in combination with the FPGA pins' fixed threshold result in | |
415 | * a programmable input threshold from the user's perspective. | |
416 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
417 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
418 | * uses three discrete settings. The R56 PWM varies with desired | |
419 | * thresholds and depends on the R79 PWM configuration. See the | |
420 | * schematics comments which discuss the formulae. | |
421 | */ | |
422 | if (voltage >= 2.9) { | |
423 | duty_R79 = 0; /* PWM off (0V). */ | |
424 | duty_R56 = (uint16_t)(302 * voltage - 363); | |
425 | } else if (voltage > -0.4) { | |
426 | duty_R79 = 0x00f2; /* 25% duty cycle. */ | |
427 | duty_R56 = (uint16_t)(302 * voltage + 121); | |
428 | } else { | |
429 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
430 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
431 | } | |
432 | ||
433 | /* Clamp duty register values to sensible limits. */ | |
434 | if (duty_R56 < 10) { | |
435 | duty_R56 = 10; | |
436 | } else if (duty_R56 > 1100) { | |
437 | duty_R56 = 1100; | |
438 | } | |
439 | ||
440 | sr_dbg("Set threshold voltage %.2fV.", voltage); | |
441 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
442 | ||
443 | wrptr = buf; | |
444 | write_u16le_inc(&wrptr, duty_R56); | |
445 | write_u16le_inc(&wrptr, duty_R79); | |
446 | ||
447 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
448 | if (ret != SR_OK) { | |
449 | sr_err("Cannot set threshold voltage %.2fV.", voltage); | |
450 | return ret; | |
451 | } | |
452 | ||
453 | return SR_OK; | |
454 | } | |
455 | ||
456 | /* | |
457 | * Communicates a channel's configuration to the device after the | |
458 | * parameters may have changed. Configuration of one channel may | |
459 | * interfere with other channels since they share FPGA registers. | |
460 | */ | |
461 | static int set_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
462 | { | |
463 | static uint8_t reg_bases[] = { REG_PWM1, REG_PWM2, }; | |
464 | ||
465 | struct dev_context *devc; | |
466 | struct pwm_setting *params; | |
467 | uint8_t reg_base; | |
468 | double val_f; | |
469 | uint32_t val_u; | |
470 | uint32_t period, duty; | |
471 | size_t ch; | |
472 | int ret; | |
473 | uint8_t enable_all, enable_cfg, reg_val; | |
474 | uint8_t buf[REG_PWM2 - REG_PWM1]; /* Width of one REG_PWMx. */ | |
475 | uint8_t *wrptr; | |
476 | ||
477 | devc = sdi->priv; | |
478 | if (idx >= ARRAY_SIZE(devc->pwm_setting)) | |
479 | return SR_ERR_ARG; | |
480 | params = &devc->pwm_setting[idx]; | |
481 | if (idx >= ARRAY_SIZE(reg_bases)) | |
482 | return SR_ERR_ARG; | |
483 | reg_base = reg_bases[idx]; | |
484 | ||
485 | /* | |
486 | * Map application's specs to hardware register values. Do math | |
487 | * in floating point initially, but convert to u32 eventually. | |
488 | */ | |
489 | sr_dbg("PWM config, app spec, ch %zu, en %d, freq %.1f, duty %.1f.", | |
490 | idx, params->enabled ? 1 : 0, params->freq, params->duty); | |
491 | val_f = PWM_CLOCK; | |
492 | val_f /= params->freq; | |
493 | val_u = val_f; | |
494 | period = val_u; | |
495 | val_f = period; | |
496 | val_f *= params->duty; | |
497 | val_f /= 100.0; | |
498 | val_f += 0.5; | |
499 | val_u = val_f; | |
500 | duty = val_u; | |
501 | sr_dbg("PWM config, reg 0x%04x, freq %u, duty %u.", | |
502 | (unsigned)reg_base, (unsigned)period, (unsigned)duty); | |
503 | ||
504 | /* Get the "enabled" state of all supported PWM channels. */ | |
505 | enable_all = 0; | |
506 | for (ch = 0; ch < ARRAY_SIZE(devc->pwm_setting); ch++) { | |
507 | if (!devc->pwm_setting[ch].enabled) | |
508 | continue; | |
509 | enable_all |= 1U << ch; | |
510 | } | |
511 | enable_cfg = 1U << idx; | |
512 | sr_spew("PWM config, enable all 0x%02hhx, cfg 0x%02hhx.", | |
513 | enable_all, enable_cfg); | |
514 | ||
515 | /* | |
516 | * Disable the to-get-configured channel before its parameters | |
517 | * will change. Or disable and exit when the channel is supposed | |
518 | * to get turned off. | |
519 | */ | |
520 | sr_spew("PWM config, disabling before param change."); | |
521 | reg_val = enable_all & ~enable_cfg; | |
522 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
523 | ®_val, sizeof(reg_val)); | |
524 | if (ret != SR_OK) { | |
525 | sr_err("Cannot adjust PWM enabled state."); | |
526 | return ret; | |
527 | } | |
528 | if (!params->enabled) | |
529 | return SR_OK; | |
530 | ||
531 | /* Write register values to device. */ | |
532 | sr_spew("PWM config, sending new parameters."); | |
533 | wrptr = buf; | |
534 | write_u32le_inc(&wrptr, period); | |
535 | write_u32le_inc(&wrptr, duty); | |
536 | ret = ctrl_out(sdi, CMD_FPGA_SPI, reg_base, 0, buf, wrptr - buf); | |
537 | if (ret != SR_OK) { | |
538 | sr_err("Cannot change PWM parameters."); | |
539 | return ret; | |
540 | } | |
541 | ||
542 | /* Enable configured channel after write completion. */ | |
543 | sr_spew("PWM config, enabling after param change."); | |
544 | reg_val = enable_all | enable_cfg; | |
545 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, | |
546 | ®_val, sizeof(reg_val)); | |
547 | if (ret != SR_OK) { | |
548 | sr_err("Cannot adjust PWM enabled state."); | |
549 | return ret; | |
550 | } | |
551 | ||
552 | return SR_OK; | |
553 | } | |
554 | ||
555 | /* | |
556 | * Determine the number of enabled channels as well as their bitmask | |
557 | * representation. Derive data here which later simplifies processing | |
558 | * of raw capture data memory content in streaming mode. | |
559 | */ | |
560 | static void la2016_prepare_stream(const struct sr_dev_inst *sdi) | |
561 | { | |
562 | struct dev_context *devc; | |
563 | struct stream_state_t *stream; | |
564 | size_t channel_mask; | |
565 | GSList *l; | |
566 | struct sr_channel *ch; | |
567 | ||
568 | devc = sdi->priv; | |
569 | stream = &devc->stream; | |
570 | memset(stream, 0, sizeof(*stream)); | |
571 | ||
572 | stream->enabled_count = 0; | |
573 | for (l = sdi->channels; l; l = l->next) { | |
574 | ch = l->data; | |
575 | if (ch->type != SR_CHANNEL_LOGIC) | |
576 | continue; | |
577 | if (!ch->enabled) | |
578 | continue; | |
579 | channel_mask = 1UL << ch->index; | |
580 | stream->enabled_mask |= channel_mask; | |
581 | stream->channel_masks[stream->enabled_count++] = channel_mask; | |
582 | } | |
583 | stream->channel_index = 0; | |
584 | } | |
585 | ||
586 | /* | |
587 | * This routine configures the set of enabled channels, as well as the | |
588 | * trigger condition (if one was specified). Also prepares the capture | |
589 | * data processing in stream mode, where the memory layout dramatically | |
590 | * differs from normal mode. | |
591 | */ | |
592 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
593 | { | |
594 | struct dev_context *devc; | |
595 | struct sr_trigger *trigger; | |
596 | struct trigger_cfg { | |
597 | uint32_t channels; /* Actually: Enabled channels? */ | |
598 | uint32_t enabled; /* Actually: Triggering channels? */ | |
599 | uint32_t level; | |
600 | uint32_t high_or_falling; | |
601 | } cfg; | |
602 | GSList *stages; | |
603 | GSList *channel; | |
604 | struct sr_trigger_stage *stage1; | |
605 | struct sr_trigger_match *match; | |
606 | uint32_t ch_mask; | |
607 | int ret; | |
608 | uint8_t buf[REG_UNKNOWN_30 - REG_TRIGGER]; /* Width of REG_TRIGGER. */ | |
609 | uint8_t *wrptr; | |
610 | ||
611 | devc = sdi->priv; | |
612 | ||
613 | la2016_prepare_stream(sdi); | |
614 | ||
615 | memset(&cfg, 0, sizeof(cfg)); | |
616 | cfg.channels = devc->stream.enabled_mask; | |
617 | if (!cfg.channels) { | |
618 | sr_err("Need at least one enabled logic channel."); | |
619 | return SR_ERR_ARG; | |
620 | } | |
621 | trigger = sr_session_trigger_get(sdi->session); | |
622 | if (trigger && trigger->stages) { | |
623 | stages = trigger->stages; | |
624 | stage1 = stages->data; | |
625 | if (stages->next) { | |
626 | sr_err("Only one trigger stage supported for now."); | |
627 | return SR_ERR_ARG; | |
628 | } | |
629 | channel = stage1->matches; | |
630 | while (channel) { | |
631 | match = channel->data; | |
632 | ch_mask = 1UL << match->channel->index; | |
633 | ||
634 | switch (match->match) { | |
635 | case SR_TRIGGER_ZERO: | |
636 | cfg.level |= ch_mask; | |
637 | cfg.high_or_falling &= ~ch_mask; | |
638 | break; | |
639 | case SR_TRIGGER_ONE: | |
640 | cfg.level |= ch_mask; | |
641 | cfg.high_or_falling |= ch_mask; | |
642 | break; | |
643 | case SR_TRIGGER_RISING: | |
644 | if ((cfg.enabled & ~cfg.level)) { | |
645 | sr_err("Device only supports one edge trigger."); | |
646 | return SR_ERR_ARG; | |
647 | } | |
648 | cfg.level &= ~ch_mask; | |
649 | cfg.high_or_falling &= ~ch_mask; | |
650 | break; | |
651 | case SR_TRIGGER_FALLING: | |
652 | if ((cfg.enabled & ~cfg.level)) { | |
653 | sr_err("Device only supports one edge trigger."); | |
654 | return SR_ERR_ARG; | |
655 | } | |
656 | cfg.level &= ~ch_mask; | |
657 | cfg.high_or_falling |= ch_mask; | |
658 | break; | |
659 | default: | |
660 | sr_err("Unknown trigger condition."); | |
661 | return SR_ERR_ARG; | |
662 | } | |
663 | cfg.enabled |= ch_mask; | |
664 | channel = channel->next; | |
665 | } | |
666 | } | |
667 | sr_dbg("Set trigger config: " | |
668 | "enabled-channels 0x%04x, triggering-channels 0x%04x, " | |
669 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
670 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
671 | ||
672 | /* | |
673 | * Don't configure hardware trigger parameters in streaming mode | |
674 | * or when the device lacks local memory. Yet the above dump of | |
675 | * derived parameters from user specs is considered valueable. | |
676 | * | |
677 | * TODO Add support for soft triggers when hardware triggers in | |
678 | * the device are not used or are not available at all. | |
679 | */ | |
680 | if (!devc->model->memory_bits || devc->continuous) { | |
681 | if (!devc->model->memory_bits) | |
682 | sr_dbg("Device without memory. No hardware triggers."); | |
683 | else if (devc->continuous) | |
684 | sr_dbg("Streaming mode. No hardware triggers."); | |
685 | cfg.enabled = 0; | |
686 | cfg.level = 0; | |
687 | cfg.high_or_falling = 0; | |
688 | } | |
689 | ||
690 | devc->trigger_involved = cfg.enabled != 0; | |
691 | ||
692 | wrptr = buf; | |
693 | write_u32le_inc(&wrptr, cfg.channels); | |
694 | write_u32le_inc(&wrptr, cfg.enabled); | |
695 | write_u32le_inc(&wrptr, cfg.level); | |
696 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
697 | /* TODO | |
698 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
699 | * register offset, nor the transfer length. Is it a channels | |
700 | * count that is relevant for 16 and 32 channel models? Is it | |
701 | * an obsolete experiment? | |
702 | */ | |
703 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); | |
704 | if (ret != SR_OK) { | |
705 | sr_err("Cannot setup trigger configuration."); | |
706 | return ret; | |
707 | } | |
708 | ||
709 | return SR_OK; | |
710 | } | |
711 | ||
712 | /* | |
713 | * This routine communicates the sample configuration to the device: | |
714 | * Total samples count and samplerate, pre-trigger configuration. | |
715 | */ | |
716 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
717 | { | |
718 | struct dev_context *devc; | |
719 | uint64_t baseclock; | |
720 | uint64_t min_samplerate, eff_samplerate; | |
721 | uint64_t stream_bandwidth; | |
722 | uint16_t divider_u16; | |
723 | uint64_t limit_samples; | |
724 | uint64_t pre_trigger_samples; | |
725 | uint64_t pre_trigger_memory; | |
726 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
727 | uint8_t *wrptr; | |
728 | int ret; | |
729 | ||
730 | devc = sdi->priv; | |
731 | ||
732 | /* | |
733 | * The base clock need not be identical to the maximum samplerate, | |
734 | * and differs between models. The 500MHz devices even use a base | |
735 | * clock of 800MHz, and communicate divider 1 to the hardware to | |
736 | * configure the 500MHz samplerate. This allows them to operate at | |
737 | * a 200MHz samplerate which uses divider 4. | |
738 | */ | |
739 | if (devc->samplerate > devc->model->samplerate) { | |
740 | sr_err("Too high a sample rate: %" PRIu64 ".", | |
741 | devc->samplerate); | |
742 | return SR_ERR_ARG; | |
743 | } | |
744 | baseclock = devc->model->baseclock; | |
745 | if (!baseclock) | |
746 | baseclock = devc->model->samplerate; | |
747 | min_samplerate = baseclock; | |
748 | min_samplerate /= 65536; | |
749 | if (devc->samplerate < min_samplerate) { | |
750 | sr_err("Too low a sample rate: %" PRIu64 ".", | |
751 | devc->samplerate); | |
752 | return SR_ERR_ARG; | |
753 | } | |
754 | divider_u16 = baseclock / devc->samplerate; | |
755 | eff_samplerate = baseclock / divider_u16; | |
756 | if (eff_samplerate > devc->model->samplerate) | |
757 | eff_samplerate = devc->model->samplerate; | |
758 | ||
759 | ret = sr_sw_limits_get_remain(&devc->sw_limits, | |
760 | &limit_samples, NULL, NULL, NULL); | |
761 | if (ret != SR_OK) { | |
762 | sr_err("Cannot get acquisition limits."); | |
763 | return ret; | |
764 | } | |
765 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { | |
766 | sr_warn("Too high a sample depth: %" PRIu64 ", capping.", | |
767 | limit_samples); | |
768 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
769 | } | |
770 | if (limit_samples == 0) { | |
771 | limit_samples = LA2016_NUM_SAMPLES_MAX; | |
772 | sr_dbg("Passing %" PRIu64 " to HW for unlimited samples.", | |
773 | limit_samples); | |
774 | } | |
775 | ||
776 | /* | |
777 | * The acquisition configuration communicates "pre-trigger" | |
778 | * specs in several formats. sigrok users provide a percentage | |
779 | * (0-100%), which translates to a pre-trigger samples count | |
780 | * (assuming that a total samples count limit was specified). | |
781 | * The device supports hardware compression, which depends on | |
782 | * slowly changing input data to be effective. Fast changing | |
783 | * input data may occupy more space in sample memory than its | |
784 | * uncompressed form would. This is why a third parameter can | |
785 | * limit the amount of sample memory to use for pre-trigger | |
786 | * data. Only the upper 24 bits of that memory size spec get | |
787 | * communicated to the device (written to its FPGA register). | |
788 | */ | |
789 | if (!devc->model->memory_bits) { | |
790 | sr_dbg("Memory-less device, skipping pre-trigger config."); | |
791 | pre_trigger_samples = 0; | |
792 | pre_trigger_memory = 0; | |
793 | } else if (devc->trigger_involved) { | |
794 | pre_trigger_samples = limit_samples; | |
795 | pre_trigger_samples *= devc->capture_ratio; | |
796 | pre_trigger_samples /= 100; | |
797 | pre_trigger_memory = devc->model->memory_bits; | |
798 | pre_trigger_memory *= UINT64_C(1024 * 1024 * 1024); | |
799 | pre_trigger_memory /= 8; /* devc->model->channel_count ? */ | |
800 | pre_trigger_memory *= devc->capture_ratio; | |
801 | pre_trigger_memory /= 100; | |
802 | } else { | |
803 | sr_dbg("No trigger setup, skipping pre-trigger config."); | |
804 | pre_trigger_samples = 0; | |
805 | pre_trigger_memory = 0; | |
806 | } | |
807 | /* Ensure non-zero value after LSB shift out in HW reg. */ | |
808 | if (pre_trigger_memory < 0x100) | |
809 | pre_trigger_memory = 0x100; | |
810 | ||
811 | sr_dbg("Set sample config: %" PRIu64 "kHz (div %" PRIu16 "), %" PRIu64 " samples.", | |
812 | eff_samplerate / SR_KHZ(1), divider_u16, limit_samples); | |
813 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", | |
814 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
815 | ||
816 | if (devc->continuous) { | |
817 | stream_bandwidth = eff_samplerate; | |
818 | stream_bandwidth *= devc->stream.enabled_count; | |
819 | sr_dbg("Streaming: channel count %zu, product %" PRIu64 ".", | |
820 | devc->stream.enabled_count, stream_bandwidth); | |
821 | stream_bandwidth /= 1000 * 1000; | |
822 | if (stream_bandwidth >= LA2016_STREAM_MBPS_MAX) { | |
823 | sr_warn("High USB stream bandwidth: %" PRIu64 "Mbps.", | |
824 | stream_bandwidth); | |
825 | } | |
826 | if (stream_bandwidth < LA2016_STREAM_PUSH_THR) { | |
827 | sr_dbg("Streaming: low Mbps, suggest periodic flush."); | |
828 | devc->stream.flush_period_ms = LA2016_STREAM_PUSH_IVAL; | |
829 | } | |
830 | } | |
831 | ||
832 | /* | |
833 | * The acquisition configuration occupies a total of 16 bytes: | |
834 | * - A 34bit total samples count limit (up to 10 billions) that | |
835 | * is kept in a 40bit register. | |
836 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
837 | * in another 40bit register. | |
838 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
839 | * the upper 24bits are kept in an FPGA register. | |
840 | * - A 16bit clock divider which gets applied to the maximum | |
841 | * samplerate of the device. | |
842 | * - An 8bit register of unknown meaning. Currently always 0. | |
843 | */ | |
844 | wrptr = buf; | |
845 | write_u40le_inc(&wrptr, limit_samples); | |
846 | write_u40le_inc(&wrptr, pre_trigger_samples); | |
847 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
848 | write_u16le_inc(&wrptr, divider_u16); | |
849 | write_u8_inc(&wrptr, 0); | |
850 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); | |
851 | if (ret != SR_OK) { | |
852 | sr_err("Cannot setup acquisition configuration."); | |
853 | return ret; | |
854 | } | |
855 | ||
856 | return SR_OK; | |
857 | } | |
858 | ||
859 | /* | |
860 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
861 | * of interest: | |
862 | * bit 0: value 1 = idle | |
863 | * bit 1: value 1 = writing to SDRAM | |
864 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
865 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
866 | * The meaning of other bit fields is unknown. | |
867 | * | |
868 | * Typical values in order of appearance during execution: | |
869 | * 0x85e1: idle, no acquisition pending | |
870 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
871 | * "In idle state." Takes precedence over all others. | |
872 | * 0x85e2: pre-sampling, samples before the trigger position, | |
873 | * when capture ratio > 0% | |
874 | * IDLE clear, TRGD clear, POST clear; DRAM don't care | |
875 | * "Not idle any more, no post yet, not triggered yet." | |
876 | * 0x85ea: pre-sampling complete, now waiting for the trigger | |
877 | * (whilst sampling continuously) | |
878 | * IDLE clear, TRGD clear, POST set; DRAM don't care | |
879 | * "Post set thus after pre, not triggered yet" | |
880 | * 0x85ee: trigger seen, capturing post-trigger samples, running | |
881 | * IDLE clear, TRGD set, POST set; DRAM don't care | |
882 | * "Triggered and in post, not idle yet." | |
883 | * 0x85ed: idle | |
884 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
885 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
886 | */ | |
887 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; | |
888 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
889 | static const uint16_t runstate_mask_step = | |
890 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
891 | static const uint16_t runstate_patt_pre_trig = 0; | |
892 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
893 | static const uint16_t runstate_patt_post_trig = | |
894 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
895 | ||
896 | static uint16_t run_state(const struct sr_dev_inst *sdi) | |
897 | { | |
898 | static uint16_t previous_state; | |
899 | ||
900 | int ret; | |
901 | uint16_t state; | |
902 | uint8_t buff[REG_PWM_EN - REG_RUN]; /* Width of REG_RUN. */ | |
903 | const uint8_t *rdptr; | |
904 | const char *label; | |
905 | ||
906 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); | |
907 | if (ret != SR_OK) { | |
908 | sr_err("Cannot read run state."); | |
909 | return ret; | |
910 | } | |
911 | rdptr = buff; | |
912 | state = read_u16le_inc(&rdptr); | |
913 | ||
914 | /* | |
915 | * Avoid flooding the log, only dump values as they change. | |
916 | * The routine is called about every 50ms. | |
917 | */ | |
918 | if (state == previous_state) | |
919 | return state; | |
920 | ||
921 | previous_state = state; | |
922 | label = NULL; | |
923 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
924 | label = "idle"; | |
925 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
926 | label = "pre-trigger sampling"; | |
927 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
928 | label = "sampling, waiting for trigger"; | |
929 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
930 | label = "post-trigger sampling"; | |
931 | if (label && *label) | |
932 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
933 | else | |
934 | sr_dbg("Run state: 0x%04x.", state); | |
935 | ||
936 | return state; | |
937 | } | |
938 | ||
939 | static gboolean la2016_is_idle(const struct sr_dev_inst *sdi) | |
940 | { | |
941 | uint16_t state; | |
942 | ||
943 | state = run_state(sdi); | |
944 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
945 | return TRUE; | |
946 | ||
947 | return FALSE; | |
948 | } | |
949 | ||
950 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
951 | { | |
952 | int ret; | |
953 | ||
954 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); | |
955 | if (ret != SR_OK) { | |
956 | sr_err("Cannot configure run mode %d.", mode); | |
957 | return ret; | |
958 | } | |
959 | ||
960 | return SR_OK; | |
961 | } | |
962 | ||
963 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
964 | { | |
965 | struct dev_context *devc; | |
966 | int ret; | |
967 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
968 | const uint8_t *rdptr; | |
969 | ||
970 | devc = sdi->priv; | |
971 | ||
972 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); | |
973 | if (ret != SR_OK) { | |
974 | sr_err("Cannot read capture info."); | |
975 | return ret; | |
976 | } | |
977 | ||
978 | rdptr = buf; | |
979 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
980 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
981 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
982 | ||
983 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", | |
984 | devc->info.n_rep_packets, devc->info.n_rep_packets, | |
985 | devc->info.n_rep_packets_before_trigger, | |
986 | devc->info.n_rep_packets_before_trigger, | |
987 | devc->info.write_pos, devc->info.write_pos); | |
988 | ||
989 | if (devc->info.n_rep_packets % devc->packets_per_chunk) { | |
990 | sr_warn("Unexpected packets count %lu, not a multiple of %lu.", | |
991 | (unsigned long)devc->info.n_rep_packets, | |
992 | (unsigned long)devc->packets_per_chunk); | |
993 | } | |
994 | ||
995 | return SR_OK; | |
996 | } | |
997 | ||
998 | SR_PRIV int la2016_upload_firmware(const struct sr_dev_inst *sdi, | |
999 | struct sr_context *sr_ctx, libusb_device *dev, gboolean skip_upload) | |
1000 | { | |
1001 | struct dev_context *devc; | |
1002 | uint16_t pid; | |
1003 | char *fw; | |
1004 | int ret; | |
1005 | ||
1006 | devc = sdi ? sdi->priv : NULL; | |
1007 | if (!devc || !devc->usb_pid) | |
1008 | return SR_ERR_ARG; | |
1009 | pid = devc->usb_pid; | |
1010 | ||
1011 | fw = g_strdup_printf(MCU_FWFILE_FMT, pid); | |
1012 | sr_info("USB PID %04hx, MCU firmware '%s'.", pid, fw); | |
1013 | devc->mcu_firmware = g_strdup(fw); | |
1014 | ||
1015 | if (skip_upload) | |
1016 | ret = SR_OK; | |
1017 | else | |
1018 | ret = ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw); | |
1019 | g_free(fw); | |
1020 | if (ret != SR_OK) | |
1021 | return ret; | |
1022 | ||
1023 | return SR_OK; | |
1024 | } | |
1025 | ||
1026 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *xfer); | |
1027 | ||
1028 | static void la2016_usbxfer_release_cb(gpointer p) | |
1029 | { | |
1030 | struct libusb_transfer *xfer; | |
1031 | ||
1032 | xfer = p; | |
1033 | g_free(xfer->buffer); | |
1034 | libusb_free_transfer(xfer); | |
1035 | } | |
1036 | ||
1037 | static int la2016_usbxfer_release(const struct sr_dev_inst *sdi) | |
1038 | { | |
1039 | struct dev_context *devc; | |
1040 | ||
1041 | devc = sdi ? sdi->priv : NULL; | |
1042 | if (!devc) | |
1043 | return SR_ERR_ARG; | |
1044 | ||
1045 | /* Release all USB transfers. */ | |
1046 | g_slist_free_full(devc->transfers, la2016_usbxfer_release_cb); | |
1047 | devc->transfers = NULL; | |
1048 | ||
1049 | return SR_OK; | |
1050 | } | |
1051 | ||
1052 | static int la2016_usbxfer_allocate(const struct sr_dev_inst *sdi) | |
1053 | { | |
1054 | struct dev_context *devc; | |
1055 | size_t bufsize, xfercount; | |
1056 | uint8_t *buffer; | |
1057 | struct libusb_transfer *xfer; | |
1058 | ||
1059 | devc = sdi ? sdi->priv : NULL; | |
1060 | if (!devc) | |
1061 | return SR_ERR_ARG; | |
1062 | ||
1063 | /* Transfers were already allocated before? */ | |
1064 | if (devc->transfers) | |
1065 | return SR_OK; | |
1066 | ||
1067 | /* | |
1068 | * Allocate all USB transfers and their buffers. Arrange for a | |
1069 | * buffer size which is within the device's capabilities, and | |
1070 | * is a multiple of the USB endpoint's size, to make use of the | |
1071 | * RAW_IO performance feature. | |
1072 | * | |
1073 | * Implementation detail: The LA2016_USB_BUFSZ value happens | |
1074 | * to match all those constraints. No additional arithmetics is | |
1075 | * required in this location. | |
1076 | */ | |
1077 | bufsize = LA2016_USB_BUFSZ; | |
1078 | xfercount = LA2016_USB_XFER_COUNT; | |
1079 | while (xfercount--) { | |
1080 | buffer = g_try_malloc(bufsize); | |
1081 | if (!buffer) { | |
1082 | sr_err("Cannot allocate USB transfer buffer."); | |
1083 | return SR_ERR_MALLOC; | |
1084 | } | |
1085 | xfer = libusb_alloc_transfer(0); | |
1086 | if (!xfer) { | |
1087 | sr_err("Cannot allocate USB transfer."); | |
1088 | g_free(buffer); | |
1089 | return SR_ERR_MALLOC; | |
1090 | } | |
1091 | xfer->buffer = buffer; | |
1092 | devc->transfers = g_slist_append(devc->transfers, xfer); | |
1093 | } | |
1094 | devc->transfer_bufsize = bufsize; | |
1095 | ||
1096 | return SR_OK; | |
1097 | } | |
1098 | ||
1099 | static int la2016_usbxfer_cancel_all(const struct sr_dev_inst *sdi) | |
1100 | { | |
1101 | struct dev_context *devc; | |
1102 | GSList *l; | |
1103 | struct libusb_transfer *xfer; | |
1104 | ||
1105 | devc = sdi ? sdi->priv : NULL; | |
1106 | if (!devc) | |
1107 | return SR_ERR_ARG; | |
1108 | ||
1109 | /* Unconditionally cancel the transfer. Ignore errors. */ | |
1110 | for (l = devc->transfers; l; l = l->next) { | |
1111 | xfer = l->data; | |
1112 | if (!xfer) | |
1113 | continue; | |
1114 | libusb_cancel_transfer(xfer); | |
1115 | } | |
1116 | ||
1117 | return SR_OK; | |
1118 | } | |
1119 | ||
1120 | static int la2016_usbxfer_resubmit(const struct sr_dev_inst *sdi, | |
1121 | struct libusb_transfer *xfer) | |
1122 | { | |
1123 | struct dev_context *devc; | |
1124 | struct sr_usb_dev_inst *usb; | |
1125 | libusb_transfer_cb_fn cb; | |
1126 | int ret; | |
1127 | ||
1128 | devc = sdi ? sdi->priv : NULL; | |
1129 | usb = sdi ? sdi->conn : NULL; | |
1130 | if (!devc || !usb) | |
1131 | return SR_ERR_ARG; | |
1132 | ||
1133 | if (!xfer) | |
1134 | return SR_ERR_ARG; | |
1135 | ||
1136 | cb = receive_transfer; | |
1137 | libusb_fill_bulk_transfer(xfer, usb->devhdl, | |
1138 | USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1139 | xfer->buffer, devc->transfer_bufsize, | |
1140 | cb, (void *)sdi, CAPTURE_TIMEOUT_MS); | |
1141 | ret = libusb_submit_transfer(xfer); | |
1142 | if (ret != 0) { | |
1143 | sr_err("Cannot submit USB transfer: %s.", | |
1144 | libusb_error_name(ret)); | |
1145 | return SR_ERR_IO; | |
1146 | } | |
1147 | ||
1148 | return SR_OK; | |
1149 | } | |
1150 | ||
1151 | static int la2016_usbxfer_submit_all(const struct sr_dev_inst *sdi) | |
1152 | { | |
1153 | struct dev_context *devc; | |
1154 | GSList *l; | |
1155 | struct libusb_transfer *xfer; | |
1156 | int ret; | |
1157 | ||
1158 | devc = sdi ? sdi->priv : NULL; | |
1159 | if (!devc) | |
1160 | return SR_ERR_ARG; | |
1161 | ||
1162 | for (l = devc->transfers; l; l = l->next) { | |
1163 | xfer = l->data; | |
1164 | if (!xfer) | |
1165 | return SR_ERR_ARG; | |
1166 | ret = la2016_usbxfer_resubmit(sdi, xfer); | |
1167 | if (ret != SR_OK) | |
1168 | return ret; | |
1169 | } | |
1170 | ||
1171 | return SR_OK; | |
1172 | } | |
1173 | ||
1174 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi, | |
1175 | double voltage) | |
1176 | { | |
1177 | struct dev_context *devc; | |
1178 | int ret; | |
1179 | uint8_t cmd; | |
1180 | ||
1181 | devc = sdi->priv; | |
1182 | ||
1183 | ret = set_threshold_voltage(sdi, voltage); | |
1184 | if (ret != SR_OK) | |
1185 | return ret; | |
1186 | ||
1187 | cmd = devc->continuous ? CAPTMODE_STREAM : CAPTMODE_TO_RAM; | |
1188 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); | |
1189 | if (ret != SR_OK) { | |
1190 | sr_err("Cannot send command to stop sampling."); | |
1191 | return ret; | |
1192 | } | |
1193 | ||
1194 | ret = set_trigger_config(sdi); | |
1195 | if (ret != SR_OK) | |
1196 | return ret; | |
1197 | ||
1198 | ret = set_sample_config(sdi); | |
1199 | if (ret != SR_OK) | |
1200 | return ret; | |
1201 | ||
1202 | return SR_OK; | |
1203 | } | |
1204 | ||
1205 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
1206 | { | |
1207 | struct dev_context *devc; | |
1208 | int ret; | |
1209 | ||
1210 | devc = sdi->priv; | |
1211 | ||
1212 | ret = la2016_usbxfer_allocate(sdi); | |
1213 | if (ret != SR_OK) | |
1214 | return ret; | |
1215 | ||
1216 | if (devc->continuous) { | |
1217 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); | |
1218 | if (ret != SR_OK) | |
1219 | return ret; | |
1220 | ||
1221 | ret = la2016_usbxfer_submit_all(sdi); | |
1222 | if (ret != SR_OK) | |
1223 | return ret; | |
1224 | ||
1225 | /* | |
1226 | * Periodic receive callback will set runmode. This | |
1227 | * activity MUST be close to data reception, a pause | |
1228 | * between these steps breaks the stream's operation. | |
1229 | */ | |
1230 | } else { | |
1231 | ret = set_run_mode(sdi, RUNMODE_RUN); | |
1232 | if (ret != SR_OK) | |
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | return SR_OK; | |
1237 | } | |
1238 | ||
1239 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) | |
1240 | { | |
1241 | struct dev_context *devc; | |
1242 | int ret; | |
1243 | ||
1244 | ret = set_run_mode(sdi, RUNMODE_HALT); | |
1245 | if (ret != SR_OK) | |
1246 | return ret; | |
1247 | ||
1248 | devc = sdi->priv; | |
1249 | if (devc->continuous) | |
1250 | devc->download_finished = TRUE; | |
1251 | ||
1252 | return SR_OK; | |
1253 | } | |
1254 | ||
1255 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
1256 | { | |
1257 | int ret; | |
1258 | ||
1259 | ret = la2016_stop_acquisition(sdi); | |
1260 | if (ret != SR_OK) | |
1261 | return ret; | |
1262 | ||
1263 | (void)la2016_usbxfer_cancel_all(sdi); | |
1264 | ||
1265 | return SR_OK; | |
1266 | } | |
1267 | ||
1268 | static int la2016_start_download(const struct sr_dev_inst *sdi) | |
1269 | { | |
1270 | struct dev_context *devc; | |
1271 | int ret; | |
1272 | uint8_t wrbuf[REG_SAMPLING - REG_BULK]; /* Width of REG_BULK. */ | |
1273 | uint8_t *wrptr; | |
1274 | ||
1275 | devc = sdi->priv; | |
1276 | ||
1277 | ret = get_capture_info(sdi); | |
1278 | if (ret != SR_OK) | |
1279 | return ret; | |
1280 | ||
1281 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets; | |
1282 | devc->n_transfer_packets_to_read /= devc->packets_per_chunk; | |
1283 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read; | |
1284 | devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH; | |
1285 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; | |
1286 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
1287 | ||
1288 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", | |
1289 | devc->n_transfer_packets_to_read, devc->read_pos); | |
1290 | ||
1291 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); | |
1292 | if (ret != SR_OK) { | |
1293 | sr_err("Cannot reset USB bulk state."); | |
1294 | return ret; | |
1295 | } | |
1296 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", | |
1297 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
1298 | wrptr = wrbuf; | |
1299 | write_u32le_inc(&wrptr, devc->read_pos); | |
1300 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
1301 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); | |
1302 | if (ret != SR_OK) { | |
1303 | sr_err("Cannot send USB bulk config."); | |
1304 | return ret; | |
1305 | } | |
1306 | ||
1307 | ret = la2016_usbxfer_submit_all(sdi); | |
1308 | if (ret != SR_OK) { | |
1309 | sr_err("Cannot submit USB bulk transfers."); | |
1310 | return ret; | |
1311 | } | |
1312 | ||
1313 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); | |
1314 | if (ret != SR_OK) { | |
1315 | sr_err("Cannot start USB bulk transfers."); | |
1316 | return ret; | |
1317 | } | |
1318 | ||
1319 | return SR_OK; | |
1320 | } | |
1321 | ||
1322 | /* | |
1323 | * A chunk (received via USB) contains a number of transfers (USB length | |
1324 | * divided by 16) which contain a number of packets (5 per transfer) which | |
1325 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
1326 | */ | |
1327 | static void send_chunk(struct sr_dev_inst *sdi, | |
1328 | const uint8_t *data_buffer, size_t data_length) | |
1329 | { | |
1330 | struct dev_context *devc; | |
1331 | size_t num_xfers, num_pkts; | |
1332 | const uint8_t *rp; | |
1333 | uint32_t sample_value; | |
1334 | size_t repetitions; | |
1335 | uint8_t sample_buff[sizeof(sample_value)]; | |
1336 | ||
1337 | devc = sdi->priv; | |
1338 | ||
1339 | /* Ignore incoming USB data after complete sample data download. */ | |
1340 | if (devc->download_finished) | |
1341 | return; | |
1342 | ||
1343 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { | |
1344 | feed_queue_logic_send_trigger(devc->feed_queue); | |
1345 | devc->trigger_marked = TRUE; | |
1346 | } | |
1347 | ||
1348 | /* | |
1349 | * Adjust the number of remaining bytes to read from the device | |
1350 | * before the processing of the currently received chunk affects | |
1351 | * the variable which holds the number of received bytes. | |
1352 | */ | |
1353 | if (data_length > devc->n_bytes_to_read) | |
1354 | devc->n_bytes_to_read = 0; | |
1355 | else | |
1356 | devc->n_bytes_to_read -= data_length; | |
1357 | ||
1358 | /* Process the received chunk of capture data. */ | |
1359 | sample_value = 0; | |
1360 | rp = data_buffer; | |
1361 | num_xfers = data_length / TRANSFER_PACKET_LENGTH; | |
1362 | while (num_xfers--) { | |
1363 | num_pkts = devc->packets_per_chunk; | |
1364 | while (num_pkts--) { | |
1365 | ||
1366 | /* TODO Verify 32channel layout. */ | |
1367 | if (devc->model->channel_count == 32) | |
1368 | sample_value = read_u32le_inc(&rp); | |
1369 | else if (devc->model->channel_count == 16) | |
1370 | sample_value = read_u16le_inc(&rp); | |
1371 | repetitions = read_u8_inc(&rp); | |
1372 | ||
1373 | devc->total_samples += repetitions; | |
1374 | ||
1375 | write_u32le(sample_buff, sample_value); | |
1376 | feed_queue_logic_submit(devc->feed_queue, | |
1377 | sample_buff, repetitions); | |
1378 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1379 | repetitions); | |
1380 | ||
1381 | if (devc->trigger_involved && !devc->trigger_marked) { | |
1382 | if (!--devc->n_reps_until_trigger) { | |
1383 | feed_queue_logic_send_trigger(devc->feed_queue); | |
1384 | devc->trigger_marked = TRUE; | |
1385 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", | |
1386 | devc->total_samples, | |
1387 | (double)devc->total_samples / devc->samplerate * 1e3); | |
1388 | } | |
1389 | } | |
1390 | } | |
1391 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1392 | } | |
1393 | ||
1394 | /* | |
1395 | * Check for several conditions which shall terminate the | |
1396 | * capture data download: When the amount of capture data in | |
1397 | * the device is exhausted. When the user specified samples | |
1398 | * count limit is reached. | |
1399 | */ | |
1400 | if (!devc->n_bytes_to_read) { | |
1401 | devc->download_finished = TRUE; | |
1402 | } else { | |
1403 | sr_dbg("%" PRIu32 " more bytes to download from the device.", | |
1404 | devc->n_bytes_to_read); | |
1405 | } | |
1406 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { | |
1407 | sr_dbg("Acquisition limit reached."); | |
1408 | devc->download_finished = TRUE; | |
1409 | } | |
1410 | if (devc->download_finished) { | |
1411 | sr_dbg("Download finished, flushing session feed queue."); | |
1412 | feed_queue_logic_flush(devc->feed_queue); | |
1413 | } | |
1414 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); | |
1415 | } | |
1416 | ||
1417 | /* | |
1418 | * Process a chunk of capture data in streaming mode. The memory layout | |
1419 | * is rather different from "normal mode" (see the send_chunk() routine | |
1420 | * above). In streaming mode data is not compressed, and memory cells | |
1421 | * neither contain raw sampled pin values at a given point in time. The | |
1422 | * memory content needs transformation. | |
1423 | * - The memory content can be seen as a sequence of memory cells. | |
1424 | * - Each cell contains samples that correspond to the same channel. | |
1425 | * The next cell contains samples for the next channel, etc. | |
1426 | * - Only enabled channels occupy memory cells. Disabled channels are | |
1427 | * not part of the capture data memory layout. | |
1428 | * - The LSB bit position in a cell is the sample which was taken first | |
1429 | * for this channel. Upper bit positions were taken later. | |
1430 | * | |
1431 | * Implementor's note: This routine is inspired by convert_sample_data() | |
1432 | * in the https://github.com/AlexUg/sigrok implementation. Which in turn | |
1433 | * appears to have been derived from the saleae-logic16 sigrok driver. | |
1434 | * The code is phrased conservatively to verify the layout as discussed | |
1435 | * above, performance was not a priority. Operation was verified with an | |
1436 | * LA2016 device. The memory layout of 32 channel models is yet to get | |
1437 | * determined. | |
1438 | */ | |
1439 | static void stream_data(struct sr_dev_inst *sdi, | |
1440 | const uint8_t *data_buffer, size_t data_length) | |
1441 | { | |
1442 | struct dev_context *devc; | |
1443 | struct stream_state_t *stream; | |
1444 | size_t bit_count; | |
1445 | const uint8_t *rp; | |
1446 | uint32_t sample_value; | |
1447 | uint8_t sample_buff[sizeof(sample_value)]; | |
1448 | size_t bit_idx; | |
1449 | uint32_t ch_mask; | |
1450 | ||
1451 | devc = sdi->priv; | |
1452 | stream = &devc->stream; | |
1453 | ||
1454 | /* Ignore incoming USB data after complete sample data download. */ | |
1455 | if (devc->download_finished) | |
1456 | return; | |
1457 | sr_dbg("Stream mode, got another chunk: %p, length %zu.", | |
1458 | data_buffer, data_length); | |
1459 | ||
1460 | /* TODO Add soft trigger support when in stream mode? */ | |
1461 | ||
1462 | /* | |
1463 | * TODO Are memory cells always as wide as the channel count? | |
1464 | * Are they always 16bits wide? Verify for 32 channel devices. | |
1465 | */ | |
1466 | bit_count = devc->model->channel_count; | |
1467 | if (bit_count == 32) { | |
1468 | data_length /= sizeof(uint32_t); | |
1469 | } else if (bit_count == 16) { | |
1470 | data_length /= sizeof(uint16_t); | |
1471 | } else { | |
1472 | /* | |
1473 | * Unhandled case. Acquisition should not start. | |
1474 | * The statement silences the compiler. | |
1475 | */ | |
1476 | return; | |
1477 | } | |
1478 | rp = data_buffer; | |
1479 | sample_value = 0; | |
1480 | while (data_length--) { | |
1481 | /* Get another entity. */ | |
1482 | if (bit_count == 32) | |
1483 | sample_value = read_u32le_inc(&rp); | |
1484 | else if (bit_count == 16) | |
1485 | sample_value = read_u16le_inc(&rp); | |
1486 | ||
1487 | /* Map the entity's bits to a channel's samples. */ | |
1488 | ch_mask = stream->channel_masks[stream->channel_index]; | |
1489 | for (bit_idx = 0; bit_idx < bit_count; bit_idx++) { | |
1490 | if (sample_value & (1UL << bit_idx)) | |
1491 | stream->sample_data[bit_idx] |= ch_mask; | |
1492 | } | |
1493 | ||
1494 | /* | |
1495 | * Advance to the next channel. Submit a block of | |
1496 | * samples when all channels' data was seen. | |
1497 | */ | |
1498 | stream->channel_index++; | |
1499 | if (stream->channel_index != stream->enabled_count) | |
1500 | continue; | |
1501 | for (bit_idx = 0; bit_idx < bit_count; bit_idx++) { | |
1502 | sample_value = stream->sample_data[bit_idx]; | |
1503 | write_u32le(sample_buff, sample_value); | |
1504 | feed_queue_logic_submit(devc->feed_queue, sample_buff, 1); | |
1505 | } | |
1506 | sr_sw_limits_update_samples_read(&devc->sw_limits, bit_count); | |
1507 | devc->total_samples += bit_count; | |
1508 | memset(stream->sample_data, 0, sizeof(stream->sample_data)); | |
1509 | stream->channel_index = 0; | |
1510 | } | |
1511 | ||
1512 | /* | |
1513 | * Need we count empty or failed USB transfers? This version | |
1514 | * doesn't, assumes that timeouts are perfectly legal because | |
1515 | * transfers are started early, and slow samplerates or trigger | |
1516 | * support in hardware are plausible causes for empty transfers. | |
1517 | * | |
1518 | * TODO Maybe a good condition would be (rather large) a timeout | |
1519 | * after a previous capture data chunk was seen? So that stalled | |
1520 | * streaming gets detected which _is_ an exceptional condition. | |
1521 | * We have observed these when "runmode" is set early but bulk | |
1522 | * transfers start late with a pause after setting the runmode. | |
1523 | */ | |
1524 | if (sr_sw_limits_check(&devc->sw_limits)) { | |
1525 | sr_dbg("Acquisition end reached (sw limits)."); | |
1526 | devc->download_finished = TRUE; | |
1527 | } | |
1528 | if (devc->download_finished) { | |
1529 | sr_dbg("Stream receive done, flushing session feed queue."); | |
1530 | feed_queue_logic_flush(devc->feed_queue); | |
1531 | } | |
1532 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); | |
1533 | } | |
1534 | ||
1535 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1536 | { | |
1537 | struct sr_dev_inst *sdi; | |
1538 | struct dev_context *devc; | |
1539 | gboolean was_cancelled, device_gone; | |
1540 | int ret; | |
1541 | ||
1542 | sdi = transfer->user_data; | |
1543 | devc = sdi->priv; | |
1544 | ||
1545 | was_cancelled = transfer->status == LIBUSB_TRANSFER_CANCELLED; | |
1546 | device_gone = transfer->status == LIBUSB_TRANSFER_NO_DEVICE; | |
1547 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1548 | libusb_error_name(transfer->status), transfer->actual_length); | |
1549 | if (device_gone) { | |
1550 | sr_warn("Lost communication to USB device."); | |
1551 | devc->download_finished = TRUE; | |
1552 | return; | |
1553 | } | |
1554 | ||
1555 | /* | |
1556 | * Implementation detail: A USB transfer timeout is not fatal | |
1557 | * here. We just process whatever was received, empty input is | |
1558 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1559 | * or exhausting the device's captured data will complete the | |
1560 | * sample data download. | |
1561 | */ | |
1562 | if (devc->continuous) | |
1563 | stream_data(sdi, transfer->buffer, transfer->actual_length); | |
1564 | else | |
1565 | send_chunk(sdi, transfer->buffer, transfer->actual_length); | |
1566 | ||
1567 | /* | |
1568 | * Re-submit completed transfers (regardless of timeout or | |
1569 | * data reception), unless the transfer was cancelled when | |
1570 | * the acquisition was terminated or has completed. | |
1571 | */ | |
1572 | if (!was_cancelled && !devc->download_finished) { | |
1573 | ret = la2016_usbxfer_resubmit(sdi, transfer); | |
1574 | if (ret == SR_OK) | |
1575 | return; | |
1576 | devc->download_finished = TRUE; | |
1577 | } | |
1578 | } | |
1579 | ||
1580 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1581 | { | |
1582 | const struct sr_dev_inst *sdi; | |
1583 | struct dev_context *devc; | |
1584 | struct drv_context *drvc; | |
1585 | struct timeval tv; | |
1586 | int ret; | |
1587 | ||
1588 | (void)fd; | |
1589 | (void)revents; | |
1590 | ||
1591 | sdi = cb_data; | |
1592 | devc = sdi->priv; | |
1593 | drvc = sdi->driver->context; | |
1594 | ||
1595 | /* Arrange for the start of stream mode when requested. */ | |
1596 | if (devc->continuous && !devc->frame_begin_sent) { | |
1597 | sr_dbg("First receive callback in stream mode."); | |
1598 | devc->download_finished = FALSE; | |
1599 | devc->trigger_marked = FALSE; | |
1600 | devc->total_samples = 0; | |
1601 | ||
1602 | std_session_send_df_frame_begin(sdi); | |
1603 | devc->frame_begin_sent = TRUE; | |
1604 | ||
1605 | ret = set_run_mode(sdi, RUNMODE_RUN); | |
1606 | if (ret != SR_OK) { | |
1607 | sr_err("Cannot set 'runmode' to 'run'."); | |
1608 | return FALSE; | |
1609 | } | |
1610 | ||
1611 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); | |
1612 | if (ret != SR_OK) { | |
1613 | sr_err("Cannot start USB bulk transfers."); | |
1614 | return FALSE; | |
1615 | } | |
1616 | sr_dbg("Stream data reception initiated."); | |
1617 | } | |
1618 | ||
1619 | /* | |
1620 | * Wait for the acquisition to complete in hardware. | |
1621 | * Periodically check a potentially configured msecs timeout. | |
1622 | */ | |
1623 | if (!devc->continuous && !devc->completion_seen) { | |
1624 | if (!la2016_is_idle(sdi)) { | |
1625 | if (sr_sw_limits_check(&devc->sw_limits)) { | |
1626 | devc->sw_limits.limit_msec = 0; | |
1627 | sr_dbg("Limit reached. Stopping acquisition."); | |
1628 | la2016_stop_acquisition(sdi); | |
1629 | } | |
1630 | /* Not yet ready for sample data download. */ | |
1631 | return TRUE; | |
1632 | } | |
1633 | sr_dbg("Acquisition completion seen (hardware)."); | |
1634 | devc->sw_limits.limit_msec = 0; | |
1635 | devc->completion_seen = TRUE; | |
1636 | devc->download_finished = FALSE; | |
1637 | devc->trigger_marked = FALSE; | |
1638 | devc->total_samples = 0; | |
1639 | ||
1640 | la2016_dump_fpga_registers(sdi, "acquisition complete", 0, 0); | |
1641 | ||
1642 | /* Initiate the download of acquired sample data. */ | |
1643 | std_session_send_df_frame_begin(sdi); | |
1644 | devc->frame_begin_sent = TRUE; | |
1645 | ret = la2016_start_download(sdi); | |
1646 | if (ret != SR_OK) { | |
1647 | sr_err("Cannot start acquisition data download."); | |
1648 | return FALSE; | |
1649 | } | |
1650 | sr_dbg("Acquisition data download started."); | |
1651 | ||
1652 | return TRUE; | |
1653 | } | |
1654 | ||
1655 | /* Handle USB reception. Drives sample data download. */ | |
1656 | memset(&tv, 0, sizeof(tv)); | |
1657 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1658 | ||
1659 | /* | |
1660 | * Periodically flush acquisition data in streaming mode. | |
1661 | * Without this nudge, previously received and accumulated data | |
1662 | * keeps sitting in queues and is not seen by applications. | |
1663 | */ | |
1664 | if (devc->continuous && devc->stream.flush_period_ms) { | |
1665 | uint64_t now, elapsed; | |
1666 | now = g_get_monotonic_time(); | |
1667 | if (!devc->stream.last_flushed) | |
1668 | devc->stream.last_flushed = now; | |
1669 | elapsed = now - devc->stream.last_flushed; | |
1670 | elapsed /= 1000; | |
1671 | if (elapsed >= devc->stream.flush_period_ms) { | |
1672 | sr_dbg("Stream mode, flushing."); | |
1673 | feed_queue_logic_flush(devc->feed_queue); | |
1674 | devc->stream.last_flushed = now; | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | /* Postprocess completion of sample data download. */ | |
1679 | if (devc->download_finished) { | |
1680 | sr_dbg("Download finished, post processing."); | |
1681 | ||
1682 | la2016_stop_acquisition(sdi); | |
1683 | usb_source_remove(sdi->session, drvc->sr_ctx); | |
1684 | ||
1685 | la2016_usbxfer_cancel_all(sdi); | |
1686 | memset(&tv, 0, sizeof(tv)); | |
1687 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1688 | ||
1689 | feed_queue_logic_flush(devc->feed_queue); | |
1690 | feed_queue_logic_free(devc->feed_queue); | |
1691 | devc->feed_queue = NULL; | |
1692 | if (devc->frame_begin_sent) { | |
1693 | std_session_send_df_frame_end(sdi); | |
1694 | devc->frame_begin_sent = FALSE; | |
1695 | } | |
1696 | std_session_send_df_end(sdi); | |
1697 | ||
1698 | sr_dbg("Download finished, done post processing."); | |
1699 | } | |
1700 | ||
1701 | return TRUE; | |
1702 | } | |
1703 | ||
1704 | SR_PRIV int la2016_identify_device(const struct sr_dev_inst *sdi, | |
1705 | gboolean show_message) | |
1706 | { | |
1707 | struct dev_context *devc; | |
1708 | uint8_t buf[8]; /* Larger size of manuf date and device type magic. */ | |
1709 | size_t rdoff, rdlen; | |
1710 | const uint8_t *rdptr; | |
1711 | uint8_t date_yy, date_mm; | |
1712 | uint8_t dinv_yy, dinv_mm; | |
1713 | uint8_t magic, magic2; | |
1714 | size_t model_idx; | |
1715 | const struct kingst_model *model; | |
1716 | int ret; | |
1717 | ||
1718 | devc = sdi->priv; | |
1719 | ||
1720 | /* | |
1721 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, | |
1722 | * year and month in BCD format, followed by inverted values for | |
1723 | * consistency checks. For example bytes 20 04 df fb translate | |
1724 | * to 2020-04. This information can help identify the vintage of | |
1725 | * devices when unknown magic numbers are seen. | |
1726 | */ | |
1727 | rdoff = 0x20; | |
1728 | rdlen = 4 * sizeof(uint8_t); | |
1729 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, buf, rdlen); | |
1730 | if (ret != SR_OK && !show_message) { | |
1731 | /* Non-fatal weak attempt during probe. Not worth logging. */ | |
1732 | sr_dbg("Cannot access EEPROM."); | |
1733 | return SR_ERR_IO; | |
1734 | } else if (ret != SR_OK) { | |
1735 | /* Failed attempt in regular use. Non-fatal. Worth logging. */ | |
1736 | sr_err("Cannot read manufacture date in EEPROM."); | |
1737 | } else { | |
1738 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { | |
1739 | GString *txt; | |
1740 | txt = sr_hexdump_new(buf, rdlen); | |
1741 | sr_spew("Manufacture date bytes %s.", txt->str); | |
1742 | sr_hexdump_free(txt); | |
1743 | } | |
1744 | rdptr = &buf[0]; | |
1745 | date_yy = read_u8_inc(&rdptr); | |
1746 | date_mm = read_u8_inc(&rdptr); | |
1747 | dinv_yy = read_u8_inc(&rdptr); | |
1748 | dinv_mm = read_u8_inc(&rdptr); | |
1749 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1750 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1751 | sr_warn("Manufacture date fails checksum test."); | |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * Several Kingst logic analyzer devices share the same USB VID | |
1756 | * and PID. The product ID determines which MCU firmware to load. | |
1757 | * The MCU firmware provides access to EEPROM content which then | |
1758 | * allows to identify the device model. Which in turn determines | |
1759 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1760 | * to get inspected. | |
1761 | * | |
1762 | * EEPROM content for model identification is kept redundantly | |
1763 | * in memory. The values are stored in verbatim and in inverted | |
1764 | * form, multiple copies are kept at different offsets. Example | |
1765 | * data: | |
1766 | * | |
1767 | * magic 0x08 | |
1768 | * | ~magic 0xf7 | |
1769 | * | | | |
1770 | * 08f7000008f710ef | |
1771 | * | | | |
1772 | * | ~magic backup | |
1773 | * magic backup | |
1774 | * | |
1775 | * Exclusively inspecting the magic byte appears to be sufficient, | |
1776 | * other fields seem to be 'don't care'. | |
1777 | * | |
1778 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" | |
1779 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1780 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1781 | * (latest v1.3.0 PCB, perhaps others) | |
1782 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1783 | * (latest v1.3.0 PCB, perhaps others) | |
1784 | * | |
1785 | * When EEPROM content does not match the hardware configuration | |
1786 | * (the board layout), the software may load but yield incorrect | |
1787 | * results (like swapped channels). The FPGA bitstream itself | |
1788 | * will authenticate with IC U10 and fail when its capabilities | |
1789 | * do not match the hardware model. An LA1016 won't become a | |
1790 | * LA2016 by faking its EEPROM content. | |
1791 | */ | |
1792 | devc->identify_magic = 0; | |
1793 | rdoff = 0x08; | |
1794 | rdlen = 8 * sizeof(uint8_t); | |
1795 | ret = ctrl_in(sdi, CMD_EEPROM, rdoff, 0, &buf, rdlen); | |
1796 | if (ret != SR_OK) { | |
1797 | sr_err("Cannot read EEPROM device identifier bytes."); | |
1798 | return ret; | |
1799 | } | |
1800 | if (sr_log_loglevel_get() >= SR_LOG_SPEW) { | |
1801 | GString *txt; | |
1802 | txt = sr_hexdump_new(buf, rdlen); | |
1803 | sr_spew("EEPROM magic bytes %s.", txt->str); | |
1804 | sr_hexdump_free(txt); | |
1805 | } | |
1806 | magic = 0; | |
1807 | magic2 = 0; | |
1808 | if ((buf[0] ^ buf[1]) == 0xff && (buf[2] ^ buf[3]) == 0xff) { | |
1809 | /* Primary copy of magic passes complement check (4 bytes). */ | |
1810 | magic = buf[0]; | |
1811 | magic2 = buf[2]; | |
1812 | sr_dbg("Using primary magic %hhu (%hhu).", magic, magic2); | |
1813 | } else if ((buf[4] ^ buf[5]) == 0xff && (buf[6] ^ buf[7]) == 0xff) { | |
1814 | /* Backup copy of magic passes complement check (4 bytes). */ | |
1815 | magic = buf[4]; | |
1816 | magic2 = buf[6]; | |
1817 | sr_dbg("Using secondary magic %hhu (%hhu).", magic, magic2); | |
1818 | } else if ((buf[0] ^ buf[1]) == 0xff) { | |
1819 | /* Primary copy of magic passes complement check (2 bytes). */ | |
1820 | magic = buf[0]; | |
1821 | sr_dbg("Using primary magic %hhu.", magic); | |
1822 | } else if ((buf[4] ^ buf[5]) == 0xff) { | |
1823 | /* Backup copy of magic passes complement check (2 bytes). */ | |
1824 | magic = buf[4]; | |
1825 | sr_dbg("Using secondary magic %hhu.", magic); | |
1826 | } else { | |
1827 | sr_err("Cannot find consistent device type identification."); | |
1828 | } | |
1829 | devc->identify_magic = magic; | |
1830 | devc->identify_magic2 = magic2; | |
1831 | ||
1832 | devc->model = NULL; | |
1833 | for (model_idx = 0; model_idx < ARRAY_SIZE(models); model_idx++) { | |
1834 | model = &models[model_idx]; | |
1835 | if (model->magic != magic) | |
1836 | continue; | |
1837 | if (model->magic2 && model->magic2 != magic2) | |
1838 | continue; | |
1839 | devc->model = model; | |
1840 | sr_info("Model '%s', %zu channels, max %" PRIu64 "MHz.", | |
1841 | model->name, model->channel_count, | |
1842 | model->samplerate / SR_MHZ(1)); | |
1843 | devc->fpga_bitstream = g_strdup_printf(FPGA_FWFILE_FMT, | |
1844 | model->fpga_stem); | |
1845 | sr_info("FPGA bitstream file '%s'.", devc->fpga_bitstream); | |
1846 | if (!model->channel_count) { | |
1847 | sr_warn("Device lacks logic channels. Not supported."); | |
1848 | devc->model = NULL; | |
1849 | } | |
1850 | break; | |
1851 | } | |
1852 | if (!devc->model) { | |
1853 | sr_err("Cannot identify as one of the supported models."); | |
1854 | return SR_ERR_DATA; | |
1855 | } | |
1856 | ||
1857 | return SR_OK; | |
1858 | } | |
1859 | ||
1860 | SR_PRIV int la2016_init_hardware(const struct sr_dev_inst *sdi) | |
1861 | { | |
1862 | struct dev_context *devc; | |
1863 | const char *bitstream_fn; | |
1864 | int ret; | |
1865 | uint16_t state; | |
1866 | ||
1867 | devc = sdi->priv; | |
1868 | bitstream_fn = devc ? devc->fpga_bitstream : ""; | |
1869 | ||
1870 | ret = check_fpga_bitstream(sdi); | |
1871 | if (ret != SR_OK) { | |
1872 | ret = upload_fpga_bitstream(sdi, bitstream_fn); | |
1873 | if (ret != SR_OK) { | |
1874 | sr_err("Cannot upload FPGA bitstream."); | |
1875 | return ret; | |
1876 | } | |
1877 | } | |
1878 | ret = enable_fpga_bitstream(sdi); | |
1879 | if (ret != SR_OK) { | |
1880 | sr_err("Cannot enable FPGA bitstream after upload."); | |
1881 | return ret; | |
1882 | } | |
1883 | ||
1884 | state = run_state(sdi); | |
1885 | if ((state & 0xfff0) != 0x85e0) { | |
1886 | sr_warn("Unexpected run state, want 0x85eX, got 0x%04x.", state); | |
1887 | } | |
1888 | ||
1889 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); | |
1890 | if (ret != SR_OK) { | |
1891 | sr_err("Cannot reset USB bulk transfer."); | |
1892 | return ret; | |
1893 | } | |
1894 | ||
1895 | sr_dbg("Device should be initialized."); | |
1896 | ||
1897 | return SR_OK; | |
1898 | } | |
1899 | ||
1900 | SR_PRIV int la2016_deinit_hardware(const struct sr_dev_inst *sdi) | |
1901 | { | |
1902 | int ret; | |
1903 | ||
1904 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0); | |
1905 | if (ret != SR_OK) { | |
1906 | sr_err("Cannot deinitialize device's FPGA."); | |
1907 | return ret; | |
1908 | } | |
1909 | ||
1910 | return SR_OK; | |
1911 | } | |
1912 | ||
1913 | SR_PRIV void la2016_release_resources(const struct sr_dev_inst *sdi) | |
1914 | { | |
1915 | (void)la2016_usbxfer_release(sdi); | |
1916 | } | |
1917 | ||
1918 | SR_PRIV int la2016_write_pwm_config(const struct sr_dev_inst *sdi, size_t idx) | |
1919 | { | |
1920 | return set_pwm_config(sdi, idx); | |
1921 | } |