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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
5 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
6 | * | |
7 | * This program is free software: you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation, either version 3 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
21 | #ifndef LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H | |
22 | #define LIBSIGROK_HARDWARE_DSLOGIC_DSLOGIC_H | |
23 | ||
24 | /* Modified protocol commands & flags used by DSLogic */ | |
25 | #define DS_CMD_GET_FW_VERSION 0xb0 | |
26 | #define DS_CMD_GET_REVID_VERSION 0xb1 | |
27 | #define DS_CMD_START 0xb2 | |
28 | #define DS_CMD_CONFIG 0xb3 | |
29 | #define DS_CMD_SETTING 0xb4 | |
30 | #define DS_CMD_CONTROL 0xb5 | |
31 | #define DS_CMD_STATUS 0xb6 | |
32 | #define DS_CMD_STATUS_INFO 0xb7 | |
33 | #define DS_CMD_WR_REG 0xb8 | |
34 | #define DS_CMD_WR_NVM 0xb9 | |
35 | #define DS_CMD_RD_NVM 0xba | |
36 | #define DS_CMD_RD_NVM_PRE 0xbb | |
37 | #define DS_CMD_GET_HW_INFO 0xbc | |
38 | ||
39 | #define DS_START_FLAGS_STOP (1 << 7) | |
40 | #define DS_START_FLAGS_CLK_48MHZ (1 << 6) | |
41 | #define DS_START_FLAGS_SAMPLE_WIDE (1 << 5) | |
42 | #define DS_START_FLAGS_MODE_LA (1 << 4) | |
43 | ||
44 | #define DS_ADDR_COMB 0x68 | |
45 | #define DS_ADDR_EEWP 0x70 | |
46 | #define DS_ADDR_VTH 0x78 | |
47 | ||
48 | #define DS_MAX_LOGIC_DEPTH SR_MHZ(16) | |
49 | #define DS_MAX_LOGIC_SAMPLERATE SR_MHZ(100) | |
50 | #define DS_MAX_TRIG_PERCENT 90 | |
51 | ||
52 | #define DS_MODE_TRIG_EN (1 << 0) | |
53 | #define DS_MODE_CLK_TYPE (1 << 1) | |
54 | #define DS_MODE_CLK_EDGE (1 << 2) | |
55 | #define DS_MODE_RLE_MODE (1 << 3) | |
56 | #define DS_MODE_DSO_MODE (1 << 4) | |
57 | #define DS_MODE_HALF_MODE (1 << 5) | |
58 | #define DS_MODE_QUAR_MODE (1 << 6) | |
59 | #define DS_MODE_ANALOG_MODE (1 << 7) | |
60 | #define DS_MODE_FILTER (1 << 8) | |
61 | #define DS_MODE_INSTANT (1 << 9) | |
62 | #define DS_MODE_STRIG_MODE (1 << 11) | |
63 | #define DS_MODE_STREAM_MODE (1 << 12) | |
64 | #define DS_MODE_LPB_TEST (1 << 13) | |
65 | #define DS_MODE_EXT_TEST (1 << 14) | |
66 | #define DS_MODE_INT_TEST (1 << 15) | |
67 | ||
68 | #define DSLOGIC_ATOMIC_SAMPLES (1 << 6) | |
69 | ||
70 | enum dslogic_operation_modes { | |
71 | DS_OP_NORMAL, | |
72 | DS_OP_INTERNAL_TEST, | |
73 | DS_OP_EXTERNAL_TEST, | |
74 | DS_OP_LOOPBACK_TEST, | |
75 | }; | |
76 | ||
77 | enum { | |
78 | DS_EDGE_RISING, | |
79 | DS_EDGE_FALLING, | |
80 | }; | |
81 | ||
82 | struct dslogic_version { | |
83 | uint8_t major; | |
84 | uint8_t minor; | |
85 | }; | |
86 | ||
87 | struct dslogic_mode { | |
88 | uint8_t flags; | |
89 | uint8_t sample_delay_h; | |
90 | uint8_t sample_delay_l; | |
91 | }; | |
92 | ||
93 | struct dslogic_trigger_pos { | |
94 | uint32_t real_pos; | |
95 | uint32_t ram_saddr; | |
96 | uint32_t remain_cnt; | |
97 | uint8_t first_block[500]; | |
98 | }; | |
99 | ||
100 | /* | |
101 | * The FPGA is configured with TLV tuples. Length is specified as the | |
102 | * number of 16-bit words. | |
103 | */ | |
104 | #define _DS_CFG(variable, wordcnt) ((variable << 8) | wordcnt) | |
105 | #define DS_CFG_START 0xf5a5f5a5 | |
106 | #define DS_CFG_MODE _DS_CFG(0, 1) | |
107 | #define DS_CFG_DIVIDER _DS_CFG(1, 2) | |
108 | #define DS_CFG_COUNT _DS_CFG(3, 2) | |
109 | #define DS_CFG_TRIG_POS _DS_CFG(5, 2) | |
110 | #define DS_CFG_TRIG_GLB _DS_CFG(7, 1) | |
111 | #define DS_CFG_CH_EN _DS_CFG(8, 1) | |
112 | #define DS_CFG_TRIG _DS_CFG(64, 160) | |
113 | #define DS_CFG_END 0xfa5afa5a | |
114 | ||
115 | #pragma pack(push, 1) | |
116 | ||
117 | struct dslogic_fpga_config { | |
118 | uint32_t sync; | |
119 | ||
120 | uint16_t mode_header; | |
121 | uint16_t mode; | |
122 | uint16_t divider_header; | |
123 | uint32_t divider; | |
124 | uint16_t count_header; | |
125 | uint32_t count; | |
126 | uint16_t trig_pos_header; | |
127 | uint32_t trig_pos; | |
128 | uint16_t trig_glb_header; | |
129 | uint16_t trig_glb; | |
130 | uint16_t ch_en_header; | |
131 | uint16_t ch_en; | |
132 | ||
133 | uint16_t trig_header; | |
134 | uint16_t trig_mask0[NUM_TRIGGER_STAGES]; | |
135 | uint16_t trig_mask1[NUM_TRIGGER_STAGES]; | |
136 | uint16_t trig_value0[NUM_TRIGGER_STAGES]; | |
137 | uint16_t trig_value1[NUM_TRIGGER_STAGES]; | |
138 | uint16_t trig_edge0[NUM_TRIGGER_STAGES]; | |
139 | uint16_t trig_edge1[NUM_TRIGGER_STAGES]; | |
140 | uint16_t trig_logic0[NUM_TRIGGER_STAGES]; | |
141 | uint16_t trig_logic1[NUM_TRIGGER_STAGES]; | |
142 | uint32_t trig_count[NUM_TRIGGER_STAGES]; | |
143 | ||
144 | uint32_t end_sync; | |
145 | }; | |
146 | ||
147 | #pragma pack(pop) | |
148 | ||
149 | SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi); | |
150 | SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi); | |
151 | SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi); | |
152 | SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi); | |
153 | SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc); | |
154 | ||
155 | #endif |