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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #ifndef LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
24 | #define LIBSIGROK_HARDWARE_ASIX_SIGMA_PROTOCOL_H | |
25 | ||
26 | #include <stdint.h> | |
27 | #include <stdlib.h> | |
28 | #include <glib.h> | |
29 | #include <ftdi.h> | |
30 | #include <string.h> | |
31 | #include <libsigrok/libsigrok.h> | |
32 | #include "libsigrok-internal.h" | |
33 | ||
34 | #define LOG_PREFIX "asix-sigma" | |
35 | ||
36 | /* | |
37 | * Triggers are not working in this implementation. Stop claiming | |
38 | * support for the feature which effectively is not available, until | |
39 | * the implementation got fixed. Yet keep the code in place and allow | |
40 | * developers to turn on this switch during development. | |
41 | */ | |
42 | #define ASIX_SIGMA_WITH_TRIGGER 1 | |
43 | ||
44 | /* Experimental support for OMEGA (scan only, operation is ENOIMPL). */ | |
45 | #define ASIX_WITH_OMEGA 0 | |
46 | ||
47 | #define USB_VENDOR_ASIX 0xa600 | |
48 | #define USB_PRODUCT_SIGMA 0xa000 | |
49 | #define USB_PRODUCT_OMEGA 0xa004 | |
50 | ||
51 | enum asix_device_type { | |
52 | ASIX_TYPE_NONE, | |
53 | ASIX_TYPE_SIGMA, | |
54 | ASIX_TYPE_OMEGA, | |
55 | }; | |
56 | ||
57 | /* Mask to isolate one bit, mask to span a number of bits. */ | |
58 | #define BIT(pos) (1UL << (pos)) | |
59 | #define BITS_MASK(count) ((1UL << (count)) - 1) | |
60 | ||
61 | #define HI4(b) (((b) >> 4) & 0x0f) | |
62 | #define LO4(b) (((b) >> 0) & 0x0f) | |
63 | ||
64 | /* | |
65 | * FPGA commands are 8bits wide. The upper nibble is a command opcode, | |
66 | * the lower nibble can carry operand values. 8bit register addresses | |
67 | * and 8bit data values get communicated in two steps. | |
68 | */ | |
69 | ||
70 | /* Register access. */ | |
71 | #define REG_ADDR_LOW (0x0 << 4) | |
72 | #define REG_ADDR_HIGH (0x1 << 4) | |
73 | #define REG_DATA_LOW (0x2 << 4) | |
74 | #define REG_DATA_HIGH_WRITE (0x3 << 4) | |
75 | #define REG_READ_ADDR (0x4 << 4) | |
76 | #define REG_ADDR_ADJUST BIT(0) /* Auto adjust register address. */ | |
77 | #define REG_ADDR_DOWN BIT(1) /* 1 decrement, 0 increment. */ | |
78 | #define REG_ADDR_INC (REG_ADDR_ADJUST) | |
79 | #define REG_ADDR_DEC (REG_ADDR_ADJUST | REG_ADDR_DOWN) | |
80 | ||
81 | /* Sample memory access. */ | |
82 | #define REG_DRAM_WAIT_ACK (0x5 << 4) /* Wait for completion. */ | |
83 | #define REG_DRAM_BLOCK (0x6 << 4) /* DRAM to BRAM, plus bank select. */ | |
84 | #define REG_DRAM_BLOCK_BEGIN (0x8 << 4) /* Read first BRAM bytes. */ | |
85 | #define REG_DRAM_BLOCK_DATA (0xa << 4) /* Read full BRAM block. */ | |
86 | #define REG_DRAM_SEL_N (0x1 << 4) /* Bank select, added to 6/8/a. */ | |
87 | #define REG_DRAM_SEL_BOOL(b) ((b) ? REG_DRAM_SEL_N : 0) | |
88 | ||
89 | /* | |
90 | * Registers at a specific address can have different meanings depending | |
91 | * on whether data is read or written. This is why direction is part of | |
92 | * the programming language identifiers. | |
93 | * | |
94 | * The vendor documentation suggests that in addition to the first 16 | |
95 | * register addresses which implement the logic analyzer's feature set, | |
96 | * there are 240 more registers in the 16 to 255 address range which | |
97 | * are available to applications and plugin features. Can libsigrok's | |
98 | * asix-sigma driver store configuration data there, to avoid expensive | |
99 | * operations (think: firmware re-load). | |
100 | * | |
101 | * Update: The documentation may be incorrect, or the FPGA netlist may | |
102 | * be incomplete. Experiments show that registers beyond 0x0f can get | |
103 | * accessed, USB communication passes, but data bytes are always 0xff. | |
104 | * Are several firmware versions around, and the documentation does not | |
105 | * match the one that ships with sigrok? | |
106 | */ | |
107 | ||
108 | enum sigma_write_register { | |
109 | WRITE_CLOCK_SELECT = 0, | |
110 | WRITE_TRIGGER_SELECT = 1, | |
111 | WRITE_TRIGGER_SELECT2 = 2, | |
112 | WRITE_MODE = 3, | |
113 | WRITE_MEMROW = 4, | |
114 | WRITE_POST_TRIGGER = 5, | |
115 | WRITE_TRIGGER_OPTION = 6, | |
116 | WRITE_PIN_VIEW = 7, | |
117 | /* Unassigned register locations. */ | |
118 | WRITE_TEST = 15, | |
119 | /* Reserved for plugin features. */ | |
120 | REG_PLUGIN_START = 16, | |
121 | REG_PLUGIN_STOP = 256, | |
122 | }; | |
123 | ||
124 | enum sigma_read_register { | |
125 | READ_ID = 0, | |
126 | READ_TRIGGER_POS_LOW = 1, | |
127 | READ_TRIGGER_POS_HIGH = 2, | |
128 | READ_TRIGGER_POS_UP = 3, | |
129 | READ_STOP_POS_LOW = 4, | |
130 | READ_STOP_POS_HIGH = 5, | |
131 | READ_STOP_POS_UP = 6, | |
132 | READ_MODE = 7, | |
133 | READ_PIN_CHANGE_LOW = 8, | |
134 | READ_PIN_CHANGE_HIGH = 9, | |
135 | READ_BLOCK_LAST_TS_LOW = 10, | |
136 | READ_BLOCK_LAST_TS_HIGH = 11, | |
137 | READ_BLOCK_TS_OVERRUN = 12, | |
138 | READ_PIN_VIEW = 13, | |
139 | /* Unassigned register location. */ | |
140 | READ_TEST = 15, | |
141 | /* Reserved for plugin features. See above. */ | |
142 | }; | |
143 | ||
144 | #define CLKSEL_CLKSEL8 BIT(0) | |
145 | #define CLKSEL_PINMASK BITS_MASK(4) | |
146 | #define CLKSEL_RISING BIT(4) | |
147 | #define CLKSEL_FALLING BIT(5) | |
148 | ||
149 | #define TRGSEL_SELINC_MASK BITS_MASK(2) | |
150 | #define TRGSEL_SELINC_SHIFT 0 | |
151 | #define TRGSEL_SELRES_MASK BITS_MASK(2) | |
152 | #define TRGSEL_SELRES_SHIFT 2 | |
153 | #define TRGSEL_SELA_MASK BITS_MASK(2) | |
154 | #define TRGSEL_SELA_SHIFT 4 | |
155 | #define TRGSEL_SELB_MASK BITS_MASK(2) | |
156 | #define TRGSEL_SELB_SHIFT 6 | |
157 | #define TRGSEL_SELC_MASK BITS_MASK(2) | |
158 | #define TRGSEL_SELC_SHIFT 8 | |
159 | #define TRGSEL_SELPRESC_MASK BITS_MASK(4) | |
160 | #define TRGSEL_SELPRESC_SHIFT 12 | |
161 | ||
162 | enum trgsel_selcode_t { | |
163 | TRGSEL_SELCODE_LEVEL = 0, | |
164 | TRGSEL_SELCODE_FALL = 1, | |
165 | TRGSEL_SELCODE_RISE = 2, | |
166 | TRGSEL_SELCODE_EVENT = 3, | |
167 | TRGSEL_SELCODE_NEVER = 3, | |
168 | }; | |
169 | ||
170 | #define TRGSEL2_PINS_MASK BITS_MASK(3) | |
171 | #define TRGSEL2_PINPOL_RISE BIT(3) | |
172 | #define TRGSEL2_LUT_ADDR_MASK BITS_MASK(4) | |
173 | #define TRGSEL2_LUT_WRITE BIT(4) | |
174 | #define TRGSEL2_RESET BIT(5) | |
175 | #define TRGSEL2_LEDSEL0 BIT(6) | |
176 | #define TRGSEL2_LEDSEL1 BIT(7) | |
177 | ||
178 | /* WRITE_MODE register fields. */ | |
179 | #define WMR_SDRAMWRITEEN BIT(0) | |
180 | #define WMR_SDRAMREADEN BIT(1) | |
181 | #define WMR_TRGRES BIT(2) | |
182 | #define WMR_TRGEN BIT(3) | |
183 | #define WMR_FORCESTOP BIT(4) | |
184 | #define WMR_TRGSW BIT(5) | |
185 | /* not used: bit position 6 */ | |
186 | #define WMR_SDRAMINIT BIT(7) | |
187 | ||
188 | /* READ_MODE register fields. */ | |
189 | #define RMR_SDRAMWRITEEN BIT(0) | |
190 | #define RMR_SDRAMREADEN BIT(1) | |
191 | /* not used: bit position 2 */ | |
192 | #define RMR_TRGEN BIT(3) | |
193 | #define RMR_ROUND BIT(4) | |
194 | #define RMR_TRIGGERED BIT(5) | |
195 | #define RMR_POSTTRIGGERED BIT(6) | |
196 | /* not used: bit position 7 */ | |
197 | ||
198 | /* | |
199 | * Trigger options. First and second write are similar, but _some_ | |
200 | * positions change their meaning. | |
201 | */ | |
202 | #define TRGOPT_TRGIEN BIT(7) | |
203 | #define TRGOPT_TRGOEN BIT(6) | |
204 | #define TRGOPT_TRGOINEN BIT(5) /* 1st write */ | |
205 | #define TRGOPT_TRGINEG TRGOPT1_TRGOINEN /* 2nd write */ | |
206 | #define TRGOPT_TRGOEVNTEN BIT(4) /* 1st write */ | |
207 | #define TRGOPT_TRGOPIN TRGOPT1_TRGOEVNTEN /* 2nd write */ | |
208 | #define TRGOPT_TRGOOUTEN BIT(3) /* 1st write */ | |
209 | #define TRGOPT_TRGOLONG TRGOPT1_TRGOOUTEN /* 2nd write */ | |
210 | #define TRGOPT_TRGOUTR_OUT BIT(1) | |
211 | #define TRGOPT_TRGOUTR_EN BIT(0) | |
212 | #define TRGOPT_CLEAR_MASK (TRGOPT_TRGOINEN | TRGOPT_TRGOEVNTEN | TRGOPT_TRGOOUTEN) | |
213 | ||
214 | /* | |
215 | * Layout of the sample data DRAM, which will be downloaded to the PC: | |
216 | * | |
217 | * Sigma memory is organized in 32K rows. Each row contains 64 clusters. | |
218 | * Each cluster contains a timestamp (16bit) and 7 events (16bits each). | |
219 | * Events contain 16 bits of sample data (potentially taken at multiple | |
220 | * sample points, see below). | |
221 | * | |
222 | * Total memory size is 32K x 64 x 8 x 2 bytes == 32 MiB (256 Mbit). The | |
223 | * size of a memory row is 1024 bytes. Assuming x16 organization of the | |
224 | * memory array, address specs (sample count, trigger position) are kept | |
225 | * in 24bit entities. The upper 15 bit address the "row", the lower 9 bit | |
226 | * refer to the "event" within the row. Because there is one timestamp for | |
227 | * seven events each, one memory row can hold up to 64x7 == 448 events. | |
228 | * | |
229 | * Sample data is represented in 16bit quantities. The first sample in | |
230 | * the cluster corresponds to the cluster's timestamp. Each next sample | |
231 | * corresponds to the timestamp + 1, timestamp + 2, etc (the distance is | |
232 | * one sample period, according to the samplerate). In the absence of | |
233 | * pin level changes, no data is provided (RLE compression). A cluster | |
234 | * is enforced for each 64K ticks of the timestamp, to reliably handle | |
235 | * rollover and determine the next timestamp of the next cluster. | |
236 | * | |
237 | * For samplerates up to 50MHz, an event directly translates to one set | |
238 | * of sample data at a single sample point, spanning up to 16 channels. | |
239 | * For samplerates of 100MHz, there is one 16 bit entity for each 20ns | |
240 | * period (50MHz rate). The 16 bit memory contains 2 samples of up to | |
241 | * 8 channels. Bits of multiple samples are interleaved. For samplerates | |
242 | * of 200MHz one 16bit entity contains 4 samples of up to 4 channels, | |
243 | * each 5ns apart. | |
244 | */ | |
245 | ||
246 | #define ROW_COUNT 32768 | |
247 | #define ROW_LENGTH_BYTES 1024 | |
248 | #define ROW_LENGTH_U16 (ROW_LENGTH_BYTES / sizeof(uint16_t)) | |
249 | #define ROW_SHIFT 9 /* log2 of u16 count */ | |
250 | #define ROW_MASK BITS_MASK(ROW_SHIFT) | |
251 | #define EVENTS_PER_CLUSTER 7 | |
252 | #define CLUSTERS_PER_ROW (ROW_LENGTH_U16 / (1 + EVENTS_PER_CLUSTER)) | |
253 | #define EVENTS_PER_ROW (CLUSTERS_PER_ROW * EVENTS_PER_CLUSTER) | |
254 | ||
255 | struct sigma_dram_line { | |
256 | struct sigma_dram_cluster { | |
257 | uint16_t timestamp; | |
258 | uint16_t samples[EVENTS_PER_CLUSTER]; | |
259 | } cluster[CLUSTERS_PER_ROW]; | |
260 | }; | |
261 | ||
262 | /* The effect of all these are still a bit unclear. */ | |
263 | struct triggerinout { | |
264 | gboolean trgout_resistor_enable, trgout_resistor_pullup; | |
265 | gboolean trgout_resistor_enable2, trgout_resistor_pullup2; | |
266 | gboolean trgout_bytrigger, trgout_byevent, trgout_bytriggerin; | |
267 | gboolean trgout_long, trgout_pin; /* 1ms pulse, 1k resistor */ | |
268 | gboolean trgin_negate, trgout_enable, trgin_enable; | |
269 | }; | |
270 | ||
271 | struct triggerlut { | |
272 | uint16_t m0d[4], m1d[4], m2d[4]; | |
273 | uint16_t m3q, m3s, m4; | |
274 | struct { | |
275 | uint8_t selpresc; | |
276 | uint8_t sela, selb, selc; | |
277 | uint8_t selinc, selres; | |
278 | uint16_t cmpa, cmpb; | |
279 | } params; | |
280 | }; | |
281 | ||
282 | /* Trigger configuration */ | |
283 | struct sigma_trigger { | |
284 | /* Only two channels can be used in mask. */ | |
285 | uint16_t risingmask; | |
286 | uint16_t fallingmask; | |
287 | ||
288 | /* Simple trigger support (<= 50 MHz). */ | |
289 | uint16_t simplemask; | |
290 | uint16_t simplevalue; | |
291 | ||
292 | /* TODO: Advanced trigger support (boolean expressions). */ | |
293 | }; | |
294 | ||
295 | /* Events for trigger operation. */ | |
296 | enum triggerop { | |
297 | OP_LEVEL = 1, | |
298 | OP_NOT, | |
299 | OP_RISE, | |
300 | OP_FALL, | |
301 | OP_RISEFALL, | |
302 | OP_NOTRISE, | |
303 | OP_NOTFALL, | |
304 | OP_NOTRISEFALL, | |
305 | }; | |
306 | ||
307 | /* Logical functions for trigger operation. */ | |
308 | enum triggerfunc { | |
309 | FUNC_AND = 1, | |
310 | FUNC_NAND, | |
311 | FUNC_OR, | |
312 | FUNC_NOR, | |
313 | FUNC_XOR, | |
314 | FUNC_NXOR, | |
315 | }; | |
316 | ||
317 | enum sigma_firmware_idx { | |
318 | SIGMA_FW_NONE, | |
319 | SIGMA_FW_50MHZ, | |
320 | SIGMA_FW_100MHZ, | |
321 | SIGMA_FW_200MHZ, | |
322 | SIGMA_FW_SYNC, | |
323 | SIGMA_FW_FREQ, | |
324 | }; | |
325 | ||
326 | enum ext_clock_edge_t { | |
327 | SIGMA_CLOCK_EDGE_RISING, | |
328 | SIGMA_CLOCK_EDGE_FALLING, | |
329 | SIGMA_CLOCK_EDGE_EITHER, | |
330 | }; | |
331 | ||
332 | struct submit_buffer; | |
333 | ||
334 | struct dev_context { | |
335 | struct { | |
336 | uint16_t vid, pid; | |
337 | uint32_t serno; | |
338 | uint16_t prefix; | |
339 | enum asix_device_type type; | |
340 | } id; | |
341 | struct { | |
342 | struct ftdi_context ctx; | |
343 | gboolean is_open, must_close; | |
344 | } ftdi; | |
345 | struct { | |
346 | uint64_t samplerate; | |
347 | gboolean use_ext_clock; | |
348 | size_t clock_pin; | |
349 | enum ext_clock_edge_t clock_edge; | |
350 | } clock; | |
351 | struct { | |
352 | /* | |
353 | * User specified configuration values, in contrast to | |
354 | * internal arrangement of acquisition, and submission | |
355 | * to the session feed. | |
356 | */ | |
357 | struct sr_sw_limits config; | |
358 | struct sr_sw_limits acquire; | |
359 | struct sr_sw_limits submit; | |
360 | } limit; | |
361 | enum sigma_firmware_idx firmware_idx; | |
362 | struct sigma_sample_interp { | |
363 | /* Interpretation of sample memory. */ | |
364 | size_t num_channels; | |
365 | size_t samples_per_event; | |
366 | struct { | |
367 | uint16_t ts; | |
368 | uint16_t sample; | |
369 | } last; | |
370 | struct sigma_location { | |
371 | size_t raw, line, cluster, event; | |
372 | } start, stop, trig, iter, trig_arm; | |
373 | struct { | |
374 | size_t lines_total, lines_done; | |
375 | size_t lines_per_read; /* USB transfer limit */ | |
376 | size_t lines_rcvd; | |
377 | struct sigma_dram_line *rcvd_lines; | |
378 | struct sigma_dram_line *curr_line; | |
379 | } fetch; | |
380 | struct { | |
381 | gboolean armed; | |
382 | gboolean matched; | |
383 | size_t evt_remain; | |
384 | } trig_chk; | |
385 | } interp; | |
386 | uint64_t capture_ratio; | |
387 | struct sigma_trigger trigger; | |
388 | gboolean use_triggers; | |
389 | enum { | |
390 | SIGMA_UNINITIALIZED = 0, | |
391 | SIGMA_CONFIG, | |
392 | SIGMA_IDLE, | |
393 | SIGMA_CAPTURE, | |
394 | SIGMA_STOPPING, | |
395 | SIGMA_DOWNLOAD, | |
396 | } state; | |
397 | struct submit_buffer *buffer; | |
398 | }; | |
399 | ||
400 | /* "Automatic" and forced USB connection open/close support. */ | |
401 | SR_PRIV int sigma_check_open(const struct sr_dev_inst *sdi); | |
402 | SR_PRIV int sigma_check_close(struct dev_context *devc); | |
403 | SR_PRIV int sigma_force_open(const struct sr_dev_inst *sdi); | |
404 | SR_PRIV int sigma_force_close(struct dev_context *devc); | |
405 | ||
406 | /* Save configuration across sessions, to reduce cost of continuation. */ | |
407 | SR_PRIV int sigma_store_hw_config(const struct sr_dev_inst *sdi); | |
408 | SR_PRIV int sigma_fetch_hw_config(const struct sr_dev_inst *sdi); | |
409 | ||
410 | /* Send register content (simple and complex) to the hardware. */ | |
411 | SR_PRIV int sigma_write_register(struct dev_context *devc, | |
412 | uint8_t reg, uint8_t *data, size_t len); | |
413 | SR_PRIV int sigma_set_register(struct dev_context *devc, | |
414 | uint8_t reg, uint8_t value); | |
415 | SR_PRIV int sigma_write_trigger_lut(struct dev_context *devc, | |
416 | struct triggerlut *lut); | |
417 | ||
418 | /* Samplerate constraints check, get/set/list helpers. */ | |
419 | SR_PRIV int sigma_normalize_samplerate(uint64_t want_rate, uint64_t *have_rate); | |
420 | SR_PRIV GVariant *sigma_get_samplerates_list(void); | |
421 | ||
422 | /* Preparation of data acquisition, spec conversion, hardware configuration. */ | |
423 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi); | |
424 | SR_PRIV int sigma_set_acquire_timeout(struct dev_context *devc); | |
425 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi); | |
426 | SR_PRIV int sigma_build_basic_trigger(struct dev_context *devc, | |
427 | struct triggerlut *lut); | |
428 | ||
429 | /* Callback to periodically drive acuisition progress. */ | |
430 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data); | |
431 | ||
432 | #endif |