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1 | /* | |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | /* | |
23 | * ASIX SIGMA/SIGMA2 logic analyzer driver | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include "protocol.h" | |
28 | ||
29 | #define USB_VENDOR 0xa600 | |
30 | #define USB_PRODUCT 0xa000 | |
31 | #define USB_DESCRIPTION "ASIX SIGMA" | |
32 | #define USB_VENDOR_NAME "ASIX" | |
33 | #define USB_MODEL_NAME "SIGMA" | |
34 | ||
35 | SR_PRIV struct sr_dev_driver asix_sigma_driver_info; | |
36 | ||
37 | /* | |
38 | * The ASIX Sigma supports arbitrary integer frequency divider in | |
39 | * the 50MHz mode. The divider is in range 1...256 , allowing for | |
40 | * very precise sampling rate selection. This driver supports only | |
41 | * a subset of the sampling rates. | |
42 | */ | |
43 | SR_PRIV const uint64_t samplerates[] = { | |
44 | SR_KHZ(200), /* div=250 */ | |
45 | SR_KHZ(250), /* div=200 */ | |
46 | SR_KHZ(500), /* div=100 */ | |
47 | SR_MHZ(1), /* div=50 */ | |
48 | SR_MHZ(5), /* div=10 */ | |
49 | SR_MHZ(10), /* div=5 */ | |
50 | SR_MHZ(25), /* div=2 */ | |
51 | SR_MHZ(50), /* div=1 */ | |
52 | SR_MHZ(100), /* Special FW needed */ | |
53 | SR_MHZ(200), /* Special FW needed */ | |
54 | }; | |
55 | ||
56 | SR_PRIV const int SAMPLERATES_COUNT = ARRAY_SIZE(samplerates); | |
57 | ||
58 | static const char sigma_firmware_files[][24] = { | |
59 | /* 50 MHz, supports 8 bit fractions */ | |
60 | "asix-sigma-50.fw", | |
61 | /* 100 MHz */ | |
62 | "asix-sigma-100.fw", | |
63 | /* 200 MHz */ | |
64 | "asix-sigma-200.fw", | |
65 | /* Synchronous clock from pin */ | |
66 | "asix-sigma-50sync.fw", | |
67 | /* Frequency counter */ | |
68 | "asix-sigma-phasor.fw", | |
69 | }; | |
70 | ||
71 | static int sigma_read(void *buf, size_t size, struct dev_context *devc) | |
72 | { | |
73 | int ret; | |
74 | ||
75 | ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size); | |
76 | if (ret < 0) { | |
77 | sr_err("ftdi_read_data failed: %s", | |
78 | ftdi_get_error_string(&devc->ftdic)); | |
79 | } | |
80 | ||
81 | return ret; | |
82 | } | |
83 | ||
84 | static int sigma_write(void *buf, size_t size, struct dev_context *devc) | |
85 | { | |
86 | int ret; | |
87 | ||
88 | ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size); | |
89 | if (ret < 0) { | |
90 | sr_err("ftdi_write_data failed: %s", | |
91 | ftdi_get_error_string(&devc->ftdic)); | |
92 | } else if ((size_t) ret != size) { | |
93 | sr_err("ftdi_write_data did not complete write."); | |
94 | } | |
95 | ||
96 | return ret; | |
97 | } | |
98 | ||
99 | /* | |
100 | * NOTE: We chose the buffer size to be large enough to hold any write to the | |
101 | * device. We still print a message just in case. | |
102 | */ | |
103 | SR_PRIV int sigma_write_register(uint8_t reg, uint8_t *data, size_t len, | |
104 | struct dev_context *devc) | |
105 | { | |
106 | size_t i; | |
107 | uint8_t buf[80]; | |
108 | int idx = 0; | |
109 | ||
110 | if ((len + 2) > sizeof(buf)) { | |
111 | sr_err("Attempted to write %zu bytes, but buffer is too small.", | |
112 | len + 2); | |
113 | return SR_ERR_BUG; | |
114 | } | |
115 | ||
116 | buf[idx++] = REG_ADDR_LOW | (reg & 0xf); | |
117 | buf[idx++] = REG_ADDR_HIGH | (reg >> 4); | |
118 | ||
119 | for (i = 0; i < len; ++i) { | |
120 | buf[idx++] = REG_DATA_LOW | (data[i] & 0xf); | |
121 | buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4); | |
122 | } | |
123 | ||
124 | return sigma_write(buf, idx, devc); | |
125 | } | |
126 | ||
127 | SR_PRIV int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc) | |
128 | { | |
129 | return sigma_write_register(reg, &value, 1, devc); | |
130 | } | |
131 | ||
132 | static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len, | |
133 | struct dev_context *devc) | |
134 | { | |
135 | uint8_t buf[3]; | |
136 | ||
137 | buf[0] = REG_ADDR_LOW | (reg & 0xf); | |
138 | buf[1] = REG_ADDR_HIGH | (reg >> 4); | |
139 | buf[2] = REG_READ_ADDR; | |
140 | ||
141 | sigma_write(buf, sizeof(buf), devc); | |
142 | ||
143 | return sigma_read(data, len, devc); | |
144 | } | |
145 | ||
146 | static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc) | |
147 | { | |
148 | uint8_t value; | |
149 | ||
150 | if (1 != sigma_read_register(reg, &value, 1, devc)) { | |
151 | sr_err("sigma_get_register: 1 byte expected"); | |
152 | return 0; | |
153 | } | |
154 | ||
155 | return value; | |
156 | } | |
157 | ||
158 | static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos, | |
159 | struct dev_context *devc) | |
160 | { | |
161 | uint8_t buf[] = { | |
162 | REG_ADDR_LOW | READ_TRIGGER_POS_LOW, | |
163 | ||
164 | REG_READ_ADDR | NEXT_REG, | |
165 | REG_READ_ADDR | NEXT_REG, | |
166 | REG_READ_ADDR | NEXT_REG, | |
167 | REG_READ_ADDR | NEXT_REG, | |
168 | REG_READ_ADDR | NEXT_REG, | |
169 | REG_READ_ADDR | NEXT_REG, | |
170 | }; | |
171 | uint8_t result[6]; | |
172 | ||
173 | sigma_write(buf, sizeof(buf), devc); | |
174 | ||
175 | sigma_read(result, sizeof(result), devc); | |
176 | ||
177 | *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16); | |
178 | *stoppos = result[3] | (result[4] << 8) | (result[5] << 16); | |
179 | ||
180 | /* Not really sure why this must be done, but according to spec. */ | |
181 | if ((--*stoppos & 0x1ff) == 0x1ff) | |
182 | *stoppos -= 64; | |
183 | ||
184 | if ((*--triggerpos & 0x1ff) == 0x1ff) | |
185 | *triggerpos -= 64; | |
186 | ||
187 | return 1; | |
188 | } | |
189 | ||
190 | static int sigma_read_dram(uint16_t startchunk, size_t numchunks, | |
191 | uint8_t *data, struct dev_context *devc) | |
192 | { | |
193 | size_t i; | |
194 | uint8_t buf[4096]; | |
195 | int idx = 0; | |
196 | ||
197 | /* Send the startchunk. Index start with 1. */ | |
198 | buf[0] = startchunk >> 8; | |
199 | buf[1] = startchunk & 0xff; | |
200 | sigma_write_register(WRITE_MEMROW, buf, 2, devc); | |
201 | ||
202 | /* Read the DRAM. */ | |
203 | buf[idx++] = REG_DRAM_BLOCK; | |
204 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
205 | ||
206 | for (i = 0; i < numchunks; ++i) { | |
207 | /* Alternate bit to copy from DRAM to cache. */ | |
208 | if (i != (numchunks - 1)) | |
209 | buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4); | |
210 | ||
211 | buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4); | |
212 | ||
213 | if (i != (numchunks - 1)) | |
214 | buf[idx++] = REG_DRAM_WAIT_ACK; | |
215 | } | |
216 | ||
217 | sigma_write(buf, idx, devc); | |
218 | ||
219 | return sigma_read(data, numchunks * CHUNK_SIZE, devc); | |
220 | } | |
221 | ||
222 | /* Upload trigger look-up tables to Sigma. */ | |
223 | SR_PRIV int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc) | |
224 | { | |
225 | int i; | |
226 | uint8_t tmp[2]; | |
227 | uint16_t bit; | |
228 | ||
229 | /* Transpose the table and send to Sigma. */ | |
230 | for (i = 0; i < 16; ++i) { | |
231 | bit = 1 << i; | |
232 | ||
233 | tmp[0] = tmp[1] = 0; | |
234 | ||
235 | if (lut->m2d[0] & bit) | |
236 | tmp[0] |= 0x01; | |
237 | if (lut->m2d[1] & bit) | |
238 | tmp[0] |= 0x02; | |
239 | if (lut->m2d[2] & bit) | |
240 | tmp[0] |= 0x04; | |
241 | if (lut->m2d[3] & bit) | |
242 | tmp[0] |= 0x08; | |
243 | ||
244 | if (lut->m3 & bit) | |
245 | tmp[0] |= 0x10; | |
246 | if (lut->m3s & bit) | |
247 | tmp[0] |= 0x20; | |
248 | if (lut->m4 & bit) | |
249 | tmp[0] |= 0x40; | |
250 | ||
251 | if (lut->m0d[0] & bit) | |
252 | tmp[1] |= 0x01; | |
253 | if (lut->m0d[1] & bit) | |
254 | tmp[1] |= 0x02; | |
255 | if (lut->m0d[2] & bit) | |
256 | tmp[1] |= 0x04; | |
257 | if (lut->m0d[3] & bit) | |
258 | tmp[1] |= 0x08; | |
259 | ||
260 | if (lut->m1d[0] & bit) | |
261 | tmp[1] |= 0x10; | |
262 | if (lut->m1d[1] & bit) | |
263 | tmp[1] |= 0x20; | |
264 | if (lut->m1d[2] & bit) | |
265 | tmp[1] |= 0x40; | |
266 | if (lut->m1d[3] & bit) | |
267 | tmp[1] |= 0x80; | |
268 | ||
269 | sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp), | |
270 | devc); | |
271 | sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc); | |
272 | } | |
273 | ||
274 | /* Send the parameters */ | |
275 | sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params, | |
276 | sizeof(lut->params), devc); | |
277 | ||
278 | return SR_OK; | |
279 | } | |
280 | ||
281 | SR_PRIV void sigma_clear_helper(void *priv) | |
282 | { | |
283 | struct dev_context *devc; | |
284 | ||
285 | devc = priv; | |
286 | ||
287 | ftdi_deinit(&devc->ftdic); | |
288 | } | |
289 | ||
290 | /* | |
291 | * Configure the FPGA for bitbang mode. | |
292 | * This sequence is documented in section 2. of the ASIX Sigma programming | |
293 | * manual. This sequence is necessary to configure the FPGA in the Sigma | |
294 | * into Bitbang mode, in which it can be programmed with the firmware. | |
295 | */ | |
296 | static int sigma_fpga_init_bitbang(struct dev_context *devc) | |
297 | { | |
298 | uint8_t suicide[] = { | |
299 | 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84, | |
300 | }; | |
301 | uint8_t init_array[] = { | |
302 | 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, | |
303 | 0x01, 0x01, | |
304 | }; | |
305 | int i, ret, timeout = (10 * 1000); | |
306 | uint8_t data; | |
307 | ||
308 | /* Section 2. part 1), do the FPGA suicide. */ | |
309 | sigma_write(suicide, sizeof(suicide), devc); | |
310 | sigma_write(suicide, sizeof(suicide), devc); | |
311 | sigma_write(suicide, sizeof(suicide), devc); | |
312 | sigma_write(suicide, sizeof(suicide), devc); | |
313 | ||
314 | /* Section 2. part 2), do pulse on D1. */ | |
315 | sigma_write(init_array, sizeof(init_array), devc); | |
316 | ftdi_usb_purge_buffers(&devc->ftdic); | |
317 | ||
318 | /* Wait until the FPGA asserts D6/INIT_B. */ | |
319 | for (i = 0; i < timeout; i++) { | |
320 | ret = sigma_read(&data, 1, devc); | |
321 | if (ret < 0) | |
322 | return ret; | |
323 | /* Test if pin D6 got asserted. */ | |
324 | if (data & (1 << 5)) | |
325 | return 0; | |
326 | /* The D6 was not asserted yet, wait a bit. */ | |
327 | g_usleep(10 * 1000); | |
328 | } | |
329 | ||
330 | return SR_ERR_TIMEOUT; | |
331 | } | |
332 | ||
333 | /* | |
334 | * Configure the FPGA for logic-analyzer mode. | |
335 | */ | |
336 | static int sigma_fpga_init_la(struct dev_context *devc) | |
337 | { | |
338 | /* Initialize the logic analyzer mode. */ | |
339 | uint8_t logic_mode_start[] = { | |
340 | REG_ADDR_LOW | (READ_ID & 0xf), | |
341 | REG_ADDR_HIGH | (READ_ID >> 8), | |
342 | REG_READ_ADDR, /* Read ID register. */ | |
343 | ||
344 | REG_ADDR_LOW | (WRITE_TEST & 0xf), | |
345 | REG_DATA_LOW | 0x5, | |
346 | REG_DATA_HIGH_WRITE | 0x5, | |
347 | REG_READ_ADDR, /* Read scratch register. */ | |
348 | ||
349 | REG_DATA_LOW | 0xa, | |
350 | REG_DATA_HIGH_WRITE | 0xa, | |
351 | REG_READ_ADDR, /* Read scratch register. */ | |
352 | ||
353 | REG_ADDR_LOW | (WRITE_MODE & 0xf), | |
354 | REG_DATA_LOW | 0x0, | |
355 | REG_DATA_HIGH_WRITE | 0x8, | |
356 | }; | |
357 | ||
358 | uint8_t result[3]; | |
359 | int ret; | |
360 | ||
361 | /* Initialize the logic analyzer mode. */ | |
362 | sigma_write(logic_mode_start, sizeof(logic_mode_start), devc); | |
363 | ||
364 | /* Expect a 3 byte reply since we issued three READ requests. */ | |
365 | ret = sigma_read(result, 3, devc); | |
366 | if (ret != 3) | |
367 | goto err; | |
368 | ||
369 | if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) | |
370 | goto err; | |
371 | ||
372 | return SR_OK; | |
373 | err: | |
374 | sr_err("Configuration failed. Invalid reply received."); | |
375 | return SR_ERR; | |
376 | } | |
377 | ||
378 | /* | |
379 | * Read the firmware from a file and transform it into a series of bitbang | |
380 | * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d | |
381 | * by the caller of this function. | |
382 | */ | |
383 | static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name, | |
384 | uint8_t **bb_cmd, gsize *bb_cmd_size) | |
385 | { | |
386 | size_t i, file_size, bb_size; | |
387 | char *firmware; | |
388 | uint8_t *bb_stream, *bbs; | |
389 | uint32_t imm; | |
390 | int bit, v; | |
391 | int ret = SR_OK; | |
392 | ||
393 | firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, | |
394 | name, &file_size, 256 * 1024); | |
395 | if (!firmware) | |
396 | return SR_ERR; | |
397 | ||
398 | /* Weird magic transformation below, I have no idea what it does. */ | |
399 | imm = 0x3f6df2ab; | |
400 | for (i = 0; i < file_size; i++) { | |
401 | imm = (imm + 0xa853753) % 177 + (imm * 0x8034052); | |
402 | firmware[i] ^= imm & 0xff; | |
403 | } | |
404 | ||
405 | /* | |
406 | * Now that the firmware is "transformed", we will transcribe the | |
407 | * firmware blob into a sequence of toggles of the Dx wires. This | |
408 | * sequence will be fed directly into the Sigma, which must be in | |
409 | * the FPGA bitbang programming mode. | |
410 | */ | |
411 | ||
412 | /* Each bit of firmware is transcribed as two toggles of Dx wires. */ | |
413 | bb_size = file_size * 8 * 2; | |
414 | bb_stream = (uint8_t *)g_try_malloc(bb_size); | |
415 | if (!bb_stream) { | |
416 | sr_err("%s: Failed to allocate bitbang stream", __func__); | |
417 | ret = SR_ERR_MALLOC; | |
418 | goto exit; | |
419 | } | |
420 | ||
421 | bbs = bb_stream; | |
422 | for (i = 0; i < file_size; i++) { | |
423 | for (bit = 7; bit >= 0; bit--) { | |
424 | v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00; | |
425 | *bbs++ = v | 0x01; | |
426 | *bbs++ = v; | |
427 | } | |
428 | } | |
429 | ||
430 | /* The transformation completed successfully, return the result. */ | |
431 | *bb_cmd = bb_stream; | |
432 | *bb_cmd_size = bb_size; | |
433 | ||
434 | exit: | |
435 | g_free(firmware); | |
436 | return ret; | |
437 | } | |
438 | ||
439 | static int upload_firmware(struct sr_context *ctx, | |
440 | int firmware_idx, struct dev_context *devc) | |
441 | { | |
442 | int ret; | |
443 | unsigned char *buf; | |
444 | unsigned char pins; | |
445 | size_t buf_size; | |
446 | const char *firmware = sigma_firmware_files[firmware_idx]; | |
447 | struct ftdi_context *ftdic = &devc->ftdic; | |
448 | ||
449 | /* Make sure it's an ASIX SIGMA. */ | |
450 | ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT, | |
451 | USB_DESCRIPTION, NULL); | |
452 | if (ret < 0) { | |
453 | sr_err("ftdi_usb_open failed: %s", | |
454 | ftdi_get_error_string(ftdic)); | |
455 | return 0; | |
456 | } | |
457 | ||
458 | ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG); | |
459 | if (ret < 0) { | |
460 | sr_err("ftdi_set_bitmode failed: %s", | |
461 | ftdi_get_error_string(ftdic)); | |
462 | return 0; | |
463 | } | |
464 | ||
465 | /* Four times the speed of sigmalogan - Works well. */ | |
466 | ret = ftdi_set_baudrate(ftdic, 750 * 1000); | |
467 | if (ret < 0) { | |
468 | sr_err("ftdi_set_baudrate failed: %s", | |
469 | ftdi_get_error_string(ftdic)); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | /* Initialize the FPGA for firmware upload. */ | |
474 | ret = sigma_fpga_init_bitbang(devc); | |
475 | if (ret) | |
476 | return ret; | |
477 | ||
478 | /* Prepare firmware. */ | |
479 | ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size); | |
480 | if (ret != SR_OK) { | |
481 | sr_err("An error occurred while reading the firmware: %s", | |
482 | firmware); | |
483 | return ret; | |
484 | } | |
485 | ||
486 | /* Upload firmware. */ | |
487 | sr_info("Uploading firmware file '%s'.", firmware); | |
488 | sigma_write(buf, buf_size, devc); | |
489 | ||
490 | g_free(buf); | |
491 | ||
492 | ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET); | |
493 | if (ret < 0) { | |
494 | sr_err("ftdi_set_bitmode failed: %s", | |
495 | ftdi_get_error_string(ftdic)); | |
496 | return SR_ERR; | |
497 | } | |
498 | ||
499 | ftdi_usb_purge_buffers(ftdic); | |
500 | ||
501 | /* Discard garbage. */ | |
502 | while (sigma_read(&pins, 1, devc) == 1) | |
503 | ; | |
504 | ||
505 | /* Initialize the FPGA for logic-analyzer mode. */ | |
506 | ret = sigma_fpga_init_la(devc); | |
507 | if (ret != SR_OK) | |
508 | return ret; | |
509 | ||
510 | devc->cur_firmware = firmware_idx; | |
511 | ||
512 | sr_info("Firmware uploaded."); | |
513 | ||
514 | return SR_OK; | |
515 | } | |
516 | ||
517 | SR_PRIV int sigma_set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate) | |
518 | { | |
519 | struct dev_context *devc; | |
520 | struct drv_context *drvc; | |
521 | unsigned int i; | |
522 | int ret; | |
523 | ||
524 | devc = sdi->priv; | |
525 | drvc = sdi->driver->context; | |
526 | ret = SR_OK; | |
527 | ||
528 | for (i = 0; i < ARRAY_SIZE(samplerates); i++) { | |
529 | if (samplerates[i] == samplerate) | |
530 | break; | |
531 | } | |
532 | if (samplerates[i] == 0) | |
533 | return SR_ERR_SAMPLERATE; | |
534 | ||
535 | if (samplerate <= SR_MHZ(50)) { | |
536 | ret = upload_firmware(drvc->sr_ctx, 0, devc); | |
537 | devc->num_channels = 16; | |
538 | } else if (samplerate == SR_MHZ(100)) { | |
539 | ret = upload_firmware(drvc->sr_ctx, 1, devc); | |
540 | devc->num_channels = 8; | |
541 | } else if (samplerate == SR_MHZ(200)) { | |
542 | ret = upload_firmware(drvc->sr_ctx, 2, devc); | |
543 | devc->num_channels = 4; | |
544 | } | |
545 | ||
546 | if (ret == SR_OK) { | |
547 | devc->cur_samplerate = samplerate; | |
548 | devc->period_ps = 1000000000000ULL / samplerate; | |
549 | devc->samples_per_event = 16 / devc->num_channels; | |
550 | devc->state.state = SIGMA_IDLE; | |
551 | } | |
552 | ||
553 | return ret; | |
554 | } | |
555 | ||
556 | /* | |
557 | * In 100 and 200 MHz mode, only a single pin rising/falling can be | |
558 | * set as trigger. In other modes, two rising/falling triggers can be set, | |
559 | * in addition to value/mask trigger for any number of channels. | |
560 | * | |
561 | * The Sigma supports complex triggers using boolean expressions, but this | |
562 | * has not been implemented yet. | |
563 | */ | |
564 | SR_PRIV int sigma_convert_trigger(const struct sr_dev_inst *sdi) | |
565 | { | |
566 | struct dev_context *devc; | |
567 | struct sr_trigger *trigger; | |
568 | struct sr_trigger_stage *stage; | |
569 | struct sr_trigger_match *match; | |
570 | const GSList *l, *m; | |
571 | int channelbit, trigger_set; | |
572 | ||
573 | devc = sdi->priv; | |
574 | memset(&devc->trigger, 0, sizeof(struct sigma_trigger)); | |
575 | if (!(trigger = sr_session_trigger_get(sdi->session))) | |
576 | return SR_OK; | |
577 | ||
578 | trigger_set = 0; | |
579 | for (l = trigger->stages; l; l = l->next) { | |
580 | stage = l->data; | |
581 | for (m = stage->matches; m; m = m->next) { | |
582 | match = m->data; | |
583 | if (!match->channel->enabled) | |
584 | /* Ignore disabled channels with a trigger. */ | |
585 | continue; | |
586 | channelbit = 1 << (match->channel->index); | |
587 | if (devc->cur_samplerate >= SR_MHZ(100)) { | |
588 | /* Fast trigger support. */ | |
589 | if (trigger_set) { | |
590 | sr_err("Only a single pin trigger is " | |
591 | "supported in 100 and 200MHz mode."); | |
592 | return SR_ERR; | |
593 | } | |
594 | if (match->match == SR_TRIGGER_FALLING) | |
595 | devc->trigger.fallingmask |= channelbit; | |
596 | else if (match->match == SR_TRIGGER_RISING) | |
597 | devc->trigger.risingmask |= channelbit; | |
598 | else { | |
599 | sr_err("Only rising/falling trigger is " | |
600 | "supported in 100 and 200MHz mode."); | |
601 | return SR_ERR; | |
602 | } | |
603 | ||
604 | ++trigger_set; | |
605 | } else { | |
606 | /* Simple trigger support (event). */ | |
607 | if (match->match == SR_TRIGGER_ONE) { | |
608 | devc->trigger.simplevalue |= channelbit; | |
609 | devc->trigger.simplemask |= channelbit; | |
610 | } | |
611 | else if (match->match == SR_TRIGGER_ZERO) { | |
612 | devc->trigger.simplevalue &= ~channelbit; | |
613 | devc->trigger.simplemask |= channelbit; | |
614 | } | |
615 | else if (match->match == SR_TRIGGER_FALLING) { | |
616 | devc->trigger.fallingmask |= channelbit; | |
617 | ++trigger_set; | |
618 | } | |
619 | else if (match->match == SR_TRIGGER_RISING) { | |
620 | devc->trigger.risingmask |= channelbit; | |
621 | ++trigger_set; | |
622 | } | |
623 | ||
624 | /* | |
625 | * Actually, Sigma supports 2 rising/falling triggers, | |
626 | * but they are ORed and the current trigger syntax | |
627 | * does not permit ORed triggers. | |
628 | */ | |
629 | if (trigger_set > 1) { | |
630 | sr_err("Only 1 rising/falling trigger " | |
631 | "is supported."); | |
632 | return SR_ERR; | |
633 | } | |
634 | } | |
635 | } | |
636 | } | |
637 | ||
638 | return SR_OK; | |
639 | } | |
640 | ||
641 | ||
642 | /* Software trigger to determine exact trigger position. */ | |
643 | static int get_trigger_offset(uint8_t *samples, uint16_t last_sample, | |
644 | struct sigma_trigger *t) | |
645 | { | |
646 | int i; | |
647 | uint16_t sample = 0; | |
648 | ||
649 | for (i = 0; i < 8; ++i) { | |
650 | if (i > 0) | |
651 | last_sample = sample; | |
652 | sample = samples[2 * i] | (samples[2 * i + 1] << 8); | |
653 | ||
654 | /* Simple triggers. */ | |
655 | if ((sample & t->simplemask) != t->simplevalue) | |
656 | continue; | |
657 | ||
658 | /* Rising edge. */ | |
659 | if (((last_sample & t->risingmask) != 0) || | |
660 | ((sample & t->risingmask) != t->risingmask)) | |
661 | continue; | |
662 | ||
663 | /* Falling edge. */ | |
664 | if ((last_sample & t->fallingmask) != t->fallingmask || | |
665 | (sample & t->fallingmask) != 0) | |
666 | continue; | |
667 | ||
668 | break; | |
669 | } | |
670 | ||
671 | /* If we did not match, return original trigger pos. */ | |
672 | return i & 0x7; | |
673 | } | |
674 | ||
675 | /* | |
676 | * Return the timestamp of "DRAM cluster". | |
677 | */ | |
678 | static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster) | |
679 | { | |
680 | return (cluster->timestamp_hi << 8) | cluster->timestamp_lo; | |
681 | } | |
682 | ||
683 | static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster, | |
684 | unsigned int events_in_cluster, | |
685 | unsigned int triggered, | |
686 | struct sr_dev_inst *sdi) | |
687 | { | |
688 | struct dev_context *devc = sdi->priv; | |
689 | struct sigma_state *ss = &devc->state; | |
690 | struct sr_datafeed_packet packet; | |
691 | struct sr_datafeed_logic logic; | |
692 | uint16_t tsdiff, ts; | |
693 | uint8_t samples[2048]; | |
694 | unsigned int i; | |
695 | ||
696 | ts = sigma_dram_cluster_ts(dram_cluster); | |
697 | tsdiff = ts - ss->lastts; | |
698 | ss->lastts = ts; | |
699 | ||
700 | packet.type = SR_DF_LOGIC; | |
701 | packet.payload = &logic; | |
702 | logic.unitsize = 2; | |
703 | logic.data = samples; | |
704 | ||
705 | /* | |
706 | * First of all, send Sigrok a copy of the last sample from | |
707 | * previous cluster as many times as needed to make up for | |
708 | * the differential characteristics of data we get from the | |
709 | * Sigma. Sigrok needs one sample of data per period. | |
710 | * | |
711 | * One DRAM cluster contains a timestamp and seven samples, | |
712 | * the units of timestamp are "devc->period_ps" , the first | |
713 | * sample in the cluster happens at the time of the timestamp | |
714 | * and the remaining samples happen at timestamp +1...+6 . | |
715 | */ | |
716 | for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) { | |
717 | i = ts % 1024; | |
718 | samples[2 * i + 0] = ss->lastsample & 0xff; | |
719 | samples[2 * i + 1] = ss->lastsample >> 8; | |
720 | ||
721 | /* | |
722 | * If we have 1024 samples ready or we're at the | |
723 | * end of submitting the padding samples, submit | |
724 | * the packet to Sigrok. | |
725 | */ | |
726 | if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) { | |
727 | logic.length = (i + 1) * logic.unitsize; | |
728 | sr_session_send(sdi, &packet); | |
729 | } | |
730 | } | |
731 | ||
732 | /* | |
733 | * Parse the samples in current cluster and prepare them | |
734 | * to be submitted to Sigrok. | |
735 | */ | |
736 | for (i = 0; i < events_in_cluster; i++) { | |
737 | samples[2 * i + 1] = dram_cluster->samples[i].sample_lo; | |
738 | samples[2 * i + 0] = dram_cluster->samples[i].sample_hi; | |
739 | } | |
740 | ||
741 | /* Send data up to trigger point (if triggered). */ | |
742 | int trigger_offset = 0; | |
743 | if (triggered) { | |
744 | /* | |
745 | * Trigger is not always accurate to sample because of | |
746 | * pipeline delay. However, it always triggers before | |
747 | * the actual event. We therefore look at the next | |
748 | * samples to pinpoint the exact position of the trigger. | |
749 | */ | |
750 | trigger_offset = get_trigger_offset(samples, | |
751 | ss->lastsample, &devc->trigger); | |
752 | ||
753 | if (trigger_offset > 0) { | |
754 | packet.type = SR_DF_LOGIC; | |
755 | logic.length = trigger_offset * logic.unitsize; | |
756 | sr_session_send(sdi, &packet); | |
757 | events_in_cluster -= trigger_offset; | |
758 | } | |
759 | ||
760 | /* Only send trigger if explicitly enabled. */ | |
761 | if (devc->use_triggers) { | |
762 | packet.type = SR_DF_TRIGGER; | |
763 | sr_session_send(sdi, &packet); | |
764 | } | |
765 | } | |
766 | ||
767 | if (events_in_cluster > 0) { | |
768 | packet.type = SR_DF_LOGIC; | |
769 | logic.length = events_in_cluster * logic.unitsize; | |
770 | logic.data = samples + (trigger_offset * logic.unitsize); | |
771 | sr_session_send(sdi, &packet); | |
772 | } | |
773 | ||
774 | ss->lastsample = | |
775 | samples[2 * (events_in_cluster - 1) + 0] | | |
776 | (samples[2 * (events_in_cluster - 1) + 1] << 8); | |
777 | ||
778 | } | |
779 | ||
780 | /* | |
781 | * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster. | |
782 | * Each event is 20ns apart, and can contain multiple samples. | |
783 | * | |
784 | * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart. | |
785 | * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart. | |
786 | * For 50 MHz and below, events contain one sample for each channel, | |
787 | * spread 20 ns apart. | |
788 | */ | |
789 | static int decode_chunk_ts(struct sigma_dram_line *dram_line, | |
790 | uint16_t events_in_line, | |
791 | uint32_t trigger_event, | |
792 | struct sr_dev_inst *sdi) | |
793 | { | |
794 | struct sigma_dram_cluster *dram_cluster; | |
795 | struct dev_context *devc = sdi->priv; | |
796 | unsigned int clusters_in_line = | |
797 | (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER; | |
798 | unsigned int events_in_cluster; | |
799 | unsigned int i; | |
800 | uint32_t trigger_cluster = ~0, triggered = 0; | |
801 | ||
802 | /* Check if trigger is in this chunk. */ | |
803 | if (trigger_event < (64 * 7)) { | |
804 | if (devc->cur_samplerate <= SR_MHZ(50)) { | |
805 | trigger_event -= MIN(EVENTS_PER_CLUSTER - 1, | |
806 | trigger_event); | |
807 | } | |
808 | ||
809 | /* Find in which cluster the trigger occurred. */ | |
810 | trigger_cluster = trigger_event / EVENTS_PER_CLUSTER; | |
811 | } | |
812 | ||
813 | /* For each full DRAM cluster. */ | |
814 | for (i = 0; i < clusters_in_line; i++) { | |
815 | dram_cluster = &dram_line->cluster[i]; | |
816 | ||
817 | /* The last cluster might not be full. */ | |
818 | if ((i == clusters_in_line - 1) && | |
819 | (events_in_line % EVENTS_PER_CLUSTER)) { | |
820 | events_in_cluster = events_in_line % EVENTS_PER_CLUSTER; | |
821 | } else { | |
822 | events_in_cluster = EVENTS_PER_CLUSTER; | |
823 | } | |
824 | ||
825 | triggered = (i == trigger_cluster); | |
826 | sigma_decode_dram_cluster(dram_cluster, events_in_cluster, | |
827 | triggered, sdi); | |
828 | } | |
829 | ||
830 | return SR_OK; | |
831 | } | |
832 | ||
833 | static int download_capture(struct sr_dev_inst *sdi) | |
834 | { | |
835 | struct dev_context *devc = sdi->priv; | |
836 | const uint32_t chunks_per_read = 32; | |
837 | struct sigma_dram_line *dram_line; | |
838 | int bufsz; | |
839 | uint32_t stoppos, triggerpos; | |
840 | struct sr_datafeed_packet packet; | |
841 | uint8_t modestatus; | |
842 | ||
843 | uint32_t i; | |
844 | uint32_t dl_lines_total, dl_lines_curr, dl_lines_done; | |
845 | uint32_t dl_events_in_line = 64 * 7; | |
846 | uint32_t trg_line = ~0, trg_event = ~0; | |
847 | ||
848 | dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line)); | |
849 | if (!dram_line) | |
850 | return FALSE; | |
851 | ||
852 | sr_info("Downloading sample data."); | |
853 | ||
854 | /* Stop acquisition. */ | |
855 | sigma_set_register(WRITE_MODE, 0x11, devc); | |
856 | ||
857 | /* Set SDRAM Read Enable. */ | |
858 | sigma_set_register(WRITE_MODE, 0x02, devc); | |
859 | ||
860 | /* Get the current position. */ | |
861 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
862 | ||
863 | /* Check if trigger has fired. */ | |
864 | modestatus = sigma_get_register(READ_MODE, devc); | |
865 | if (modestatus & 0x20) { | |
866 | trg_line = triggerpos >> 9; | |
867 | trg_event = triggerpos & 0x1ff; | |
868 | } | |
869 | ||
870 | /* | |
871 | * Determine how many 1024b "DRAM lines" do we need to read from the | |
872 | * Sigma so we have a complete set of samples. Note that the last | |
873 | * line can be only partial, containing less than 64 clusters. | |
874 | */ | |
875 | dl_lines_total = (stoppos >> 9) + 1; | |
876 | ||
877 | dl_lines_done = 0; | |
878 | ||
879 | while (dl_lines_total > dl_lines_done) { | |
880 | /* We can download only up-to 32 DRAM lines in one go! */ | |
881 | dl_lines_curr = MIN(chunks_per_read, dl_lines_total); | |
882 | ||
883 | bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr, | |
884 | (uint8_t *)dram_line, devc); | |
885 | /* TODO: Check bufsz. For now, just avoid compiler warnings. */ | |
886 | (void)bufsz; | |
887 | ||
888 | /* This is the first DRAM line, so find the initial timestamp. */ | |
889 | if (dl_lines_done == 0) { | |
890 | devc->state.lastts = | |
891 | sigma_dram_cluster_ts(&dram_line[0].cluster[0]); | |
892 | devc->state.lastsample = 0; | |
893 | } | |
894 | ||
895 | for (i = 0; i < dl_lines_curr; i++) { | |
896 | uint32_t trigger_event = ~0; | |
897 | /* The last "DRAM line" can be only partially full. */ | |
898 | if (dl_lines_done + i == dl_lines_total - 1) | |
899 | dl_events_in_line = stoppos & 0x1ff; | |
900 | ||
901 | /* Test if the trigger happened on this line. */ | |
902 | if (dl_lines_done + i == trg_line) | |
903 | trigger_event = trg_event; | |
904 | ||
905 | decode_chunk_ts(dram_line + i, dl_events_in_line, | |
906 | trigger_event, sdi); | |
907 | } | |
908 | ||
909 | dl_lines_done += dl_lines_curr; | |
910 | } | |
911 | ||
912 | /* All done. */ | |
913 | packet.type = SR_DF_END; | |
914 | sr_session_send(sdi, &packet); | |
915 | ||
916 | sdi->driver->dev_acquisition_stop(sdi, sdi); | |
917 | ||
918 | g_free(dram_line); | |
919 | ||
920 | return TRUE; | |
921 | } | |
922 | ||
923 | /* | |
924 | * Handle the Sigma when in CAPTURE mode. This function checks: | |
925 | * - Sampling time ended | |
926 | * - DRAM capacity overflow | |
927 | * This function triggers download of the samples from Sigma | |
928 | * in case either of the above conditions is true. | |
929 | */ | |
930 | static int sigma_capture_mode(struct sr_dev_inst *sdi) | |
931 | { | |
932 | struct dev_context *devc = sdi->priv; | |
933 | ||
934 | uint64_t running_msec; | |
935 | struct timeval tv; | |
936 | ||
937 | uint32_t stoppos, triggerpos; | |
938 | ||
939 | /* Check if the selected sampling duration passed. */ | |
940 | gettimeofday(&tv, 0); | |
941 | running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 + | |
942 | (tv.tv_usec - devc->start_tv.tv_usec) / 1000; | |
943 | if (running_msec >= devc->limit_msec) | |
944 | return download_capture(sdi); | |
945 | ||
946 | /* Get the position in DRAM to which the FPGA is writing now. */ | |
947 | sigma_read_pos(&stoppos, &triggerpos, devc); | |
948 | /* Test if DRAM is full and if so, download the data. */ | |
949 | if ((stoppos >> 9) == 32767) | |
950 | return download_capture(sdi); | |
951 | ||
952 | return TRUE; | |
953 | } | |
954 | ||
955 | SR_PRIV int sigma_receive_data(int fd, int revents, void *cb_data) | |
956 | { | |
957 | struct sr_dev_inst *sdi; | |
958 | struct dev_context *devc; | |
959 | ||
960 | (void)fd; | |
961 | (void)revents; | |
962 | ||
963 | sdi = cb_data; | |
964 | devc = sdi->priv; | |
965 | ||
966 | if (devc->state.state == SIGMA_IDLE) | |
967 | return TRUE; | |
968 | ||
969 | if (devc->state.state == SIGMA_CAPTURE) | |
970 | return sigma_capture_mode(sdi); | |
971 | ||
972 | return TRUE; | |
973 | } | |
974 | ||
975 | /* Build a LUT entry used by the trigger functions. */ | |
976 | static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry) | |
977 | { | |
978 | int i, j, k, bit; | |
979 | ||
980 | /* For each quad channel. */ | |
981 | for (i = 0; i < 4; ++i) { | |
982 | entry[i] = 0xffff; | |
983 | ||
984 | /* For each bit in LUT. */ | |
985 | for (j = 0; j < 16; ++j) | |
986 | ||
987 | /* For each channel in quad. */ | |
988 | for (k = 0; k < 4; ++k) { | |
989 | bit = 1 << (i * 4 + k); | |
990 | ||
991 | /* Set bit in entry */ | |
992 | if ((mask & bit) && | |
993 | ((!(value & bit)) != | |
994 | (!(j & (1 << k))))) | |
995 | entry[i] &= ~(1 << j); | |
996 | } | |
997 | } | |
998 | } | |
999 | ||
1000 | /* Add a logical function to LUT mask. */ | |
1001 | static void add_trigger_function(enum triggerop oper, enum triggerfunc func, | |
1002 | int index, int neg, uint16_t *mask) | |
1003 | { | |
1004 | int i, j; | |
1005 | int x[2][2], tmp, a, b, aset, bset, rset; | |
1006 | ||
1007 | memset(x, 0, 4 * sizeof(int)); | |
1008 | ||
1009 | /* Trigger detect condition. */ | |
1010 | switch (oper) { | |
1011 | case OP_LEVEL: | |
1012 | x[0][1] = 1; | |
1013 | x[1][1] = 1; | |
1014 | break; | |
1015 | case OP_NOT: | |
1016 | x[0][0] = 1; | |
1017 | x[1][0] = 1; | |
1018 | break; | |
1019 | case OP_RISE: | |
1020 | x[0][1] = 1; | |
1021 | break; | |
1022 | case OP_FALL: | |
1023 | x[1][0] = 1; | |
1024 | break; | |
1025 | case OP_RISEFALL: | |
1026 | x[0][1] = 1; | |
1027 | x[1][0] = 1; | |
1028 | break; | |
1029 | case OP_NOTRISE: | |
1030 | x[1][1] = 1; | |
1031 | x[0][0] = 1; | |
1032 | x[1][0] = 1; | |
1033 | break; | |
1034 | case OP_NOTFALL: | |
1035 | x[1][1] = 1; | |
1036 | x[0][0] = 1; | |
1037 | x[0][1] = 1; | |
1038 | break; | |
1039 | case OP_NOTRISEFALL: | |
1040 | x[1][1] = 1; | |
1041 | x[0][0] = 1; | |
1042 | break; | |
1043 | } | |
1044 | ||
1045 | /* Transpose if neg is set. */ | |
1046 | if (neg) { | |
1047 | for (i = 0; i < 2; ++i) { | |
1048 | for (j = 0; j < 2; ++j) { | |
1049 | tmp = x[i][j]; | |
1050 | x[i][j] = x[1-i][1-j]; | |
1051 | x[1-i][1-j] = tmp; | |
1052 | } | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | /* Update mask with function. */ | |
1057 | for (i = 0; i < 16; ++i) { | |
1058 | a = (i >> (2 * index + 0)) & 1; | |
1059 | b = (i >> (2 * index + 1)) & 1; | |
1060 | ||
1061 | aset = (*mask >> i) & 1; | |
1062 | bset = x[b][a]; | |
1063 | ||
1064 | rset = 0; | |
1065 | if (func == FUNC_AND || func == FUNC_NAND) | |
1066 | rset = aset & bset; | |
1067 | else if (func == FUNC_OR || func == FUNC_NOR) | |
1068 | rset = aset | bset; | |
1069 | else if (func == FUNC_XOR || func == FUNC_NXOR) | |
1070 | rset = aset ^ bset; | |
1071 | ||
1072 | if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR) | |
1073 | rset = !rset; | |
1074 | ||
1075 | *mask &= ~(1 << i); | |
1076 | ||
1077 | if (rset) | |
1078 | *mask |= 1 << i; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Build trigger LUTs used by 50 MHz and lower sample rates for supporting | |
1084 | * simple pin change and state triggers. Only two transitions (rise/fall) can be | |
1085 | * set at any time, but a full mask and value can be set (0/1). | |
1086 | */ | |
1087 | SR_PRIV int sigma_build_basic_trigger(struct triggerlut *lut, struct dev_context *devc) | |
1088 | { | |
1089 | int i,j; | |
1090 | uint16_t masks[2] = { 0, 0 }; | |
1091 | ||
1092 | memset(lut, 0, sizeof(struct triggerlut)); | |
1093 | ||
1094 | /* Constant for simple triggers. */ | |
1095 | lut->m4 = 0xa000; | |
1096 | ||
1097 | /* Value/mask trigger support. */ | |
1098 | build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask, | |
1099 | lut->m2d); | |
1100 | ||
1101 | /* Rise/fall trigger support. */ | |
1102 | for (i = 0, j = 0; i < 16; ++i) { | |
1103 | if (devc->trigger.risingmask & (1 << i) || | |
1104 | devc->trigger.fallingmask & (1 << i)) | |
1105 | masks[j++] = 1 << i; | |
1106 | } | |
1107 | ||
1108 | build_lut_entry(masks[0], masks[0], lut->m0d); | |
1109 | build_lut_entry(masks[1], masks[1], lut->m1d); | |
1110 | ||
1111 | /* Add glue logic */ | |
1112 | if (masks[0] || masks[1]) { | |
1113 | /* Transition trigger. */ | |
1114 | if (masks[0] & devc->trigger.risingmask) | |
1115 | add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3); | |
1116 | if (masks[0] & devc->trigger.fallingmask) | |
1117 | add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3); | |
1118 | if (masks[1] & devc->trigger.risingmask) | |
1119 | add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3); | |
1120 | if (masks[1] & devc->trigger.fallingmask) | |
1121 | add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3); | |
1122 | } else { | |
1123 | /* Only value/mask trigger. */ | |
1124 | lut->m3 = 0xffff; | |
1125 | } | |
1126 | ||
1127 | /* Triggertype: event. */ | |
1128 | lut->params.selres = 3; | |
1129 | ||
1130 | return SR_OK; | |
1131 | } |