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[libsigrok.git] / src / hardware / asix-sigma / asix-sigma.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <unistd.h>
31#include "libsigrok.h"
32#include "libsigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
43
44/*
45 * The ASIX Sigma supports arbitrary integer frequency divider in
46 * the 50MHz mode. The divider is in range 1...256 , allowing for
47 * very precise sampling rate selection. This driver supports only
48 * a subset of the sampling rates.
49 */
50static const uint64_t samplerates[] = {
51 SR_KHZ(200), /* div=250 */
52 SR_KHZ(250), /* div=200 */
53 SR_KHZ(500), /* div=100 */
54 SR_MHZ(1), /* div=50 */
55 SR_MHZ(5), /* div=10 */
56 SR_MHZ(10), /* div=5 */
57 SR_MHZ(25), /* div=2 */
58 SR_MHZ(50), /* div=1 */
59 SR_MHZ(100), /* Special FW needed */
60 SR_MHZ(200), /* Special FW needed */
61};
62
63/*
64 * Channel numbers seem to go from 1-16, according to this image:
65 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
66 * (the cable has two additional GND pins, and a TI and TO pin)
67 */
68static const char *channel_names[] = {
69 "1", "2", "3", "4", "5", "6", "7", "8",
70 "9", "10", "11", "12", "13", "14", "15", "16",
71};
72
73static const uint32_t drvopts[] = {
74 SR_CONF_LOGIC_ANALYZER,
75};
76
77static const uint32_t devopts[] = {
78 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
79 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
80 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
81 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
82 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
83};
84
85static const int32_t trigger_matches[] = {
86 SR_TRIGGER_ZERO,
87 SR_TRIGGER_ONE,
88 SR_TRIGGER_RISING,
89 SR_TRIGGER_FALLING,
90};
91
92static const char *sigma_firmware_files[] = {
93 /* 50 MHz, supports 8 bit fractions */
94 FIRMWARE_DIR "/asix-sigma-50.fw",
95 /* 100 MHz */
96 FIRMWARE_DIR "/asix-sigma-100.fw",
97 /* 200 MHz */
98 FIRMWARE_DIR "/asix-sigma-200.fw",
99 /* Synchronous clock from pin */
100 FIRMWARE_DIR "/asix-sigma-50sync.fw",
101 /* Frequency counter */
102 FIRMWARE_DIR "/asix-sigma-phasor.fw",
103};
104
105static int sigma_read(void *buf, size_t size, struct dev_context *devc)
106{
107 int ret;
108
109 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
110 if (ret < 0) {
111 sr_err("ftdi_read_data failed: %s",
112 ftdi_get_error_string(&devc->ftdic));
113 }
114
115 return ret;
116}
117
118static int sigma_write(void *buf, size_t size, struct dev_context *devc)
119{
120 int ret;
121
122 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
123 if (ret < 0) {
124 sr_err("ftdi_write_data failed: %s",
125 ftdi_get_error_string(&devc->ftdic));
126 } else if ((size_t) ret != size) {
127 sr_err("ftdi_write_data did not complete write.");
128 }
129
130 return ret;
131}
132
133static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
134 struct dev_context *devc)
135{
136 size_t i;
137 uint8_t buf[len + 2];
138 int idx = 0;
139
140 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
141 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
142
143 for (i = 0; i < len; ++i) {
144 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
145 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
146 }
147
148 return sigma_write(buf, idx, devc);
149}
150
151static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
152{
153 return sigma_write_register(reg, &value, 1, devc);
154}
155
156static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
157 struct dev_context *devc)
158{
159 uint8_t buf[3];
160
161 buf[0] = REG_ADDR_LOW | (reg & 0xf);
162 buf[1] = REG_ADDR_HIGH | (reg >> 4);
163 buf[2] = REG_READ_ADDR;
164
165 sigma_write(buf, sizeof(buf), devc);
166
167 return sigma_read(data, len, devc);
168}
169
170static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
171{
172 uint8_t value;
173
174 if (1 != sigma_read_register(reg, &value, 1, devc)) {
175 sr_err("sigma_get_register: 1 byte expected");
176 return 0;
177 }
178
179 return value;
180}
181
182static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
183 struct dev_context *devc)
184{
185 uint8_t buf[] = {
186 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
187
188 REG_READ_ADDR | NEXT_REG,
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 };
195 uint8_t result[6];
196
197 sigma_write(buf, sizeof(buf), devc);
198
199 sigma_read(result, sizeof(result), devc);
200
201 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
202 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
203
204 /* Not really sure why this must be done, but according to spec. */
205 if ((--*stoppos & 0x1ff) == 0x1ff)
206 *stoppos -= 64;
207
208 if ((*--triggerpos & 0x1ff) == 0x1ff)
209 *triggerpos -= 64;
210
211 return 1;
212}
213
214static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
215 uint8_t *data, struct dev_context *devc)
216{
217 size_t i;
218 uint8_t buf[4096];
219 int idx = 0;
220
221 /* Send the startchunk. Index start with 1. */
222 buf[0] = startchunk >> 8;
223 buf[1] = startchunk & 0xff;
224 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
225
226 /* Read the DRAM. */
227 buf[idx++] = REG_DRAM_BLOCK;
228 buf[idx++] = REG_DRAM_WAIT_ACK;
229
230 for (i = 0; i < numchunks; ++i) {
231 /* Alternate bit to copy from DRAM to cache. */
232 if (i != (numchunks - 1))
233 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
234
235 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
236
237 if (i != (numchunks - 1))
238 buf[idx++] = REG_DRAM_WAIT_ACK;
239 }
240
241 sigma_write(buf, idx, devc);
242
243 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
244}
245
246/* Upload trigger look-up tables to Sigma. */
247static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
248{
249 int i;
250 uint8_t tmp[2];
251 uint16_t bit;
252
253 /* Transpose the table and send to Sigma. */
254 for (i = 0; i < 16; ++i) {
255 bit = 1 << i;
256
257 tmp[0] = tmp[1] = 0;
258
259 if (lut->m2d[0] & bit)
260 tmp[0] |= 0x01;
261 if (lut->m2d[1] & bit)
262 tmp[0] |= 0x02;
263 if (lut->m2d[2] & bit)
264 tmp[0] |= 0x04;
265 if (lut->m2d[3] & bit)
266 tmp[0] |= 0x08;
267
268 if (lut->m3 & bit)
269 tmp[0] |= 0x10;
270 if (lut->m3s & bit)
271 tmp[0] |= 0x20;
272 if (lut->m4 & bit)
273 tmp[0] |= 0x40;
274
275 if (lut->m0d[0] & bit)
276 tmp[1] |= 0x01;
277 if (lut->m0d[1] & bit)
278 tmp[1] |= 0x02;
279 if (lut->m0d[2] & bit)
280 tmp[1] |= 0x04;
281 if (lut->m0d[3] & bit)
282 tmp[1] |= 0x08;
283
284 if (lut->m1d[0] & bit)
285 tmp[1] |= 0x10;
286 if (lut->m1d[1] & bit)
287 tmp[1] |= 0x20;
288 if (lut->m1d[2] & bit)
289 tmp[1] |= 0x40;
290 if (lut->m1d[3] & bit)
291 tmp[1] |= 0x80;
292
293 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
294 devc);
295 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
296 }
297
298 /* Send the parameters */
299 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
300 sizeof(lut->params), devc);
301
302 return SR_OK;
303}
304
305static void clear_helper(void *priv)
306{
307 struct dev_context *devc;
308
309 devc = priv;
310
311 ftdi_deinit(&devc->ftdic);
312}
313
314static int dev_clear(const struct sr_dev_driver *di)
315{
316 return std_dev_clear(di, clear_helper);
317}
318
319static int init(struct sr_dev_driver *di, struct sr_context *sr_ctx)
320{
321 return std_init(sr_ctx, di, LOG_PREFIX);
322}
323
324static GSList *scan(struct sr_dev_driver *di, GSList *options)
325{
326 struct sr_dev_inst *sdi;
327 struct drv_context *drvc;
328 struct dev_context *devc;
329 GSList *devices;
330 struct ftdi_device_list *devlist;
331 char serial_txt[10];
332 uint32_t serial;
333 int ret;
334 unsigned int i;
335
336 (void)options;
337
338 drvc = di->priv;
339
340 devices = NULL;
341
342 devc = g_malloc0(sizeof(struct dev_context));
343
344 ftdi_init(&devc->ftdic);
345
346 /* Look for SIGMAs. */
347
348 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
349 USB_VENDOR, USB_PRODUCT)) <= 0) {
350 if (ret < 0)
351 sr_err("ftdi_usb_find_all(): %d", ret);
352 goto free;
353 }
354
355 /* Make sure it's a version 1 or 2 SIGMA. */
356 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
357 serial_txt, sizeof(serial_txt));
358 sscanf(serial_txt, "%x", &serial);
359
360 if (serial < 0xa6010000 || serial > 0xa602ffff) {
361 sr_err("Only SIGMA and SIGMA2 are supported "
362 "in this version of libsigrok.");
363 goto free;
364 }
365
366 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
367
368 devc->cur_samplerate = samplerates[0];
369 devc->period_ps = 0;
370 devc->limit_msec = 0;
371 devc->cur_firmware = -1;
372 devc->num_channels = 0;
373 devc->samples_per_event = 0;
374 devc->capture_ratio = 50;
375 devc->use_triggers = 0;
376
377 /* Register SIGMA device. */
378 sdi = g_malloc0(sizeof(struct sr_dev_inst));
379 sdi->status = SR_ST_INITIALIZING;
380 sdi->vendor = g_strdup(USB_VENDOR_NAME);
381 sdi->model = g_strdup(USB_MODEL_NAME);
382 sdi->driver = di;
383
384 for (i = 0; i < ARRAY_SIZE(channel_names); i++)
385 sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE,
386 channel_names[i]);
387
388 devices = g_slist_append(devices, sdi);
389 drvc->instances = g_slist_append(drvc->instances, sdi);
390 sdi->priv = devc;
391
392 /* We will open the device again when we need it. */
393 ftdi_list_free(&devlist);
394
395 return devices;
396
397free:
398 ftdi_deinit(&devc->ftdic);
399 g_free(devc);
400 return NULL;
401}
402
403static GSList *dev_list(const struct sr_dev_driver *di)
404{
405 return ((struct drv_context *)(di->priv))->instances;
406}
407
408/*
409 * Configure the FPGA for bitbang mode.
410 * This sequence is documented in section 2. of the ASIX Sigma programming
411 * manual. This sequence is necessary to configure the FPGA in the Sigma
412 * into Bitbang mode, in which it can be programmed with the firmware.
413 */
414static int sigma_fpga_init_bitbang(struct dev_context *devc)
415{
416 uint8_t suicide[] = {
417 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
418 };
419 uint8_t init_array[] = {
420 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
421 0x01, 0x01,
422 };
423 int i, ret, timeout = 10000;
424 uint8_t data;
425
426 /* Section 2. part 1), do the FPGA suicide. */
427 sigma_write(suicide, sizeof(suicide), devc);
428 sigma_write(suicide, sizeof(suicide), devc);
429 sigma_write(suicide, sizeof(suicide), devc);
430 sigma_write(suicide, sizeof(suicide), devc);
431
432 /* Section 2. part 2), do pulse on D1. */
433 sigma_write(init_array, sizeof(init_array), devc);
434 ftdi_usb_purge_buffers(&devc->ftdic);
435
436 /* Wait until the FPGA asserts D6/INIT_B. */
437 for (i = 0; i < timeout; i++) {
438 ret = sigma_read(&data, 1, devc);
439 if (ret < 0)
440 return ret;
441 /* Test if pin D6 got asserted. */
442 if (data & (1 << 5))
443 return 0;
444 /* The D6 was not asserted yet, wait a bit. */
445 g_usleep(10000);
446 }
447
448 return SR_ERR_TIMEOUT;
449}
450
451/*
452 * Configure the FPGA for logic-analyzer mode.
453 */
454static int sigma_fpga_init_la(struct dev_context *devc)
455{
456 /* Initialize the logic analyzer mode. */
457 uint8_t logic_mode_start[] = {
458 REG_ADDR_LOW | (READ_ID & 0xf),
459 REG_ADDR_HIGH | (READ_ID >> 8),
460 REG_READ_ADDR, /* Read ID register. */
461
462 REG_ADDR_LOW | (WRITE_TEST & 0xf),
463 REG_DATA_LOW | 0x5,
464 REG_DATA_HIGH_WRITE | 0x5,
465 REG_READ_ADDR, /* Read scratch register. */
466
467 REG_DATA_LOW | 0xa,
468 REG_DATA_HIGH_WRITE | 0xa,
469 REG_READ_ADDR, /* Read scratch register. */
470
471 REG_ADDR_LOW | (WRITE_MODE & 0xf),
472 REG_DATA_LOW | 0x0,
473 REG_DATA_HIGH_WRITE | 0x8,
474 };
475
476 uint8_t result[3];
477 int ret;
478
479 /* Initialize the logic analyzer mode. */
480 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
481
482 /* Expect a 3 byte reply since we issued three READ requests. */
483 ret = sigma_read(result, 3, devc);
484 if (ret != 3)
485 goto err;
486
487 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
488 goto err;
489
490 return SR_OK;
491err:
492 sr_err("Configuration failed. Invalid reply received.");
493 return SR_ERR;
494}
495
496/*
497 * Read the firmware from a file and transform it into a series of bitbang
498 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
499 * by the caller of this function.
500 */
501static int sigma_fw_2_bitbang(const char *filename,
502 uint8_t **bb_cmd, gsize *bb_cmd_size)
503{
504 GMappedFile *file;
505 GError *error;
506 gsize i, file_size, bb_size;
507 gchar *firmware;
508 uint8_t *bb_stream, *bbs;
509 uint32_t imm;
510 int bit, v;
511 int ret = SR_OK;
512
513 /*
514 * Map the file and make the mapped buffer writable.
515 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
516 * will be modified. It will not be modified until someone uses
517 * g_file_set_contents() on it.
518 */
519 error = NULL;
520 file = g_mapped_file_new(filename, TRUE, &error);
521 g_assert_no_error(error);
522
523 file_size = g_mapped_file_get_length(file);
524 firmware = g_mapped_file_get_contents(file);
525 g_assert(firmware);
526
527 /* Weird magic transformation below, I have no idea what it does. */
528 imm = 0x3f6df2ab;
529 for (i = 0; i < file_size; i++) {
530 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
531 firmware[i] ^= imm & 0xff;
532 }
533
534 /*
535 * Now that the firmware is "transformed", we will transcribe the
536 * firmware blob into a sequence of toggles of the Dx wires. This
537 * sequence will be fed directly into the Sigma, which must be in
538 * the FPGA bitbang programming mode.
539 */
540
541 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
542 bb_size = file_size * 8 * 2;
543 bb_stream = (uint8_t *)g_try_malloc(bb_size);
544 if (!bb_stream) {
545 sr_err("%s: Failed to allocate bitbang stream", __func__);
546 ret = SR_ERR_MALLOC;
547 goto exit;
548 }
549
550 bbs = bb_stream;
551 for (i = 0; i < file_size; i++) {
552 for (bit = 7; bit >= 0; bit--) {
553 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
554 *bbs++ = v | 0x01;
555 *bbs++ = v;
556 }
557 }
558
559 /* The transformation completed successfully, return the result. */
560 *bb_cmd = bb_stream;
561 *bb_cmd_size = bb_size;
562
563exit:
564 g_mapped_file_unref(file);
565 return ret;
566}
567
568static int upload_firmware(int firmware_idx, struct dev_context *devc)
569{
570 int ret;
571 unsigned char *buf;
572 unsigned char pins;
573 size_t buf_size;
574 const char *firmware = sigma_firmware_files[firmware_idx];
575 struct ftdi_context *ftdic = &devc->ftdic;
576
577 /* Make sure it's an ASIX SIGMA. */
578 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
579 USB_DESCRIPTION, NULL);
580 if (ret < 0) {
581 sr_err("ftdi_usb_open failed: %s",
582 ftdi_get_error_string(ftdic));
583 return 0;
584 }
585
586 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
587 if (ret < 0) {
588 sr_err("ftdi_set_bitmode failed: %s",
589 ftdi_get_error_string(ftdic));
590 return 0;
591 }
592
593 /* Four times the speed of sigmalogan - Works well. */
594 ret = ftdi_set_baudrate(ftdic, 750000);
595 if (ret < 0) {
596 sr_err("ftdi_set_baudrate failed: %s",
597 ftdi_get_error_string(ftdic));
598 return 0;
599 }
600
601 /* Initialize the FPGA for firmware upload. */
602 ret = sigma_fpga_init_bitbang(devc);
603 if (ret)
604 return ret;
605
606 /* Prepare firmware. */
607 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
608 if (ret != SR_OK) {
609 sr_err("An error occured while reading the firmware: %s",
610 firmware);
611 return ret;
612 }
613
614 /* Upload firmare. */
615 sr_info("Uploading firmware file '%s'.", firmware);
616 sigma_write(buf, buf_size, devc);
617
618 g_free(buf);
619
620 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
621 if (ret < 0) {
622 sr_err("ftdi_set_bitmode failed: %s",
623 ftdi_get_error_string(ftdic));
624 return SR_ERR;
625 }
626
627 ftdi_usb_purge_buffers(ftdic);
628
629 /* Discard garbage. */
630 while (sigma_read(&pins, 1, devc) == 1)
631 ;
632
633 /* Initialize the FPGA for logic-analyzer mode. */
634 ret = sigma_fpga_init_la(devc);
635 if (ret != SR_OK)
636 return ret;
637
638 devc->cur_firmware = firmware_idx;
639
640 sr_info("Firmware uploaded.");
641
642 return SR_OK;
643}
644
645static int dev_open(struct sr_dev_inst *sdi)
646{
647 struct dev_context *devc;
648 int ret;
649
650 devc = sdi->priv;
651
652 /* Make sure it's an ASIX SIGMA. */
653 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
654 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
655
656 sr_err("ftdi_usb_open failed: %s",
657 ftdi_get_error_string(&devc->ftdic));
658
659 return 0;
660 }
661
662 sdi->status = SR_ST_ACTIVE;
663
664 return SR_OK;
665}
666
667static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
668{
669 struct dev_context *devc;
670 unsigned int i;
671 int ret;
672
673 devc = sdi->priv;
674 ret = SR_OK;
675
676 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
677 if (samplerates[i] == samplerate)
678 break;
679 }
680 if (samplerates[i] == 0)
681 return SR_ERR_SAMPLERATE;
682
683 if (samplerate <= SR_MHZ(50)) {
684 ret = upload_firmware(0, devc);
685 devc->num_channels = 16;
686 } else if (samplerate == SR_MHZ(100)) {
687 ret = upload_firmware(1, devc);
688 devc->num_channels = 8;
689 } else if (samplerate == SR_MHZ(200)) {
690 ret = upload_firmware(2, devc);
691 devc->num_channels = 4;
692 }
693
694 if (ret == SR_OK) {
695 devc->cur_samplerate = samplerate;
696 devc->period_ps = 1000000000000ULL / samplerate;
697 devc->samples_per_event = 16 / devc->num_channels;
698 devc->state.state = SIGMA_IDLE;
699 }
700
701 return ret;
702}
703
704/*
705 * In 100 and 200 MHz mode, only a single pin rising/falling can be
706 * set as trigger. In other modes, two rising/falling triggers can be set,
707 * in addition to value/mask trigger for any number of channels.
708 *
709 * The Sigma supports complex triggers using boolean expressions, but this
710 * has not been implemented yet.
711 */
712static int convert_trigger(const struct sr_dev_inst *sdi)
713{
714 struct dev_context *devc;
715 struct sr_trigger *trigger;
716 struct sr_trigger_stage *stage;
717 struct sr_trigger_match *match;
718 const GSList *l, *m;
719 int channelbit, trigger_set;
720
721 devc = sdi->priv;
722 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
723 if (!(trigger = sr_session_trigger_get(sdi->session)))
724 return SR_OK;
725
726 trigger_set = 0;
727 for (l = trigger->stages; l; l = l->next) {
728 stage = l->data;
729 for (m = stage->matches; m; m = m->next) {
730 match = m->data;
731 if (!match->channel->enabled)
732 /* Ignore disabled channels with a trigger. */
733 continue;
734 channelbit = 1 << (match->channel->index);
735 if (devc->cur_samplerate >= SR_MHZ(100)) {
736 /* Fast trigger support. */
737 if (trigger_set) {
738 sr_err("Only a single pin trigger is "
739 "supported in 100 and 200MHz mode.");
740 return SR_ERR;
741 }
742 if (match->match == SR_TRIGGER_FALLING)
743 devc->trigger.fallingmask |= channelbit;
744 else if (match->match == SR_TRIGGER_RISING)
745 devc->trigger.risingmask |= channelbit;
746 else {
747 sr_err("Only rising/falling trigger is "
748 "supported in 100 and 200MHz mode.");
749 return SR_ERR;
750 }
751
752 ++trigger_set;
753 } else {
754 /* Simple trigger support (event). */
755 if (match->match == SR_TRIGGER_ONE) {
756 devc->trigger.simplevalue |= channelbit;
757 devc->trigger.simplemask |= channelbit;
758 }
759 else if (match->match == SR_TRIGGER_ZERO) {
760 devc->trigger.simplevalue &= ~channelbit;
761 devc->trigger.simplemask |= channelbit;
762 }
763 else if (match->match == SR_TRIGGER_FALLING) {
764 devc->trigger.fallingmask |= channelbit;
765 ++trigger_set;
766 }
767 else if (match->match == SR_TRIGGER_RISING) {
768 devc->trigger.risingmask |= channelbit;
769 ++trigger_set;
770 }
771
772 /*
773 * Actually, Sigma supports 2 rising/falling triggers,
774 * but they are ORed and the current trigger syntax
775 * does not permit ORed triggers.
776 */
777 if (trigger_set > 1) {
778 sr_err("Only 1 rising/falling trigger "
779 "is supported.");
780 return SR_ERR;
781 }
782 }
783 }
784 }
785
786
787 return SR_OK;
788}
789
790static int dev_close(struct sr_dev_inst *sdi)
791{
792 struct dev_context *devc;
793
794 devc = sdi->priv;
795
796 /* TODO */
797 if (sdi->status == SR_ST_ACTIVE)
798 ftdi_usb_close(&devc->ftdic);
799
800 sdi->status = SR_ST_INACTIVE;
801
802 return SR_OK;
803}
804
805static int cleanup(const struct sr_dev_driver *di)
806{
807 return dev_clear(di);
808}
809
810static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
811 const struct sr_channel_group *cg)
812{
813 struct dev_context *devc;
814
815 (void)cg;
816
817 if (!sdi)
818 return SR_ERR;
819 devc = sdi->priv;
820
821 switch (key) {
822 case SR_CONF_SAMPLERATE:
823 *data = g_variant_new_uint64(devc->cur_samplerate);
824 break;
825 case SR_CONF_LIMIT_MSEC:
826 *data = g_variant_new_uint64(devc->limit_msec);
827 break;
828 case SR_CONF_CAPTURE_RATIO:
829 *data = g_variant_new_uint64(devc->capture_ratio);
830 break;
831 default:
832 return SR_ERR_NA;
833 }
834
835 return SR_OK;
836}
837
838static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
839 const struct sr_channel_group *cg)
840{
841 struct dev_context *devc;
842 uint64_t tmp;
843 int ret;
844
845 (void)cg;
846
847 if (sdi->status != SR_ST_ACTIVE)
848 return SR_ERR_DEV_CLOSED;
849
850 devc = sdi->priv;
851
852 ret = SR_OK;
853 switch (key) {
854 case SR_CONF_SAMPLERATE:
855 ret = set_samplerate(sdi, g_variant_get_uint64(data));
856 break;
857 case SR_CONF_LIMIT_MSEC:
858 tmp = g_variant_get_uint64(data);
859 if (tmp > 0)
860 devc->limit_msec = g_variant_get_uint64(data);
861 else
862 ret = SR_ERR;
863 break;
864 case SR_CONF_LIMIT_SAMPLES:
865 tmp = g_variant_get_uint64(data);
866 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
867 break;
868 case SR_CONF_CAPTURE_RATIO:
869 tmp = g_variant_get_uint64(data);
870 if (tmp <= 100)
871 devc->capture_ratio = tmp;
872 else
873 ret = SR_ERR;
874 break;
875 default:
876 ret = SR_ERR_NA;
877 }
878
879 return ret;
880}
881
882static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
883 const struct sr_channel_group *cg)
884{
885 GVariant *gvar;
886 GVariantBuilder gvb;
887
888 (void)sdi;
889 (void)cg;
890
891 switch (key) {
892 case SR_CONF_DEVICE_OPTIONS:
893 if (!sdi)
894 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
895 drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
896 else
897 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
898 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
899 break;
900 case SR_CONF_SAMPLERATE:
901 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
902 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
903 ARRAY_SIZE(samplerates), sizeof(uint64_t));
904 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
905 *data = g_variant_builder_end(&gvb);
906 break;
907 case SR_CONF_TRIGGER_MATCH:
908 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
909 trigger_matches, ARRAY_SIZE(trigger_matches),
910 sizeof(int32_t));
911 break;
912 default:
913 return SR_ERR_NA;
914 }
915
916 return SR_OK;
917}
918
919/* Software trigger to determine exact trigger position. */
920static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
921 struct sigma_trigger *t)
922{
923 int i;
924 uint16_t sample = 0;
925
926 for (i = 0; i < 8; ++i) {
927 if (i > 0)
928 last_sample = sample;
929 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
930
931 /* Simple triggers. */
932 if ((sample & t->simplemask) != t->simplevalue)
933 continue;
934
935 /* Rising edge. */
936 if (((last_sample & t->risingmask) != 0) ||
937 ((sample & t->risingmask) != t->risingmask))
938 continue;
939
940 /* Falling edge. */
941 if ((last_sample & t->fallingmask) != t->fallingmask ||
942 (sample & t->fallingmask) != 0)
943 continue;
944
945 break;
946 }
947
948 /* If we did not match, return original trigger pos. */
949 return i & 0x7;
950}
951
952
953/*
954 * Return the timestamp of "DRAM cluster".
955 */
956static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
957{
958 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
959}
960
961static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
962 unsigned int events_in_cluster,
963 unsigned int triggered,
964 struct sr_dev_inst *sdi)
965{
966 struct dev_context *devc = sdi->priv;
967 struct sigma_state *ss = &devc->state;
968 struct sr_datafeed_packet packet;
969 struct sr_datafeed_logic logic;
970 uint16_t tsdiff, ts;
971 uint8_t samples[2048];
972 unsigned int i;
973
974 ts = sigma_dram_cluster_ts(dram_cluster);
975 tsdiff = ts - ss->lastts;
976 ss->lastts = ts;
977
978 packet.type = SR_DF_LOGIC;
979 packet.payload = &logic;
980 logic.unitsize = 2;
981 logic.data = samples;
982
983 /*
984 * First of all, send Sigrok a copy of the last sample from
985 * previous cluster as many times as needed to make up for
986 * the differential characteristics of data we get from the
987 * Sigma. Sigrok needs one sample of data per period.
988 *
989 * One DRAM cluster contains a timestamp and seven samples,
990 * the units of timestamp are "devc->period_ps" , the first
991 * sample in the cluster happens at the time of the timestamp
992 * and the remaining samples happen at timestamp +1...+6 .
993 */
994 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
995 i = ts % 1024;
996 samples[2 * i + 0] = ss->lastsample & 0xff;
997 samples[2 * i + 1] = ss->lastsample >> 8;
998
999 /*
1000 * If we have 1024 samples ready or we're at the
1001 * end of submitting the padding samples, submit
1002 * the packet to Sigrok.
1003 */
1004 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1005 logic.length = (i + 1) * logic.unitsize;
1006 sr_session_send(sdi, &packet);
1007 }
1008 }
1009
1010 /*
1011 * Parse the samples in current cluster and prepare them
1012 * to be submitted to Sigrok.
1013 */
1014 for (i = 0; i < events_in_cluster; i++) {
1015 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1016 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1017 }
1018
1019 /* Send data up to trigger point (if triggered). */
1020 int trigger_offset = 0;
1021 if (triggered) {
1022 /*
1023 * Trigger is not always accurate to sample because of
1024 * pipeline delay. However, it always triggers before
1025 * the actual event. We therefore look at the next
1026 * samples to pinpoint the exact position of the trigger.
1027 */
1028 trigger_offset = get_trigger_offset(samples,
1029 ss->lastsample, &devc->trigger);
1030
1031 if (trigger_offset > 0) {
1032 packet.type = SR_DF_LOGIC;
1033 logic.length = trigger_offset * logic.unitsize;
1034 sr_session_send(sdi, &packet);
1035 events_in_cluster -= trigger_offset;
1036 }
1037
1038 /* Only send trigger if explicitly enabled. */
1039 if (devc->use_triggers) {
1040 packet.type = SR_DF_TRIGGER;
1041 sr_session_send(sdi, &packet);
1042 }
1043 }
1044
1045 if (events_in_cluster > 0) {
1046 packet.type = SR_DF_LOGIC;
1047 logic.length = events_in_cluster * logic.unitsize;
1048 logic.data = samples + (trigger_offset * logic.unitsize);
1049 sr_session_send(sdi, &packet);
1050 }
1051
1052 ss->lastsample =
1053 samples[2 * (events_in_cluster - 1) + 0] |
1054 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1055
1056}
1057
1058/*
1059 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1060 * Each event is 20ns apart, and can contain multiple samples.
1061 *
1062 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1063 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1064 * For 50 MHz and below, events contain one sample for each channel,
1065 * spread 20 ns apart.
1066 */
1067static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1068 uint16_t events_in_line,
1069 uint32_t trigger_event,
1070 struct sr_dev_inst *sdi)
1071{
1072 struct sigma_dram_cluster *dram_cluster;
1073 struct dev_context *devc = sdi->priv;
1074 unsigned int clusters_in_line =
1075 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1076 unsigned int events_in_cluster;
1077 unsigned int i;
1078 uint32_t trigger_cluster = ~0, triggered = 0;
1079
1080 /* Check if trigger is in this chunk. */
1081 if (trigger_event < (64 * 7)) {
1082 if (devc->cur_samplerate <= SR_MHZ(50)) {
1083 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1084 trigger_event);
1085 }
1086
1087 /* Find in which cluster the trigger occured. */
1088 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1089 }
1090
1091 /* For each full DRAM cluster. */
1092 for (i = 0; i < clusters_in_line; i++) {
1093 dram_cluster = &dram_line->cluster[i];
1094
1095 /* The last cluster might not be full. */
1096 if ((i == clusters_in_line - 1) &&
1097 (events_in_line % EVENTS_PER_CLUSTER)) {
1098 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1099 } else {
1100 events_in_cluster = EVENTS_PER_CLUSTER;
1101 }
1102
1103 triggered = (i == trigger_cluster);
1104 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1105 triggered, sdi);
1106 }
1107
1108 return SR_OK;
1109}
1110
1111static int download_capture(struct sr_dev_inst *sdi)
1112{
1113 struct dev_context *devc = sdi->priv;
1114 const uint32_t chunks_per_read = 32;
1115 struct sigma_dram_line *dram_line;
1116 int bufsz;
1117 uint32_t stoppos, triggerpos;
1118 struct sr_datafeed_packet packet;
1119 uint8_t modestatus;
1120
1121 uint32_t i;
1122 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1123 uint32_t dl_events_in_line = 64 * 7;
1124 uint32_t trg_line = ~0, trg_event = ~0;
1125
1126 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1127 if (!dram_line)
1128 return FALSE;
1129
1130 sr_info("Downloading sample data.");
1131
1132 /* Stop acquisition. */
1133 sigma_set_register(WRITE_MODE, 0x11, devc);
1134
1135 /* Set SDRAM Read Enable. */
1136 sigma_set_register(WRITE_MODE, 0x02, devc);
1137
1138 /* Get the current position. */
1139 sigma_read_pos(&stoppos, &triggerpos, devc);
1140
1141 /* Check if trigger has fired. */
1142 modestatus = sigma_get_register(READ_MODE, devc);
1143 if (modestatus & 0x20) {
1144 trg_line = triggerpos >> 9;
1145 trg_event = triggerpos & 0x1ff;
1146 }
1147
1148 /*
1149 * Determine how many 1024b "DRAM lines" do we need to read from the
1150 * Sigma so we have a complete set of samples. Note that the last
1151 * line can be only partial, containing less than 64 clusters.
1152 */
1153 dl_lines_total = (stoppos >> 9) + 1;
1154
1155 dl_lines_done = 0;
1156
1157 while (dl_lines_total > dl_lines_done) {
1158 /* We can download only up-to 32 DRAM lines in one go! */
1159 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1160
1161 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1162 (uint8_t *)dram_line, devc);
1163 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1164 (void)bufsz;
1165
1166 /* This is the first DRAM line, so find the initial timestamp. */
1167 if (dl_lines_done == 0) {
1168 devc->state.lastts =
1169 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1170 devc->state.lastsample = 0;
1171 }
1172
1173 for (i = 0; i < dl_lines_curr; i++) {
1174 uint32_t trigger_event = ~0;
1175 /* The last "DRAM line" can be only partially full. */
1176 if (dl_lines_done + i == dl_lines_total - 1)
1177 dl_events_in_line = stoppos & 0x1ff;
1178
1179 /* Test if the trigger happened on this line. */
1180 if (dl_lines_done + i == trg_line)
1181 trigger_event = trg_event;
1182
1183 decode_chunk_ts(dram_line + i, dl_events_in_line,
1184 trigger_event, sdi);
1185 }
1186
1187 dl_lines_done += dl_lines_curr;
1188 }
1189
1190 /* All done. */
1191 packet.type = SR_DF_END;
1192 sr_session_send(sdi, &packet);
1193
1194 dev_acquisition_stop(sdi, sdi);
1195
1196 g_free(dram_line);
1197
1198 return TRUE;
1199}
1200
1201/*
1202 * Handle the Sigma when in CAPTURE mode. This function checks:
1203 * - Sampling time ended
1204 * - DRAM capacity overflow
1205 * This function triggers download of the samples from Sigma
1206 * in case either of the above conditions is true.
1207 */
1208static int sigma_capture_mode(struct sr_dev_inst *sdi)
1209{
1210 struct dev_context *devc = sdi->priv;
1211
1212 uint64_t running_msec;
1213 struct timeval tv;
1214
1215 uint32_t stoppos, triggerpos;
1216
1217 /* Check if the selected sampling duration passed. */
1218 gettimeofday(&tv, 0);
1219 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1220 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1221 if (running_msec >= devc->limit_msec)
1222 return download_capture(sdi);
1223
1224 /* Get the position in DRAM to which the FPGA is writing now. */
1225 sigma_read_pos(&stoppos, &triggerpos, devc);
1226 /* Test if DRAM is full and if so, download the data. */
1227 if ((stoppos >> 9) == 32767)
1228 return download_capture(sdi);
1229
1230 return TRUE;
1231}
1232
1233static int receive_data(int fd, int revents, void *cb_data)
1234{
1235 struct sr_dev_inst *sdi;
1236 struct dev_context *devc;
1237
1238 (void)fd;
1239 (void)revents;
1240
1241 sdi = cb_data;
1242 devc = sdi->priv;
1243
1244 if (devc->state.state == SIGMA_IDLE)
1245 return TRUE;
1246
1247 if (devc->state.state == SIGMA_CAPTURE)
1248 return sigma_capture_mode(sdi);
1249
1250 return TRUE;
1251}
1252
1253/* Build a LUT entry used by the trigger functions. */
1254static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1255{
1256 int i, j, k, bit;
1257
1258 /* For each quad channel. */
1259 for (i = 0; i < 4; ++i) {
1260 entry[i] = 0xffff;
1261
1262 /* For each bit in LUT. */
1263 for (j = 0; j < 16; ++j)
1264
1265 /* For each channel in quad. */
1266 for (k = 0; k < 4; ++k) {
1267 bit = 1 << (i * 4 + k);
1268
1269 /* Set bit in entry */
1270 if ((mask & bit) &&
1271 ((!(value & bit)) !=
1272 (!(j & (1 << k)))))
1273 entry[i] &= ~(1 << j);
1274 }
1275 }
1276}
1277
1278/* Add a logical function to LUT mask. */
1279static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1280 int index, int neg, uint16_t *mask)
1281{
1282 int i, j;
1283 int x[2][2], tmp, a, b, aset, bset, rset;
1284
1285 memset(x, 0, 4 * sizeof(int));
1286
1287 /* Trigger detect condition. */
1288 switch (oper) {
1289 case OP_LEVEL:
1290 x[0][1] = 1;
1291 x[1][1] = 1;
1292 break;
1293 case OP_NOT:
1294 x[0][0] = 1;
1295 x[1][0] = 1;
1296 break;
1297 case OP_RISE:
1298 x[0][1] = 1;
1299 break;
1300 case OP_FALL:
1301 x[1][0] = 1;
1302 break;
1303 case OP_RISEFALL:
1304 x[0][1] = 1;
1305 x[1][0] = 1;
1306 break;
1307 case OP_NOTRISE:
1308 x[1][1] = 1;
1309 x[0][0] = 1;
1310 x[1][0] = 1;
1311 break;
1312 case OP_NOTFALL:
1313 x[1][1] = 1;
1314 x[0][0] = 1;
1315 x[0][1] = 1;
1316 break;
1317 case OP_NOTRISEFALL:
1318 x[1][1] = 1;
1319 x[0][0] = 1;
1320 break;
1321 }
1322
1323 /* Transpose if neg is set. */
1324 if (neg) {
1325 for (i = 0; i < 2; ++i) {
1326 for (j = 0; j < 2; ++j) {
1327 tmp = x[i][j];
1328 x[i][j] = x[1-i][1-j];
1329 x[1-i][1-j] = tmp;
1330 }
1331 }
1332 }
1333
1334 /* Update mask with function. */
1335 for (i = 0; i < 16; ++i) {
1336 a = (i >> (2 * index + 0)) & 1;
1337 b = (i >> (2 * index + 1)) & 1;
1338
1339 aset = (*mask >> i) & 1;
1340 bset = x[b][a];
1341
1342 rset = 0;
1343 if (func == FUNC_AND || func == FUNC_NAND)
1344 rset = aset & bset;
1345 else if (func == FUNC_OR || func == FUNC_NOR)
1346 rset = aset | bset;
1347 else if (func == FUNC_XOR || func == FUNC_NXOR)
1348 rset = aset ^ bset;
1349
1350 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1351 rset = !rset;
1352
1353 *mask &= ~(1 << i);
1354
1355 if (rset)
1356 *mask |= 1 << i;
1357 }
1358}
1359
1360/*
1361 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1362 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1363 * set at any time, but a full mask and value can be set (0/1).
1364 */
1365static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1366{
1367 int i,j;
1368 uint16_t masks[2] = { 0, 0 };
1369
1370 memset(lut, 0, sizeof(struct triggerlut));
1371
1372 /* Contant for simple triggers. */
1373 lut->m4 = 0xa000;
1374
1375 /* Value/mask trigger support. */
1376 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1377 lut->m2d);
1378
1379 /* Rise/fall trigger support. */
1380 for (i = 0, j = 0; i < 16; ++i) {
1381 if (devc->trigger.risingmask & (1 << i) ||
1382 devc->trigger.fallingmask & (1 << i))
1383 masks[j++] = 1 << i;
1384 }
1385
1386 build_lut_entry(masks[0], masks[0], lut->m0d);
1387 build_lut_entry(masks[1], masks[1], lut->m1d);
1388
1389 /* Add glue logic */
1390 if (masks[0] || masks[1]) {
1391 /* Transition trigger. */
1392 if (masks[0] & devc->trigger.risingmask)
1393 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1394 if (masks[0] & devc->trigger.fallingmask)
1395 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1396 if (masks[1] & devc->trigger.risingmask)
1397 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1398 if (masks[1] & devc->trigger.fallingmask)
1399 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1400 } else {
1401 /* Only value/mask trigger. */
1402 lut->m3 = 0xffff;
1403 }
1404
1405 /* Triggertype: event. */
1406 lut->params.selres = 3;
1407
1408 return SR_OK;
1409}
1410
1411static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1412{
1413 struct dev_context *devc;
1414 struct clockselect_50 clockselect;
1415 int frac, triggerpin, ret;
1416 uint8_t triggerselect = 0;
1417 struct triggerinout triggerinout_conf;
1418 struct triggerlut lut;
1419
1420 if (sdi->status != SR_ST_ACTIVE)
1421 return SR_ERR_DEV_CLOSED;
1422
1423 devc = sdi->priv;
1424
1425 if (convert_trigger(sdi) != SR_OK) {
1426 sr_err("Failed to configure triggers.");
1427 return SR_ERR;
1428 }
1429
1430 /* If the samplerate has not been set, default to 200 kHz. */
1431 if (devc->cur_firmware == -1) {
1432 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1433 return ret;
1434 }
1435
1436 /* Enter trigger programming mode. */
1437 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1438
1439 /* 100 and 200 MHz mode. */
1440 if (devc->cur_samplerate >= SR_MHZ(100)) {
1441 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1442
1443 /* Find which pin to trigger on from mask. */
1444 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1445 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1446 (1 << triggerpin))
1447 break;
1448
1449 /* Set trigger pin and light LED on trigger. */
1450 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1451
1452 /* Default rising edge. */
1453 if (devc->trigger.fallingmask)
1454 triggerselect |= 1 << 3;
1455
1456 /* All other modes. */
1457 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1458 build_basic_trigger(&lut, devc);
1459
1460 sigma_write_trigger_lut(&lut, devc);
1461
1462 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1463 }
1464
1465 /* Setup trigger in and out pins to default values. */
1466 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1467 triggerinout_conf.trgout_bytrigger = 1;
1468 triggerinout_conf.trgout_enable = 1;
1469
1470 sigma_write_register(WRITE_TRIGGER_OPTION,
1471 (uint8_t *) &triggerinout_conf,
1472 sizeof(struct triggerinout), devc);
1473
1474 /* Go back to normal mode. */
1475 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1476
1477 /* Set clock select register. */
1478 if (devc->cur_samplerate == SR_MHZ(200))
1479 /* Enable 4 channels. */
1480 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1481 else if (devc->cur_samplerate == SR_MHZ(100))
1482 /* Enable 8 channels. */
1483 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1484 else {
1485 /*
1486 * 50 MHz mode (or fraction thereof). Any fraction down to
1487 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1488 */
1489 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1490
1491 clockselect.async = 0;
1492 clockselect.fraction = frac;
1493 clockselect.disabled_channels = 0;
1494
1495 sigma_write_register(WRITE_CLOCK_SELECT,
1496 (uint8_t *) &clockselect,
1497 sizeof(clockselect), devc);
1498 }
1499
1500 /* Setup maximum post trigger time. */
1501 sigma_set_register(WRITE_POST_TRIGGER,
1502 (devc->capture_ratio * 255) / 100, devc);
1503
1504 /* Start acqusition. */
1505 gettimeofday(&devc->start_tv, 0);
1506 sigma_set_register(WRITE_MODE, 0x0d, devc);
1507
1508 devc->cb_data = cb_data;
1509
1510 /* Send header packet to the session bus. */
1511 std_session_send_df_header(sdi, LOG_PREFIX);
1512
1513 /* Add capture source. */
1514 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1515
1516 devc->state.state = SIGMA_CAPTURE;
1517
1518 return SR_OK;
1519}
1520
1521static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1522{
1523 struct dev_context *devc;
1524
1525 (void)cb_data;
1526
1527 devc = sdi->priv;
1528 devc->state.state = SIGMA_IDLE;
1529
1530 sr_session_source_remove(sdi->session, 0);
1531
1532 return SR_OK;
1533}
1534
1535SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1536 .name = "asix-sigma",
1537 .longname = "ASIX SIGMA/SIGMA2",
1538 .api_version = 1,
1539 .init = init,
1540 .cleanup = cleanup,
1541 .scan = scan,
1542 .dev_list = dev_list,
1543 .dev_clear = dev_clear,
1544 .config_get = config_get,
1545 .config_set = config_set,
1546 .config_list = config_list,
1547 .dev_open = dev_open,
1548 .dev_close = dev_close,
1549 .dev_acquisition_start = dev_acquisition_start,
1550 .dev_acquisition_stop = dev_acquisition_stop,
1551 .priv = NULL,
1552};
Hardware access and backend lib