]> sigrok.org Git - libsigrok.git/blame_incremental - src/hardware/asix-sigma/asix-sigma.c
projects / libsigrok.git / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
Always save all channels to a session file.
[libsigrok.git] / src / hardware / asix-sigma / asix-sigma.c
... / ...
CommitLineData
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>,
5 * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no>
6 * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no>
7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22/*
23 * ASIX SIGMA/SIGMA2 logic analyzer driver
24 */
25
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <ftdi.h>
29#include <string.h>
30#include <unistd.h>
31#include "libsigrok.h"
32#include "libsigrok-internal.h"
33#include "asix-sigma.h"
34
35#define USB_VENDOR 0xa600
36#define USB_PRODUCT 0xa000
37#define USB_DESCRIPTION "ASIX SIGMA"
38#define USB_VENDOR_NAME "ASIX"
39#define USB_MODEL_NAME "SIGMA"
40
41SR_PRIV struct sr_dev_driver asix_sigma_driver_info;
42static struct sr_dev_driver *di = &asix_sigma_driver_info;
43static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data);
44
45/*
46 * The ASIX Sigma supports arbitrary integer frequency divider in
47 * the 50MHz mode. The divider is in range 1...256 , allowing for
48 * very precise sampling rate selection. This driver supports only
49 * a subset of the sampling rates.
50 */
51static const uint64_t samplerates[] = {
52 SR_KHZ(200), /* div=250 */
53 SR_KHZ(250), /* div=200 */
54 SR_KHZ(500), /* div=100 */
55 SR_MHZ(1), /* div=50 */
56 SR_MHZ(5), /* div=10 */
57 SR_MHZ(10), /* div=5 */
58 SR_MHZ(25), /* div=2 */
59 SR_MHZ(50), /* div=1 */
60 SR_MHZ(100), /* Special FW needed */
61 SR_MHZ(200), /* Special FW needed */
62};
63
64/*
65 * Channel numbers seem to go from 1-16, according to this image:
66 * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg
67 * (the cable has two additional GND pins, and a TI and TO pin)
68 */
69static const char *channel_names[] = {
70 "1", "2", "3", "4", "5", "6", "7", "8",
71 "9", "10", "11", "12", "13", "14", "15", "16",
72};
73
74static const uint32_t drvopts[] = {
75 SR_CONF_LOGIC_ANALYZER,
76};
77
78static const uint32_t devopts[] = {
79 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
80 SR_CONF_LIMIT_SAMPLES | SR_CONF_SET,
81 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
82 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
83 SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET,
84};
85
86static const int32_t trigger_matches[] = {
87 SR_TRIGGER_ZERO,
88 SR_TRIGGER_ONE,
89 SR_TRIGGER_RISING,
90 SR_TRIGGER_FALLING,
91};
92
93static const char *sigma_firmware_files[] = {
94 /* 50 MHz, supports 8 bit fractions */
95 FIRMWARE_DIR "/asix-sigma-50.fw",
96 /* 100 MHz */
97 FIRMWARE_DIR "/asix-sigma-100.fw",
98 /* 200 MHz */
99 FIRMWARE_DIR "/asix-sigma-200.fw",
100 /* Synchronous clock from pin */
101 FIRMWARE_DIR "/asix-sigma-50sync.fw",
102 /* Frequency counter */
103 FIRMWARE_DIR "/asix-sigma-phasor.fw",
104};
105
106static int sigma_read(void *buf, size_t size, struct dev_context *devc)
107{
108 int ret;
109
110 ret = ftdi_read_data(&devc->ftdic, (unsigned char *)buf, size);
111 if (ret < 0) {
112 sr_err("ftdi_read_data failed: %s",
113 ftdi_get_error_string(&devc->ftdic));
114 }
115
116 return ret;
117}
118
119static int sigma_write(void *buf, size_t size, struct dev_context *devc)
120{
121 int ret;
122
123 ret = ftdi_write_data(&devc->ftdic, (unsigned char *)buf, size);
124 if (ret < 0) {
125 sr_err("ftdi_write_data failed: %s",
126 ftdi_get_error_string(&devc->ftdic));
127 } else if ((size_t) ret != size) {
128 sr_err("ftdi_write_data did not complete write.");
129 }
130
131 return ret;
132}
133
134static int sigma_write_register(uint8_t reg, uint8_t *data, size_t len,
135 struct dev_context *devc)
136{
137 size_t i;
138 uint8_t buf[len + 2];
139 int idx = 0;
140
141 buf[idx++] = REG_ADDR_LOW | (reg & 0xf);
142 buf[idx++] = REG_ADDR_HIGH | (reg >> 4);
143
144 for (i = 0; i < len; ++i) {
145 buf[idx++] = REG_DATA_LOW | (data[i] & 0xf);
146 buf[idx++] = REG_DATA_HIGH_WRITE | (data[i] >> 4);
147 }
148
149 return sigma_write(buf, idx, devc);
150}
151
152static int sigma_set_register(uint8_t reg, uint8_t value, struct dev_context *devc)
153{
154 return sigma_write_register(reg, &value, 1, devc);
155}
156
157static int sigma_read_register(uint8_t reg, uint8_t *data, size_t len,
158 struct dev_context *devc)
159{
160 uint8_t buf[3];
161
162 buf[0] = REG_ADDR_LOW | (reg & 0xf);
163 buf[1] = REG_ADDR_HIGH | (reg >> 4);
164 buf[2] = REG_READ_ADDR;
165
166 sigma_write(buf, sizeof(buf), devc);
167
168 return sigma_read(data, len, devc);
169}
170
171static uint8_t sigma_get_register(uint8_t reg, struct dev_context *devc)
172{
173 uint8_t value;
174
175 if (1 != sigma_read_register(reg, &value, 1, devc)) {
176 sr_err("sigma_get_register: 1 byte expected");
177 return 0;
178 }
179
180 return value;
181}
182
183static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
184 struct dev_context *devc)
185{
186 uint8_t buf[] = {
187 REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
188
189 REG_READ_ADDR | NEXT_REG,
190 REG_READ_ADDR | NEXT_REG,
191 REG_READ_ADDR | NEXT_REG,
192 REG_READ_ADDR | NEXT_REG,
193 REG_READ_ADDR | NEXT_REG,
194 REG_READ_ADDR | NEXT_REG,
195 };
196 uint8_t result[6];
197
198 sigma_write(buf, sizeof(buf), devc);
199
200 sigma_read(result, sizeof(result), devc);
201
202 *triggerpos = result[0] | (result[1] << 8) | (result[2] << 16);
203 *stoppos = result[3] | (result[4] << 8) | (result[5] << 16);
204
205 /* Not really sure why this must be done, but according to spec. */
206 if ((--*stoppos & 0x1ff) == 0x1ff)
207 *stoppos -= 64;
208
209 if ((*--triggerpos & 0x1ff) == 0x1ff)
210 *triggerpos -= 64;
211
212 return 1;
213}
214
215static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
216 uint8_t *data, struct dev_context *devc)
217{
218 size_t i;
219 uint8_t buf[4096];
220 int idx = 0;
221
222 /* Send the startchunk. Index start with 1. */
223 buf[0] = startchunk >> 8;
224 buf[1] = startchunk & 0xff;
225 sigma_write_register(WRITE_MEMROW, buf, 2, devc);
226
227 /* Read the DRAM. */
228 buf[idx++] = REG_DRAM_BLOCK;
229 buf[idx++] = REG_DRAM_WAIT_ACK;
230
231 for (i = 0; i < numchunks; ++i) {
232 /* Alternate bit to copy from DRAM to cache. */
233 if (i != (numchunks - 1))
234 buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
235
236 buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
237
238 if (i != (numchunks - 1))
239 buf[idx++] = REG_DRAM_WAIT_ACK;
240 }
241
242 sigma_write(buf, idx, devc);
243
244 return sigma_read(data, numchunks * CHUNK_SIZE, devc);
245}
246
247/* Upload trigger look-up tables to Sigma. */
248static int sigma_write_trigger_lut(struct triggerlut *lut, struct dev_context *devc)
249{
250 int i;
251 uint8_t tmp[2];
252 uint16_t bit;
253
254 /* Transpose the table and send to Sigma. */
255 for (i = 0; i < 16; ++i) {
256 bit = 1 << i;
257
258 tmp[0] = tmp[1] = 0;
259
260 if (lut->m2d[0] & bit)
261 tmp[0] |= 0x01;
262 if (lut->m2d[1] & bit)
263 tmp[0] |= 0x02;
264 if (lut->m2d[2] & bit)
265 tmp[0] |= 0x04;
266 if (lut->m2d[3] & bit)
267 tmp[0] |= 0x08;
268
269 if (lut->m3 & bit)
270 tmp[0] |= 0x10;
271 if (lut->m3s & bit)
272 tmp[0] |= 0x20;
273 if (lut->m4 & bit)
274 tmp[0] |= 0x40;
275
276 if (lut->m0d[0] & bit)
277 tmp[1] |= 0x01;
278 if (lut->m0d[1] & bit)
279 tmp[1] |= 0x02;
280 if (lut->m0d[2] & bit)
281 tmp[1] |= 0x04;
282 if (lut->m0d[3] & bit)
283 tmp[1] |= 0x08;
284
285 if (lut->m1d[0] & bit)
286 tmp[1] |= 0x10;
287 if (lut->m1d[1] & bit)
288 tmp[1] |= 0x20;
289 if (lut->m1d[2] & bit)
290 tmp[1] |= 0x40;
291 if (lut->m1d[3] & bit)
292 tmp[1] |= 0x80;
293
294 sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
295 devc);
296 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
297 }
298
299 /* Send the parameters */
300 sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
301 sizeof(lut->params), devc);
302
303 return SR_OK;
304}
305
306static void clear_helper(void *priv)
307{
308 struct dev_context *devc;
309
310 devc = priv;
311
312 ftdi_deinit(&devc->ftdic);
313}
314
315static int dev_clear(void)
316{
317 return std_dev_clear(di, clear_helper);
318}
319
320static int init(struct sr_context *sr_ctx)
321{
322 return std_init(sr_ctx, di, LOG_PREFIX);
323}
324
325static GSList *scan(GSList *options)
326{
327 struct sr_dev_inst *sdi;
328 struct sr_channel *ch;
329 struct drv_context *drvc;
330 struct dev_context *devc;
331 GSList *devices;
332 struct ftdi_device_list *devlist;
333 char serial_txt[10];
334 uint32_t serial;
335 int ret;
336 unsigned int i;
337
338 (void)options;
339
340 drvc = di->priv;
341
342 devices = NULL;
343
344 devc = g_malloc0(sizeof(struct dev_context));
345
346 ftdi_init(&devc->ftdic);
347
348 /* Look for SIGMAs. */
349
350 if ((ret = ftdi_usb_find_all(&devc->ftdic, &devlist,
351 USB_VENDOR, USB_PRODUCT)) <= 0) {
352 if (ret < 0)
353 sr_err("ftdi_usb_find_all(): %d", ret);
354 goto free;
355 }
356
357 /* Make sure it's a version 1 or 2 SIGMA. */
358 ftdi_usb_get_strings(&devc->ftdic, devlist->dev, NULL, 0, NULL, 0,
359 serial_txt, sizeof(serial_txt));
360 sscanf(serial_txt, "%x", &serial);
361
362 if (serial < 0xa6010000 || serial > 0xa602ffff) {
363 sr_err("Only SIGMA and SIGMA2 are supported "
364 "in this version of libsigrok.");
365 goto free;
366 }
367
368 sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
369
370 devc->cur_samplerate = samplerates[0];
371 devc->period_ps = 0;
372 devc->limit_msec = 0;
373 devc->cur_firmware = -1;
374 devc->num_channels = 0;
375 devc->samples_per_event = 0;
376 devc->capture_ratio = 50;
377 devc->use_triggers = 0;
378
379 /* Register SIGMA device. */
380 sdi = g_malloc0(sizeof(struct sr_dev_inst));
381 sdi->status = SR_ST_INITIALIZING;
382 sdi->vendor = g_strdup(USB_VENDOR_NAME);
383 sdi->model = g_strdup(USB_MODEL_NAME);
384 sdi->driver = di;
385
386 for (i = 0; i < ARRAY_SIZE(channel_names); i++) {
387 ch = sr_channel_new(i, SR_CHANNEL_LOGIC, TRUE,
388 channel_names[i]);
389 sdi->channels = g_slist_append(sdi->channels, ch);
390 }
391
392 devices = g_slist_append(devices, sdi);
393 drvc->instances = g_slist_append(drvc->instances, sdi);
394 sdi->priv = devc;
395
396 /* We will open the device again when we need it. */
397 ftdi_list_free(&devlist);
398
399 return devices;
400
401free:
402 ftdi_deinit(&devc->ftdic);
403 g_free(devc);
404 return NULL;
405}
406
407static GSList *dev_list(void)
408{
409 return ((struct drv_context *)(di->priv))->instances;
410}
411
412/*
413 * Configure the FPGA for bitbang mode.
414 * This sequence is documented in section 2. of the ASIX Sigma programming
415 * manual. This sequence is necessary to configure the FPGA in the Sigma
416 * into Bitbang mode, in which it can be programmed with the firmware.
417 */
418static int sigma_fpga_init_bitbang(struct dev_context *devc)
419{
420 uint8_t suicide[] = {
421 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
422 };
423 uint8_t init_array[] = {
424 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
425 0x01, 0x01,
426 };
427 int i, ret, timeout = 10000;
428 uint8_t data;
429
430 /* Section 2. part 1), do the FPGA suicide. */
431 sigma_write(suicide, sizeof(suicide), devc);
432 sigma_write(suicide, sizeof(suicide), devc);
433 sigma_write(suicide, sizeof(suicide), devc);
434 sigma_write(suicide, sizeof(suicide), devc);
435
436 /* Section 2. part 2), do pulse on D1. */
437 sigma_write(init_array, sizeof(init_array), devc);
438 ftdi_usb_purge_buffers(&devc->ftdic);
439
440 /* Wait until the FPGA asserts D6/INIT_B. */
441 for (i = 0; i < timeout; i++) {
442 ret = sigma_read(&data, 1, devc);
443 if (ret < 0)
444 return ret;
445 /* Test if pin D6 got asserted. */
446 if (data & (1 << 5))
447 return 0;
448 /* The D6 was not asserted yet, wait a bit. */
449 usleep(10000);
450 }
451
452 return SR_ERR_TIMEOUT;
453}
454
455/*
456 * Configure the FPGA for logic-analyzer mode.
457 */
458static int sigma_fpga_init_la(struct dev_context *devc)
459{
460 /* Initialize the logic analyzer mode. */
461 uint8_t logic_mode_start[] = {
462 REG_ADDR_LOW | (READ_ID & 0xf),
463 REG_ADDR_HIGH | (READ_ID >> 8),
464 REG_READ_ADDR, /* Read ID register. */
465
466 REG_ADDR_LOW | (WRITE_TEST & 0xf),
467 REG_DATA_LOW | 0x5,
468 REG_DATA_HIGH_WRITE | 0x5,
469 REG_READ_ADDR, /* Read scratch register. */
470
471 REG_DATA_LOW | 0xa,
472 REG_DATA_HIGH_WRITE | 0xa,
473 REG_READ_ADDR, /* Read scratch register. */
474
475 REG_ADDR_LOW | (WRITE_MODE & 0xf),
476 REG_DATA_LOW | 0x0,
477 REG_DATA_HIGH_WRITE | 0x8,
478 };
479
480 uint8_t result[3];
481 int ret;
482
483 /* Initialize the logic analyzer mode. */
484 sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
485
486 /* Expect a 3 byte reply since we issued three READ requests. */
487 ret = sigma_read(result, 3, devc);
488 if (ret != 3)
489 goto err;
490
491 if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
492 goto err;
493
494 return SR_OK;
495err:
496 sr_err("Configuration failed. Invalid reply received.");
497 return SR_ERR;
498}
499
500/*
501 * Read the firmware from a file and transform it into a series of bitbang
502 * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
503 * by the caller of this function.
504 */
505static int sigma_fw_2_bitbang(const char *filename,
506 uint8_t **bb_cmd, gsize *bb_cmd_size)
507{
508 GMappedFile *file;
509 GError *error;
510 gsize i, file_size, bb_size;
511 gchar *firmware;
512 uint8_t *bb_stream, *bbs;
513 uint32_t imm;
514 int bit, v;
515 int ret = SR_OK;
516
517 /*
518 * Map the file and make the mapped buffer writable.
519 * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
520 * will be modified. It will not be modified until someone uses
521 * g_file_set_contents() on it.
522 */
523 error = NULL;
524 file = g_mapped_file_new(filename, TRUE, &error);
525 g_assert_no_error(error);
526
527 file_size = g_mapped_file_get_length(file);
528 firmware = g_mapped_file_get_contents(file);
529 g_assert(firmware);
530
531 /* Weird magic transformation below, I have no idea what it does. */
532 imm = 0x3f6df2ab;
533 for (i = 0; i < file_size; i++) {
534 imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
535 firmware[i] ^= imm & 0xff;
536 }
537
538 /*
539 * Now that the firmware is "transformed", we will transcribe the
540 * firmware blob into a sequence of toggles of the Dx wires. This
541 * sequence will be fed directly into the Sigma, which must be in
542 * the FPGA bitbang programming mode.
543 */
544
545 /* Each bit of firmware is transcribed as two toggles of Dx wires. */
546 bb_size = file_size * 8 * 2;
547 bb_stream = (uint8_t *)g_try_malloc(bb_size);
548 if (!bb_stream) {
549 sr_err("%s: Failed to allocate bitbang stream", __func__);
550 ret = SR_ERR_MALLOC;
551 goto exit;
552 }
553
554 bbs = bb_stream;
555 for (i = 0; i < file_size; i++) {
556 for (bit = 7; bit >= 0; bit--) {
557 v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
558 *bbs++ = v | 0x01;
559 *bbs++ = v;
560 }
561 }
562
563 /* The transformation completed successfully, return the result. */
564 *bb_cmd = bb_stream;
565 *bb_cmd_size = bb_size;
566
567exit:
568 g_mapped_file_unref(file);
569 return ret;
570}
571
572static int upload_firmware(int firmware_idx, struct dev_context *devc)
573{
574 int ret;
575 unsigned char *buf;
576 unsigned char pins;
577 size_t buf_size;
578 const char *firmware = sigma_firmware_files[firmware_idx];
579 struct ftdi_context *ftdic = &devc->ftdic;
580
581 /* Make sure it's an ASIX SIGMA. */
582 ret = ftdi_usb_open_desc(ftdic, USB_VENDOR, USB_PRODUCT,
583 USB_DESCRIPTION, NULL);
584 if (ret < 0) {
585 sr_err("ftdi_usb_open failed: %s",
586 ftdi_get_error_string(ftdic));
587 return 0;
588 }
589
590 ret = ftdi_set_bitmode(ftdic, 0xdf, BITMODE_BITBANG);
591 if (ret < 0) {
592 sr_err("ftdi_set_bitmode failed: %s",
593 ftdi_get_error_string(ftdic));
594 return 0;
595 }
596
597 /* Four times the speed of sigmalogan - Works well. */
598 ret = ftdi_set_baudrate(ftdic, 750000);
599 if (ret < 0) {
600 sr_err("ftdi_set_baudrate failed: %s",
601 ftdi_get_error_string(ftdic));
602 return 0;
603 }
604
605 /* Initialize the FPGA for firmware upload. */
606 ret = sigma_fpga_init_bitbang(devc);
607 if (ret)
608 return ret;
609
610 /* Prepare firmware. */
611 ret = sigma_fw_2_bitbang(firmware, &buf, &buf_size);
612 if (ret != SR_OK) {
613 sr_err("An error occured while reading the firmware: %s",
614 firmware);
615 return ret;
616 }
617
618 /* Upload firmare. */
619 sr_info("Uploading firmware file '%s'.", firmware);
620 sigma_write(buf, buf_size, devc);
621
622 g_free(buf);
623
624 ret = ftdi_set_bitmode(ftdic, 0x00, BITMODE_RESET);
625 if (ret < 0) {
626 sr_err("ftdi_set_bitmode failed: %s",
627 ftdi_get_error_string(ftdic));
628 return SR_ERR;
629 }
630
631 ftdi_usb_purge_buffers(ftdic);
632
633 /* Discard garbage. */
634 while (sigma_read(&pins, 1, devc) == 1)
635 ;
636
637 /* Initialize the FPGA for logic-analyzer mode. */
638 ret = sigma_fpga_init_la(devc);
639 if (ret != SR_OK)
640 return ret;
641
642 devc->cur_firmware = firmware_idx;
643
644 sr_info("Firmware uploaded.");
645
646 return SR_OK;
647}
648
649static int dev_open(struct sr_dev_inst *sdi)
650{
651 struct dev_context *devc;
652 int ret;
653
654 devc = sdi->priv;
655
656 /* Make sure it's an ASIX SIGMA. */
657 if ((ret = ftdi_usb_open_desc(&devc->ftdic,
658 USB_VENDOR, USB_PRODUCT, USB_DESCRIPTION, NULL)) < 0) {
659
660 sr_err("ftdi_usb_open failed: %s",
661 ftdi_get_error_string(&devc->ftdic));
662
663 return 0;
664 }
665
666 sdi->status = SR_ST_ACTIVE;
667
668 return SR_OK;
669}
670
671static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
672{
673 struct dev_context *devc;
674 unsigned int i;
675 int ret;
676
677 devc = sdi->priv;
678 ret = SR_OK;
679
680 for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
681 if (samplerates[i] == samplerate)
682 break;
683 }
684 if (samplerates[i] == 0)
685 return SR_ERR_SAMPLERATE;
686
687 if (samplerate <= SR_MHZ(50)) {
688 ret = upload_firmware(0, devc);
689 devc->num_channels = 16;
690 } else if (samplerate == SR_MHZ(100)) {
691 ret = upload_firmware(1, devc);
692 devc->num_channels = 8;
693 } else if (samplerate == SR_MHZ(200)) {
694 ret = upload_firmware(2, devc);
695 devc->num_channels = 4;
696 }
697
698 if (ret == SR_OK) {
699 devc->cur_samplerate = samplerate;
700 devc->period_ps = 1000000000000ULL / samplerate;
701 devc->samples_per_event = 16 / devc->num_channels;
702 devc->state.state = SIGMA_IDLE;
703 }
704
705 return ret;
706}
707
708/*
709 * In 100 and 200 MHz mode, only a single pin rising/falling can be
710 * set as trigger. In other modes, two rising/falling triggers can be set,
711 * in addition to value/mask trigger for any number of channels.
712 *
713 * The Sigma supports complex triggers using boolean expressions, but this
714 * has not been implemented yet.
715 */
716static int convert_trigger(const struct sr_dev_inst *sdi)
717{
718 struct dev_context *devc;
719 struct sr_trigger *trigger;
720 struct sr_trigger_stage *stage;
721 struct sr_trigger_match *match;
722 const GSList *l, *m;
723 int channelbit, trigger_set;
724
725 devc = sdi->priv;
726 memset(&devc->trigger, 0, sizeof(struct sigma_trigger));
727 if (!(trigger = sr_session_trigger_get(sdi->session)))
728 return SR_OK;
729
730 trigger_set = 0;
731 for (l = trigger->stages; l; l = l->next) {
732 stage = l->data;
733 for (m = stage->matches; m; m = m->next) {
734 match = m->data;
735 if (!match->channel->enabled)
736 /* Ignore disabled channels with a trigger. */
737 continue;
738 channelbit = 1 << (match->channel->index);
739 if (devc->cur_samplerate >= SR_MHZ(100)) {
740 /* Fast trigger support. */
741 if (trigger_set) {
742 sr_err("Only a single pin trigger is "
743 "supported in 100 and 200MHz mode.");
744 return SR_ERR;
745 }
746 if (match->match == SR_TRIGGER_FALLING)
747 devc->trigger.fallingmask |= channelbit;
748 else if (match->match == SR_TRIGGER_RISING)
749 devc->trigger.risingmask |= channelbit;
750 else {
751 sr_err("Only rising/falling trigger is "
752 "supported in 100 and 200MHz mode.");
753 return SR_ERR;
754 }
755
756 ++trigger_set;
757 } else {
758 /* Simple trigger support (event). */
759 if (match->match == SR_TRIGGER_ONE) {
760 devc->trigger.simplevalue |= channelbit;
761 devc->trigger.simplemask |= channelbit;
762 }
763 else if (match->match == SR_TRIGGER_ZERO) {
764 devc->trigger.simplevalue &= ~channelbit;
765 devc->trigger.simplemask |= channelbit;
766 }
767 else if (match->match == SR_TRIGGER_FALLING) {
768 devc->trigger.fallingmask |= channelbit;
769 ++trigger_set;
770 }
771 else if (match->match == SR_TRIGGER_RISING) {
772 devc->trigger.risingmask |= channelbit;
773 ++trigger_set;
774 }
775
776 /*
777 * Actually, Sigma supports 2 rising/falling triggers,
778 * but they are ORed and the current trigger syntax
779 * does not permit ORed triggers.
780 */
781 if (trigger_set > 1) {
782 sr_err("Only 1 rising/falling trigger "
783 "is supported.");
784 return SR_ERR;
785 }
786 }
787 }
788 }
789
790
791 return SR_OK;
792}
793
794static int dev_close(struct sr_dev_inst *sdi)
795{
796 struct dev_context *devc;
797
798 devc = sdi->priv;
799
800 /* TODO */
801 if (sdi->status == SR_ST_ACTIVE)
802 ftdi_usb_close(&devc->ftdic);
803
804 sdi->status = SR_ST_INACTIVE;
805
806 return SR_OK;
807}
808
809static int cleanup(void)
810{
811 return dev_clear();
812}
813
814static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
815 const struct sr_channel_group *cg)
816{
817 struct dev_context *devc;
818
819 (void)cg;
820
821 if (!sdi)
822 return SR_ERR;
823 devc = sdi->priv;
824
825 switch (key) {
826 case SR_CONF_SAMPLERATE:
827 *data = g_variant_new_uint64(devc->cur_samplerate);
828 break;
829 case SR_CONF_LIMIT_MSEC:
830 *data = g_variant_new_uint64(devc->limit_msec);
831 break;
832 case SR_CONF_CAPTURE_RATIO:
833 *data = g_variant_new_uint64(devc->capture_ratio);
834 break;
835 default:
836 return SR_ERR_NA;
837 }
838
839 return SR_OK;
840}
841
842static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
843 const struct sr_channel_group *cg)
844{
845 struct dev_context *devc;
846 uint64_t tmp;
847 int ret;
848
849 (void)cg;
850
851 if (sdi->status != SR_ST_ACTIVE)
852 return SR_ERR_DEV_CLOSED;
853
854 devc = sdi->priv;
855
856 ret = SR_OK;
857 switch (key) {
858 case SR_CONF_SAMPLERATE:
859 ret = set_samplerate(sdi, g_variant_get_uint64(data));
860 break;
861 case SR_CONF_LIMIT_MSEC:
862 tmp = g_variant_get_uint64(data);
863 if (tmp > 0)
864 devc->limit_msec = g_variant_get_uint64(data);
865 else
866 ret = SR_ERR;
867 break;
868 case SR_CONF_LIMIT_SAMPLES:
869 tmp = g_variant_get_uint64(data);
870 devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
871 break;
872 case SR_CONF_CAPTURE_RATIO:
873 tmp = g_variant_get_uint64(data);
874 if (tmp <= 100)
875 devc->capture_ratio = tmp;
876 else
877 ret = SR_ERR;
878 break;
879 default:
880 ret = SR_ERR_NA;
881 }
882
883 return ret;
884}
885
886static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
887 const struct sr_channel_group *cg)
888{
889 GVariant *gvar;
890 GVariantBuilder gvb;
891
892 (void)sdi;
893 (void)cg;
894
895 switch (key) {
896 case SR_CONF_DEVICE_OPTIONS:
897 if (!sdi)
898 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
899 drvopts, ARRAY_SIZE(drvopts), sizeof(uint32_t));
900 else
901 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
902 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
903 break;
904 case SR_CONF_SAMPLERATE:
905 g_variant_builder_init(&gvb, G_VARIANT_TYPE("a{sv}"));
906 gvar = g_variant_new_fixed_array(G_VARIANT_TYPE("t"), samplerates,
907 ARRAY_SIZE(samplerates), sizeof(uint64_t));
908 g_variant_builder_add(&gvb, "{sv}", "samplerates", gvar);
909 *data = g_variant_builder_end(&gvb);
910 break;
911 case SR_CONF_TRIGGER_MATCH:
912 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_INT32,
913 trigger_matches, ARRAY_SIZE(trigger_matches),
914 sizeof(int32_t));
915 break;
916 default:
917 return SR_ERR_NA;
918 }
919
920 return SR_OK;
921}
922
923/* Software trigger to determine exact trigger position. */
924static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
925 struct sigma_trigger *t)
926{
927 int i;
928 uint16_t sample = 0;
929
930 for (i = 0; i < 8; ++i) {
931 if (i > 0)
932 last_sample = sample;
933 sample = samples[2 * i] | (samples[2 * i + 1] << 8);
934
935 /* Simple triggers. */
936 if ((sample & t->simplemask) != t->simplevalue)
937 continue;
938
939 /* Rising edge. */
940 if (((last_sample & t->risingmask) != 0) ||
941 ((sample & t->risingmask) != t->risingmask))
942 continue;
943
944 /* Falling edge. */
945 if ((last_sample & t->fallingmask) != t->fallingmask ||
946 (sample & t->fallingmask) != 0)
947 continue;
948
949 break;
950 }
951
952 /* If we did not match, return original trigger pos. */
953 return i & 0x7;
954}
955
956
957/*
958 * Return the timestamp of "DRAM cluster".
959 */
960static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
961{
962 return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
963}
964
965static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
966 unsigned int events_in_cluster,
967 unsigned int triggered,
968 struct sr_dev_inst *sdi)
969{
970 struct dev_context *devc = sdi->priv;
971 struct sigma_state *ss = &devc->state;
972 struct sr_datafeed_packet packet;
973 struct sr_datafeed_logic logic;
974 uint16_t tsdiff, ts;
975 uint8_t samples[2048];
976 unsigned int i;
977
978 ts = sigma_dram_cluster_ts(dram_cluster);
979 tsdiff = ts - ss->lastts;
980 ss->lastts = ts;
981
982 packet.type = SR_DF_LOGIC;
983 packet.payload = &logic;
984 logic.unitsize = 2;
985 logic.data = samples;
986
987 /*
988 * First of all, send Sigrok a copy of the last sample from
989 * previous cluster as many times as needed to make up for
990 * the differential characteristics of data we get from the
991 * Sigma. Sigrok needs one sample of data per period.
992 *
993 * One DRAM cluster contains a timestamp and seven samples,
994 * the units of timestamp are "devc->period_ps" , the first
995 * sample in the cluster happens at the time of the timestamp
996 * and the remaining samples happen at timestamp +1...+6 .
997 */
998 for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
999 i = ts % 1024;
1000 samples[2 * i + 0] = ss->lastsample & 0xff;
1001 samples[2 * i + 1] = ss->lastsample >> 8;
1002
1003 /*
1004 * If we have 1024 samples ready or we're at the
1005 * end of submitting the padding samples, submit
1006 * the packet to Sigrok.
1007 */
1008 if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
1009 logic.length = (i + 1) * logic.unitsize;
1010 sr_session_send(sdi, &packet);
1011 }
1012 }
1013
1014 /*
1015 * Parse the samples in current cluster and prepare them
1016 * to be submitted to Sigrok.
1017 */
1018 for (i = 0; i < events_in_cluster; i++) {
1019 samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
1020 samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
1021 }
1022
1023 /* Send data up to trigger point (if triggered). */
1024 int trigger_offset = 0;
1025 if (triggered) {
1026 /*
1027 * Trigger is not always accurate to sample because of
1028 * pipeline delay. However, it always triggers before
1029 * the actual event. We therefore look at the next
1030 * samples to pinpoint the exact position of the trigger.
1031 */
1032 trigger_offset = get_trigger_offset(samples,
1033 ss->lastsample, &devc->trigger);
1034
1035 if (trigger_offset > 0) {
1036 packet.type = SR_DF_LOGIC;
1037 logic.length = trigger_offset * logic.unitsize;
1038 sr_session_send(sdi, &packet);
1039 events_in_cluster -= trigger_offset;
1040 }
1041
1042 /* Only send trigger if explicitly enabled. */
1043 if (devc->use_triggers) {
1044 packet.type = SR_DF_TRIGGER;
1045 sr_session_send(sdi, &packet);
1046 }
1047 }
1048
1049 if (events_in_cluster > 0) {
1050 packet.type = SR_DF_LOGIC;
1051 logic.length = events_in_cluster * logic.unitsize;
1052 logic.data = samples + (trigger_offset * logic.unitsize);
1053 sr_session_send(sdi, &packet);
1054 }
1055
1056 ss->lastsample =
1057 samples[2 * (events_in_cluster - 1) + 0] |
1058 (samples[2 * (events_in_cluster - 1) + 1] << 8);
1059
1060}
1061
1062/*
1063 * Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
1064 * Each event is 20ns apart, and can contain multiple samples.
1065 *
1066 * For 200 MHz, events contain 4 samples for each channel, spread 5 ns apart.
1067 * For 100 MHz, events contain 2 samples for each channel, spread 10 ns apart.
1068 * For 50 MHz and below, events contain one sample for each channel,
1069 * spread 20 ns apart.
1070 */
1071static int decode_chunk_ts(struct sigma_dram_line *dram_line,
1072 uint16_t events_in_line,
1073 uint32_t trigger_event,
1074 struct sr_dev_inst *sdi)
1075{
1076 struct sigma_dram_cluster *dram_cluster;
1077 struct dev_context *devc = sdi->priv;
1078 unsigned int clusters_in_line =
1079 (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
1080 unsigned int events_in_cluster;
1081 unsigned int i;
1082 uint32_t trigger_cluster = ~0, triggered = 0;
1083
1084 /* Check if trigger is in this chunk. */
1085 if (trigger_event < (64 * 7)) {
1086 if (devc->cur_samplerate <= SR_MHZ(50)) {
1087 trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
1088 trigger_event);
1089 }
1090
1091 /* Find in which cluster the trigger occured. */
1092 trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
1093 }
1094
1095 /* For each full DRAM cluster. */
1096 for (i = 0; i < clusters_in_line; i++) {
1097 dram_cluster = &dram_line->cluster[i];
1098
1099 /* The last cluster might not be full. */
1100 if ((i == clusters_in_line - 1) &&
1101 (events_in_line % EVENTS_PER_CLUSTER)) {
1102 events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
1103 } else {
1104 events_in_cluster = EVENTS_PER_CLUSTER;
1105 }
1106
1107 triggered = (i == trigger_cluster);
1108 sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
1109 triggered, sdi);
1110 }
1111
1112 return SR_OK;
1113}
1114
1115static int download_capture(struct sr_dev_inst *sdi)
1116{
1117 struct dev_context *devc = sdi->priv;
1118 const uint32_t chunks_per_read = 32;
1119 struct sigma_dram_line *dram_line;
1120 int bufsz;
1121 uint32_t stoppos, triggerpos;
1122 struct sr_datafeed_packet packet;
1123 uint8_t modestatus;
1124
1125 uint32_t i;
1126 uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
1127 uint32_t dl_events_in_line = 64 * 7;
1128 uint32_t trg_line = ~0, trg_event = ~0;
1129
1130 dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
1131 if (!dram_line)
1132 return FALSE;
1133
1134 sr_info("Downloading sample data.");
1135
1136 /* Stop acquisition. */
1137 sigma_set_register(WRITE_MODE, 0x11, devc);
1138
1139 /* Set SDRAM Read Enable. */
1140 sigma_set_register(WRITE_MODE, 0x02, devc);
1141
1142 /* Get the current position. */
1143 sigma_read_pos(&stoppos, &triggerpos, devc);
1144
1145 /* Check if trigger has fired. */
1146 modestatus = sigma_get_register(READ_MODE, devc);
1147 if (modestatus & 0x20) {
1148 trg_line = triggerpos >> 9;
1149 trg_event = triggerpos & 0x1ff;
1150 }
1151
1152 /*
1153 * Determine how many 1024b "DRAM lines" do we need to read from the
1154 * Sigma so we have a complete set of samples. Note that the last
1155 * line can be only partial, containing less than 64 clusters.
1156 */
1157 dl_lines_total = (stoppos >> 9) + 1;
1158
1159 dl_lines_done = 0;
1160
1161 while (dl_lines_total > dl_lines_done) {
1162 /* We can download only up-to 32 DRAM lines in one go! */
1163 dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
1164
1165 bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
1166 (uint8_t *)dram_line, devc);
1167 /* TODO: Check bufsz. For now, just avoid compiler warnings. */
1168 (void)bufsz;
1169
1170 /* This is the first DRAM line, so find the initial timestamp. */
1171 if (dl_lines_done == 0) {
1172 devc->state.lastts =
1173 sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
1174 devc->state.lastsample = 0;
1175 }
1176
1177 for (i = 0; i < dl_lines_curr; i++) {
1178 uint32_t trigger_event = ~0;
1179 /* The last "DRAM line" can be only partially full. */
1180 if (dl_lines_done + i == dl_lines_total - 1)
1181 dl_events_in_line = stoppos & 0x1ff;
1182
1183 /* Test if the trigger happened on this line. */
1184 if (dl_lines_done + i == trg_line)
1185 trigger_event = trg_event;
1186
1187 decode_chunk_ts(dram_line + i, dl_events_in_line,
1188 trigger_event, sdi);
1189 }
1190
1191 dl_lines_done += dl_lines_curr;
1192 }
1193
1194 /* All done. */
1195 packet.type = SR_DF_END;
1196 sr_session_send(sdi, &packet);
1197
1198 dev_acquisition_stop(sdi, sdi);
1199
1200 g_free(dram_line);
1201
1202 return TRUE;
1203}
1204
1205/*
1206 * Handle the Sigma when in CAPTURE mode. This function checks:
1207 * - Sampling time ended
1208 * - DRAM capacity overflow
1209 * This function triggers download of the samples from Sigma
1210 * in case either of the above conditions is true.
1211 */
1212static int sigma_capture_mode(struct sr_dev_inst *sdi)
1213{
1214 struct dev_context *devc = sdi->priv;
1215
1216 uint64_t running_msec;
1217 struct timeval tv;
1218
1219 uint32_t stoppos, triggerpos;
1220
1221 /* Check if the selected sampling duration passed. */
1222 gettimeofday(&tv, 0);
1223 running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
1224 (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
1225 if (running_msec >= devc->limit_msec)
1226 return download_capture(sdi);
1227
1228 /* Get the position in DRAM to which the FPGA is writing now. */
1229 sigma_read_pos(&stoppos, &triggerpos, devc);
1230 /* Test if DRAM is full and if so, download the data. */
1231 if ((stoppos >> 9) == 32767)
1232 return download_capture(sdi);
1233
1234 return TRUE;
1235}
1236
1237static int receive_data(int fd, int revents, void *cb_data)
1238{
1239 struct sr_dev_inst *sdi;
1240 struct dev_context *devc;
1241
1242 (void)fd;
1243 (void)revents;
1244
1245 sdi = cb_data;
1246 devc = sdi->priv;
1247
1248 if (devc->state.state == SIGMA_IDLE)
1249 return TRUE;
1250
1251 if (devc->state.state == SIGMA_CAPTURE)
1252 return sigma_capture_mode(sdi);
1253
1254 return TRUE;
1255}
1256
1257/* Build a LUT entry used by the trigger functions. */
1258static void build_lut_entry(uint16_t value, uint16_t mask, uint16_t *entry)
1259{
1260 int i, j, k, bit;
1261
1262 /* For each quad channel. */
1263 for (i = 0; i < 4; ++i) {
1264 entry[i] = 0xffff;
1265
1266 /* For each bit in LUT. */
1267 for (j = 0; j < 16; ++j)
1268
1269 /* For each channel in quad. */
1270 for (k = 0; k < 4; ++k) {
1271 bit = 1 << (i * 4 + k);
1272
1273 /* Set bit in entry */
1274 if ((mask & bit) &&
1275 ((!(value & bit)) !=
1276 (!(j & (1 << k)))))
1277 entry[i] &= ~(1 << j);
1278 }
1279 }
1280}
1281
1282/* Add a logical function to LUT mask. */
1283static void add_trigger_function(enum triggerop oper, enum triggerfunc func,
1284 int index, int neg, uint16_t *mask)
1285{
1286 int i, j;
1287 int x[2][2], tmp, a, b, aset, bset, rset;
1288
1289 memset(x, 0, 4 * sizeof(int));
1290
1291 /* Trigger detect condition. */
1292 switch (oper) {
1293 case OP_LEVEL:
1294 x[0][1] = 1;
1295 x[1][1] = 1;
1296 break;
1297 case OP_NOT:
1298 x[0][0] = 1;
1299 x[1][0] = 1;
1300 break;
1301 case OP_RISE:
1302 x[0][1] = 1;
1303 break;
1304 case OP_FALL:
1305 x[1][0] = 1;
1306 break;
1307 case OP_RISEFALL:
1308 x[0][1] = 1;
1309 x[1][0] = 1;
1310 break;
1311 case OP_NOTRISE:
1312 x[1][1] = 1;
1313 x[0][0] = 1;
1314 x[1][0] = 1;
1315 break;
1316 case OP_NOTFALL:
1317 x[1][1] = 1;
1318 x[0][0] = 1;
1319 x[0][1] = 1;
1320 break;
1321 case OP_NOTRISEFALL:
1322 x[1][1] = 1;
1323 x[0][0] = 1;
1324 break;
1325 }
1326
1327 /* Transpose if neg is set. */
1328 if (neg) {
1329 for (i = 0; i < 2; ++i) {
1330 for (j = 0; j < 2; ++j) {
1331 tmp = x[i][j];
1332 x[i][j] = x[1-i][1-j];
1333 x[1-i][1-j] = tmp;
1334 }
1335 }
1336 }
1337
1338 /* Update mask with function. */
1339 for (i = 0; i < 16; ++i) {
1340 a = (i >> (2 * index + 0)) & 1;
1341 b = (i >> (2 * index + 1)) & 1;
1342
1343 aset = (*mask >> i) & 1;
1344 bset = x[b][a];
1345
1346 rset = 0;
1347 if (func == FUNC_AND || func == FUNC_NAND)
1348 rset = aset & bset;
1349 else if (func == FUNC_OR || func == FUNC_NOR)
1350 rset = aset | bset;
1351 else if (func == FUNC_XOR || func == FUNC_NXOR)
1352 rset = aset ^ bset;
1353
1354 if (func == FUNC_NAND || func == FUNC_NOR || func == FUNC_NXOR)
1355 rset = !rset;
1356
1357 *mask &= ~(1 << i);
1358
1359 if (rset)
1360 *mask |= 1 << i;
1361 }
1362}
1363
1364/*
1365 * Build trigger LUTs used by 50 MHz and lower sample rates for supporting
1366 * simple pin change and state triggers. Only two transitions (rise/fall) can be
1367 * set at any time, but a full mask and value can be set (0/1).
1368 */
1369static int build_basic_trigger(struct triggerlut *lut, struct dev_context *devc)
1370{
1371 int i,j;
1372 uint16_t masks[2] = { 0, 0 };
1373
1374 memset(lut, 0, sizeof(struct triggerlut));
1375
1376 /* Contant for simple triggers. */
1377 lut->m4 = 0xa000;
1378
1379 /* Value/mask trigger support. */
1380 build_lut_entry(devc->trigger.simplevalue, devc->trigger.simplemask,
1381 lut->m2d);
1382
1383 /* Rise/fall trigger support. */
1384 for (i = 0, j = 0; i < 16; ++i) {
1385 if (devc->trigger.risingmask & (1 << i) ||
1386 devc->trigger.fallingmask & (1 << i))
1387 masks[j++] = 1 << i;
1388 }
1389
1390 build_lut_entry(masks[0], masks[0], lut->m0d);
1391 build_lut_entry(masks[1], masks[1], lut->m1d);
1392
1393 /* Add glue logic */
1394 if (masks[0] || masks[1]) {
1395 /* Transition trigger. */
1396 if (masks[0] & devc->trigger.risingmask)
1397 add_trigger_function(OP_RISE, FUNC_OR, 0, 0, &lut->m3);
1398 if (masks[0] & devc->trigger.fallingmask)
1399 add_trigger_function(OP_FALL, FUNC_OR, 0, 0, &lut->m3);
1400 if (masks[1] & devc->trigger.risingmask)
1401 add_trigger_function(OP_RISE, FUNC_OR, 1, 0, &lut->m3);
1402 if (masks[1] & devc->trigger.fallingmask)
1403 add_trigger_function(OP_FALL, FUNC_OR, 1, 0, &lut->m3);
1404 } else {
1405 /* Only value/mask trigger. */
1406 lut->m3 = 0xffff;
1407 }
1408
1409 /* Triggertype: event. */
1410 lut->params.selres = 3;
1411
1412 return SR_OK;
1413}
1414
1415static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
1416{
1417 struct dev_context *devc;
1418 struct clockselect_50 clockselect;
1419 int frac, triggerpin, ret;
1420 uint8_t triggerselect = 0;
1421 struct triggerinout triggerinout_conf;
1422 struct triggerlut lut;
1423
1424 if (sdi->status != SR_ST_ACTIVE)
1425 return SR_ERR_DEV_CLOSED;
1426
1427 devc = sdi->priv;
1428
1429 if (convert_trigger(sdi) != SR_OK) {
1430 sr_err("Failed to configure triggers.");
1431 return SR_ERR;
1432 }
1433
1434 /* If the samplerate has not been set, default to 200 kHz. */
1435 if (devc->cur_firmware == -1) {
1436 if ((ret = set_samplerate(sdi, SR_KHZ(200))) != SR_OK)
1437 return ret;
1438 }
1439
1440 /* Enter trigger programming mode. */
1441 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x20, devc);
1442
1443 /* 100 and 200 MHz mode. */
1444 if (devc->cur_samplerate >= SR_MHZ(100)) {
1445 sigma_set_register(WRITE_TRIGGER_SELECT1, 0x81, devc);
1446
1447 /* Find which pin to trigger on from mask. */
1448 for (triggerpin = 0; triggerpin < 8; ++triggerpin)
1449 if ((devc->trigger.risingmask | devc->trigger.fallingmask) &
1450 (1 << triggerpin))
1451 break;
1452
1453 /* Set trigger pin and light LED on trigger. */
1454 triggerselect = (1 << LEDSEL1) | (triggerpin & 0x7);
1455
1456 /* Default rising edge. */
1457 if (devc->trigger.fallingmask)
1458 triggerselect |= 1 << 3;
1459
1460 /* All other modes. */
1461 } else if (devc->cur_samplerate <= SR_MHZ(50)) {
1462 build_basic_trigger(&lut, devc);
1463
1464 sigma_write_trigger_lut(&lut, devc);
1465
1466 triggerselect = (1 << LEDSEL1) | (1 << LEDSEL0);
1467 }
1468
1469 /* Setup trigger in and out pins to default values. */
1470 memset(&triggerinout_conf, 0, sizeof(struct triggerinout));
1471 triggerinout_conf.trgout_bytrigger = 1;
1472 triggerinout_conf.trgout_enable = 1;
1473
1474 sigma_write_register(WRITE_TRIGGER_OPTION,
1475 (uint8_t *) &triggerinout_conf,
1476 sizeof(struct triggerinout), devc);
1477
1478 /* Go back to normal mode. */
1479 sigma_set_register(WRITE_TRIGGER_SELECT1, triggerselect, devc);
1480
1481 /* Set clock select register. */
1482 if (devc->cur_samplerate == SR_MHZ(200))
1483 /* Enable 4 channels. */
1484 sigma_set_register(WRITE_CLOCK_SELECT, 0xf0, devc);
1485 else if (devc->cur_samplerate == SR_MHZ(100))
1486 /* Enable 8 channels. */
1487 sigma_set_register(WRITE_CLOCK_SELECT, 0x00, devc);
1488 else {
1489 /*
1490 * 50 MHz mode (or fraction thereof). Any fraction down to
1491 * 50 MHz / 256 can be used, but is not supported by sigrok API.
1492 */
1493 frac = SR_MHZ(50) / devc->cur_samplerate - 1;
1494
1495 clockselect.async = 0;
1496 clockselect.fraction = frac;
1497 clockselect.disabled_channels = 0;
1498
1499 sigma_write_register(WRITE_CLOCK_SELECT,
1500 (uint8_t *) &clockselect,
1501 sizeof(clockselect), devc);
1502 }
1503
1504 /* Setup maximum post trigger time. */
1505 sigma_set_register(WRITE_POST_TRIGGER,
1506 (devc->capture_ratio * 255) / 100, devc);
1507
1508 /* Start acqusition. */
1509 gettimeofday(&devc->start_tv, 0);
1510 sigma_set_register(WRITE_MODE, 0x0d, devc);
1511
1512 devc->cb_data = cb_data;
1513
1514 /* Send header packet to the session bus. */
1515 std_session_send_df_header(sdi, LOG_PREFIX);
1516
1517 /* Add capture source. */
1518 sr_session_source_add(sdi->session, 0, G_IO_IN, 10, receive_data, (void *)sdi);
1519
1520 devc->state.state = SIGMA_CAPTURE;
1521
1522 return SR_OK;
1523}
1524
1525static int dev_acquisition_stop(struct sr_dev_inst *sdi, void *cb_data)
1526{
1527 struct dev_context *devc;
1528
1529 (void)cb_data;
1530
1531 devc = sdi->priv;
1532 devc->state.state = SIGMA_IDLE;
1533
1534 sr_session_source_remove(sdi->session, 0);
1535
1536 return SR_OK;
1537}
1538
1539SR_PRIV struct sr_dev_driver asix_sigma_driver_info = {
1540 .name = "asix-sigma",
1541 .longname = "ASIX SIGMA/SIGMA2",
1542 .api_version = 1,
1543 .init = init,
1544 .cleanup = cleanup,
1545 .scan = scan,
1546 .dev_list = dev_list,
1547 .dev_clear = dev_clear,
1548 .config_get = config_get,
1549 .config_set = config_set,
1550 .config_list = config_list,
1551 .dev_open = dev_open,
1552 .dev_close = dev_close,
1553 .dev_acquisition_start = dev_acquisition_start,
1554 .dev_acquisition_stop = dev_acquisition_stop,
1555 .priv = NULL,
1556};
Hardware access and backend lib